Nzenwata Uchenna J et al., GJAI, 2019; 1:5

INTRODUCTION This paper discusses the original purposes of the technology, how they have been The word transputer is a derivative name from the addressed over the intervening past years, the Computer. The transputer was architectural designs and network. It also conceived of as a building block for electronic emphasizes the factors that promoted the effacing systems comprising a , memory and a of and the Restoration movement of communication system. Large systems were to be transputer. constructed from collections of transputers, each running a program and communicating with other The study was carried out by performing in-depth transputers (Quora, n.). study on transputer literatures. The Inmos transputer was a British-designed, THE TRANSPUTER TECHNOLOGY DRIFT novel parallel architecture from Si according to the early1980s. The transputer was unique in that (Fox, Williams, and Messina, 2014), the each processor had a built-in simple operating transputer has drawn much attention among system, memory and four high speed (20 Mbit/s researchers and design engineers, due its novel full duplex) bi-directional serial links. The architectural features and excellent performance. transputer is essentially a computer system on a (Sheen, Allen, Ripke, and Woo, 1998), stated that chip. The links on the transputer allow connection the Inmos transputer device range, which started to up to four other transputers or peripherals such with the T414 in 1983, was continued with a as video graphics, floppy and hard disc drives, series: the 16-bit T212, T222 and T225. The 32 bit Ethernet networking and standard RS-232 serial line was extended with the T425, which ran with a ports (Jaros, Ohlidal and Dvorak, 2005). faster processor clock, more internal memory and The rationale behind the design of the transputer also improved the instruction set and debug came from the point-to-point connection architecture. The T800, announced around 1987, architecture of the Modular-One computer and the included a formally verified IEEE conformant work of Tony Hoare (of QuickSort fame) on Floating Point Unit (FPU) (quite rare for the period) Communication between Sequential Processes. and was developed soon after the release of the His seminal paper led to the design of the T414. Transputer and the parallel programming It was followed by the T801 and T805, introducing language Occam by David May. Starting in early among other things the improved software debug 1981 David May designed the Transputer and the also seen on the T425. The M212 was an early novel Occam language and compiler. It was not trial of an Application Specific Standard Part until 1985 that the first prototype Transputers (ASSP): an MFM disk interface controller version came off the production line at the Inmos foundry of the T212 (Sheen, et al., 1998). at Newport, Gwent (Borger and Stark, 2012). The T9000, intended as the in the line, was Inmos was sold to Thorn EMI under the privatizing announced with support for a significantly Thatcher government in the mid-80s, and later to extended instruction set, a hardware SGS Thomson, Transputer development implementation of virtual channels, superscalar continued, but was eventually abandoned. It's not performance and clock speeds which once again so easy to kill the Hydra-headed Transputer. The matched the competition, but for various reasons site of the original Inmos design centre in Bristol is the chip was delayed, suffered badly from silicon now owned by STMicroelectronics (May, n.d). bugs, and eventually canned years late having

https://escipub.com/global-journal-of-artificial-intelligence/ 2 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 reached about a quarter of its intended steadily growing, with the 80186 embedded performance (May, 2005). system version gaining a lot of popularity, helped Finally, the T400 (a 2 link T425 with reduced by the ready availability of compilers, support tools internal memory) and T450 (a T425 with extra and chips produced for the burgeoning IBM PC internal memory and enhanced instructions) market. Although the range was not particularly powerful, they were quite capable of transputers. many of the tasks being asked of them. The 68000 series, having dropped By the time the T450 (later known as the ST20) significantly in price since its release and gained a was in the field, interest in the transputer range as number of specialized variants, also gained a lot a whole was waning, and having already turned design wins. Both the and Motorola away from occam SGS Thompson announced processors had one significant point in their favour low price. Gained partly through volume and gave the impression it was dropping the line partly through in house fab lines, much of the entirely (May, 2005). market is very price sensitive (Hilton and Ivimey, As shown in figure 1 below, other processors were n.d). moving on too

FIGURE 1: This is figure 1. The release dates of various Transputers and some of their competitors (Hilton and Ivimey, n.d).

https://escipub.com/global-journal-of-artificial-intelligence/ 3 Nzenwata Uchenna J et al., GJAI, 2019; 1:5

Hitachi entered the market with its Z80 compatible those people are aware of the capabilities of the range of processors the HD64180 being a device. What is a bit sad is that what is significant advance on the ageing Z80, and have remembered best in the industry is the carried on with the SH series which was very for example its use of an successful indeed. A number of new designs odd language as well as the rather unusual emerged from Zilog themselves, but the Z8000 inclusion of fast communications links in and Z800 never caught on in a big way. preference to GPIO lines or an RS232 interface During this time, a community of academic and rather than the benefits these things provided commercial developers had grown around the (Morse, 2014). technology; user groups such as The World On the commercial front a lot of products were occam and Transputer User Group (WoTUG), and developed around the Inmos suggested TRAM The North American Transputer User Group format. This was a PCB with a base unit size (NATUG) grew and gained large followings. For slightly longer than credit card size, which could some time, the community supported several be plugged into a with connectors conferences a year averaging 250 delegates along the short sides. Designs requiring a larger each. A lot of experience was gained in the use of the very fine grained parallelism which was connectors carried mostly a number of OS Link offered by the transputer. An interesting interfaces. Bringing out address or data would observation was made that the programmers with have been contrary to the basic principle of the a background in hardware design fared better with transputer. According to (Furber, 2017), the the design of these highly parallel systems than design of TRAMS was well received and many did those with a traditional computer science devices were put on it, including high resolution background. This experience has undoubtedly graphics cards, RS232 and RS432 serial had its effect on the software community at large; interfaces along with the expected T4 or T8 CPU a very large number of engineers have at least plus memory. heard of the transputer, and quite a number of done by software (the kernel) The transputer is a programmable device on a that gives slices of CPU time to every task that is single chip with a stunning performance. The ready to run (time slicing). But with the transputer, importance of the transputer is that it provides a however, this multi-tasking kernel and scheduler higher level of abstraction in the design of information systems, due to its inherent support , which makes the transputer ideally for (Furber, 2017). (Bhowmick suited for multi-tasking applications (very fast and Prasad, 2017), said opined that context switching) (Laplante and Milojicic, 2016). multiprocessing is the only way to provide the high Transputers during its era saw its purposes in performance levels demanded by some present- satisfying several applications. (MATSUI, 2015) day applications at a moderate cost. Due to Identified some of the areas the transputer had limitations of a physical nature, technology cannot gained grounds: High speed multiprocessor provide sufficient increase in performance, so new systems, and clusters, techniques are needed. Multiprocessing is , Real time processing, Scientific definitely the most important one. and mathematical applications, Digital signal The key innovation of the transputer is its inherent processing, Accelerator processors, Distributed concurrency. In all processors multi-tasking is databases, System simulation,

https://escipub.com/global-journal-of-artificial-intelligence/ 4 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 Telecommunications, Microprocessor Graphics processing, Image processing, Pattern applications, Industrial control, Robotics, Fault recognition, Artificial intelligence, etc. tolerant systems, Medical instrumentation, TRANSPUTER ARCHITECTURE DESIGN AND Architectural Design NETWORK The INMOS transputer is the first single-chip The transputer, manufactured by INMOS, is a microprocessor to provide a high speed single chip Very Large Scale Interface (VLSI) processor, fast inter-processor communications, device with processor, memory, and and explicit support for multiple processes and communications links. This represents a slight multiple processor systems. Transputers are deviation from microprocessor designed to be part of a multiprocessor system, so architecture. The common features of transputers the performance of an individual processor is not are: High speed integer processor with micro- especially critical. If more processing power is codes process scheduler; On-chip fast static needed, more processors can simply be added. memory; Up to four links for communication with Figure 2 below shows the block diagram of a other transputers; Internal timers; and External generic transputer. memory interface (Chertovskikh and Rachek, 2014).

FIGURE 2: This is figure 2. The block diagram of a generic transputer (Transputer, 1993).

https://escipub.com/global-journal-of-artificial-intelligence/ 5 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 The internal design of the transputer is unlike that The Floating Point Unit is that part of a processor of any of its predecessors (Fox et al., 2014). The which performs floating point arithmetic. Some central concept of transputer architecture is that of series of transputers have a 32/64-bit floating the process. A process represents an individual point unit that conforms to the IEEE 754-1985 thread of control and the transputer switches specification. The floating point unit (FPU) has an between running processes to provide the illusion evaluation stack similar to that of the integer that they are all running simultaneously. This is processor, with three registers: FA, FB, and FC. normally handled by the operating system and Each of these registers can contain either a 32-bit called multitasking, but in the transputer, this is or a 64-bit number and has a flag to show which implemented in hardware and micro-coding of these it does contain. The FPU design is a (Haefner, 2018). compromise between maximizing overall According to (Manet and Rousseau, 2016), all processor performance and minimizing chip area. transputers have a fast integer processor and Because of this, the FPU has no flash multiplier or many instructions that take only a single cycle of . However, the performance is good, the processor clock to complete. Transputers with single and double precision multiplication were manufactured with clock speeds up to 25 times of 550 and 1000 nanoseconds respectively, MHz. All transputers, however, operate from an for a 20 MHz device (Cohen and Wang, 2014). external clock speed of 5 MHz. The processor The FPU operates concurrently with the integer clock is obtained from an internal phase-locked processor, and thus computation can be speeded loop multiplier. up by overlapping integer and floating-point processing. Figure 3 shows the floating point unit. The Floating Point Unit

Figure 3: This is figure 3. The Floating Point Unit (Transputer, 1993)

https://escipub.com/global-journal-of-artificial-intelligence/ 6 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 The Transputer Network While a simple tree structure provides short path A typical Transputer has four hardware lengths between the arbitrary nodes, a modified communication ports, permitting a variety of ternary tree can also achieve this between siblings configuration patterns when a number of these at the same level, thus increasing the scope for processors are linked together. This was achieving both efficiency and flexibility in the flow demonstrated by (Hass, Kuila and Shahid, 2017), of data between transputers. Four of these single where applications requiring distributed elements, a total of 16 transputers, are mounted processing from a single stream of control data, on a standard 3U printed circuit board as shown the most effective arrangement can be shown to in Figures 4 and 5. The transputers are be a ternary tree, providing hierarchical control. permanently hardwired to each other.

Figure 4: This is figure 4. Basic Network Topology of a 16-Transputer Board (Itagaki et al., 2018).

Figure 5: This is figure 5. Printed Circuit Board with 16 Transputers (Itagaki et al., 2018).

https://escipub.com/global-journal-of-artificial-intelligence/ 7 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 The rationale behind this design feature is that a mapping retains an extremely important feature real-time distributed system should not require a of CSP: processes can be composed. For an large amount of on-board memory for inter instance, if two processes x and y interact mediate data storage. Each transputer thus uses together and with some environment, the only its internal 4 kB memory for programming external behaviour can be modeled as a process purposes. This results in a total of 160 z. If y is replaced with another process transputers with 640 kB of internal memory implementing its external behavior, you also end distributed across the network in the case of the up with z so long as x and y are composed. 10-board system, as shown in figure 6, and a Composition of processes is believed to be maximum processing power of 1.4 GIPS. The essential to the ability to effectively design absence of local external memory necessitates systems. Consider how it would be if you had to compact algorithms for execution at audio use a particular finger to switch on a light. In real sampling rates and the use of a compact code world, things do exhibit composition. such as Occam, a programming language THE EFFACEMENT OF TRANSPUTER designed specifically for the transputer family. The transputer invention was a realistic implementation multiprocesses. It was intended In the words of (Furber, 2017), the transputer to provide high performance at low cost. The does not readily fall into either the CISC main idea behind the transputer was quite (complex instruction set) or the RISC (reduced simple: instead of creating a very complex instruction set) categories. It has a simple processor, the transputer consisted of a family of instruction set, called Occam, and tends to be chips. Each chip had a very simple design and viewed as a RISC processor. However, it is multiple chips could be wired together to form an much more than a RISC processor because of entire computer. Each transputer chip was in fact the functionality built into the chip to support high some kind of a and was able to level concepts such as processes, timers, and boot and operate by itself, it had its own RAM, a inter-process communication. Programmers serial bus and an embedded real-time OS. used to programming other may find programming the transputer to be a there were problems that promoted the strange experience (Bull, 2016). There is only a effacement of the transputer. These problems small number of registers that are organized as birth the replacement of the transputer with a stack, and all instructions are stack, rather than sophisticated approach to multiprocessing: the register oriented. There is little concept of Intel core microprocessors. condition codes, only limited instructions for Occam was developed to specifically support accessing memory, and more sophisticated the development of the fine grained parallel memory-addressing modes (Heath, 2014). processing environments supported by the The language created by Inmos is the Ocam. It transputer model and typical of those found in was based on research by (He, Joseph and embedded systems. It also supports extensive Hoare, 2015) that described a mathematical checking of programs, threaded or not (Haefner, language called Communicating Sequencing 2018). Processes (CSP). CSP describes the FACTORS THAT PROMOTED THE interactions of processes interacting through the EFFACEMENT OF THE TRANSPUTER exchange of signals or messages. In CSP, the There are ample number of factors, amidst the internals of a process are opaque, as are the pool of the transputer architecture applications events. In occam, CSP processes are that militated against its permissive use through implemented as tasks, and events as messages communicated over one- to-one links. This https://escipub.com/global-journal-of-artificial-intelligence/ 8 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 the generations of computing processor. Some typically far more heavyweight than in the of the major reasons are identified in this study. transputer architecture (Agullo et al., 2017). Computing Power Scalability The Inmos Patent Right Transfer As the computing power increases overtime, Inmos improved on the performance of the T8 there came a need for a miniature architecture series transputers with the introduction of the which birth the microchips. The latching of T9000 (Haase and Pester, 2013). The T9000 became a bulky technology to be laid shared most features with the T800, but moved on a mother board of a system. The idea of several pieces of the design into hardware and developing a high speed processor with added several features for superscalar support. compressed IC board became essential for the Long delays in the T9000's development meant growth of microprocessor speed. Also, since a that the faster load/store designs were already high computing power gained by the outperforming it by the time it was to be combination of multiple transistors can be released. It consistently failed to reach its own replication in a small high speed performance goal of beating the T800 by a factor microprocessor, transputers application of ten. When the project was finally cancelled it diminished due to the large size of trasputers was still achieving only about 36 MIPS at network. 50 MHz. The production delays gave rise to the Need for Superscalar Processing quip that the best host architecture for a T9000 According to (Denning and Lewis, 2017), was an overhead projector. This was too much growing internal parallelism has been one for Inmos, which did not have the funding driving force behind improvements in needed to continue development. By this time, conventional CPU designs. Instead of explicit the company had been sold to SGS-Thomson, thread-level parallelism, as is used in the now STMicroelectronics, whose focus was the transputer, CPU designs exploited implicit embedded systems market, and eventually the parallelism at the instruction-level, inspecting T9000 project was abandoned (Clark, 2006). code sequences for data dependencies and When Inmos was sold to Thorn EMI under the issuing multiple independent instructions to privatising Thatcher government in the mid-80s, different execution units. This is termed and later to SGS Thomson, Transputer superscalar processing. Superscalar processors development continued, but was eventually are suited for optimising the execution of abandoned. sequentially constructed fragments of code. Poor (MMU) Given these substantial and regular Another major problem of the transputer was the performance improvements to existing code lack of an MMU or support, which there was little incentive to rewrite software in prevented to be ported to the transputer languages or coding styles which expose more architecture. Although there were ports of some task-level parallelism. UNIX-like OSes. Unlike the transputer architecture, the The Ocam Wane processing units in these systems typically use superscalar CPUs with access to substantial The occam language, known as the transputer amounts of memory and disk storage, running language or instructions set, was though conventional operating systems and network hampered by the lack of compilers for other interfaces. Resulting from the more complex chips, it waxed as real time systems developers nodes, the software architecture used for discovered its expressive power. However, as coordinating the parallelism in such systems is the transputers lost their speed advantage against other processors, people found them

https://escipub.com/global-journal-of-artificial-intelligence/ 9 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 less and less practical, and the use of occam implementation of today waned too. microprocessors. The Restoration Movement of We have looked at the basis of the transputer: Transputer. the elements of simplicity and in integration that It was after Inmos was sold out that the idea of made it a useful and very powerful processor in Transputer restoration project came up. After the its own time. We noted here that the transputers termination of T9000 project, there was a were designed to satisfy their original purposes. comprehensive redesigned 32-bit transputer We have also identified the occam language as intended for embedded applications, the ST20 the instruction set of the transputer which Inmos series, using some technology developed for the designed with the transputer to provide high T9000. The ST20 core was incorporated into level access to these facilities. chipsets for set-top box and Global Positioning We looked at how the transputer evolved and System (GPS) applications. According to (May, addressed over the intervening past years, here, 2005), ST20 was not strictly a transputer, but it we discussed the architectural design and the was heavily influenced by the T4 and T9 and network of transputers. formed the basis of the T450, which was Some of the factors that contributed to the dead arguably the last of the transputers. end of the transputer legacy were identified. We The kernel of the idea to breathe life back into a also discussed how these factors hindered the forgotten piece of British technological genius operations. Finally, was given by Paul Walker, of 4Links Ltd, who we reported that a transputer restoration project worked with the Inmos Transputer in the early to bring into service and maintenance two fully days and took forward some of its design ideas functioning Inmos Transputer Development to help create SpaceWire, a serial System units. communication technology used throughout the REFERENCES space industry (Chintalapati, 2016). 1. What is a transputer_ - Quora. (n.d.). According to (Project Aims, n.d), the transputer 2. ). Restoration Project aims to bring into service Evolutionary design of group communication and maintain two fully functioning Inmos schedules for interconnection networks. Transputer Development System units. The first In International Symposium on Computer and Information Sciences (pp. 472-481). Springer, unit contains 64 processors and runs a Berlin, Heidelberg. demonstration of parallel processing of this 3. Börger, E., & Stärk, R. (2012). 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