DOCSLIB.ORG

Free Full-Text

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Free Full-Text Nzenwata Uchenna J et al., GJAI, 2019; 1:5 INTRODUCTION This paper discusses the original purposes of the transputer technology, how they have been The word transputer is a derivative name from the addressed over the intervening past years, the Transistor Computer. The transputer was architectural designs and network. It also conceived of as a building block for electronic emphasizes the factors that promoted the effacing systems comprising a processor, memory and a of transputers and the Restoration movement of communication system. Large systems were to be transputer. constructed from collections of transputers, each running a program and communicating with other The study was carried out by performing in-depth transputers (Quora, n.d). study on transputer literatures. The Inmos transputer was a British-designed, THE TRANSPUTER TECHNOLOGY DRIFT novel parallel microprocessor architecture from Si according to the early1980s. The transputer was unique in that (Fox, Williams, and Messina, 2014), the each processor had a built-in simple operating transputer has drawn much attention among system, memory and four high speed (20 Mbit/s researchers and design engineers, due its novel full duplex) bi-directional serial links. The architectural features and excellent performance. transputer is essentially a computer system on a (Sheen, Allen, Ripke, and Woo, 1998), stated that chip. The links on the transputer allow connection the Inmos transputer device range, which started to up to four other transputers or peripherals such with the T414 in 1983, was continued with a as video graphics, floppy and hard disc drives, series: the 16-bit T212, T222 and T225. The 32 bit Ethernet networking and standard RS-232 serial line was extended with the T425, which ran with a ports (Jaros, Ohlidal and Dvorak, 2005). faster processor clock, more internal memory and The rationale behind the design of the transputer also improved the instruction set and debug came from the point-to-point connection architecture. The T800, announced around 1987, architecture of the Modular-One computer and the included a formally verified IEEE conformant work of Tony Hoare (of QuickSort fame) on Floating Point Unit (FPU) (quite rare for the period) Communication between Sequential Processes. and was developed soon after the release of the His seminal paper led to the design of the T414. Transputer and the parallel programming It was followed by the T801 and T805, introducing language Occam by David May. Starting in early among other things the improved software debug 1981 David May designed the Transputer and the also seen on the T425. The M212 was an early novel Occam language and compiler. It was not trial of an Application Specific Standard Part until 1985 that the first prototype Transputers (ASSP): an MFM disk interface controller version came off the production line at the Inmos foundry of the T212 (Sheen, et al., 1998). at Newport, Gwent (Borger and Stark, 2012). The T9000, intended as the next in the line, was Inmos was sold to Thorn EMI under the privatizing announced with support for a significantly Thatcher government in the mid-80s, and later to extended instruction set, a hardware SGS Thomson, Transputer development implementation of virtual channels, superscalar continued, but was eventually abandoned. It's not performance and clock speeds which once again so easy to kill the Hydra-headed Transputer. The matched the competition, but for various reasons site of the original Inmos design centre in Bristol is the chip was delayed, suffered badly from silicon now owned by STMicroelectronics (May, n.d). bugs, and eventually canned years late having https://escipub.com/global-journal-of-artificial-intelligence/ 2 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 reached about a quarter of its intended steadily growing, with the 80186 embedded performance (May, 2005). system version gaining a lot of popularity, helped Finally, the T400 (a 2 link T425 with reduced by the ready availability of compilers, support tools internal memory) and T450 (a T425 with extra and chips produced for the burgeoning IBM PC internal memory and enhanced instructions) market. Although the x86 range was not particularly powerful, they were quite capable of transputers. many of the tasks being asked of them. The Motorola 68000 series, having dropped By the time the T450 (later known as the ST20) significantly in price since its release and gained a was in the field, interest in the transputer range as number of specialized variants, also gained a lot a whole was waning, and having already turned design wins. Both the Intel and Motorola away from occam SGS Thompson announced processors had one significant point in their favour low price. Gained partly through volume and gave the impression it was dropping the line partly through in house fab lines, much of the entirely (May, 2005). market is very price sensitive (Hilton and Ivimey, As shown in figure 1 below, other processors were n.d). moving on too FIGURE 1: This is figure 1. The release dates of various Transputers and some of their competitors (Hilton and Ivimey, n.d). https://escipub.com/global-journal-of-artificial-intelligence/ 3 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 Hitachi entered the market with its Z80 compatible those people are aware of the capabilities of the range of processors the HD64180 being a device. What is a bit sad is that what is significant advance on the ageing Z80, and have remembered best in the industry is the carried on with the SH series which was very for example its use of an successful indeed. A number of new designs odd language as well as the rather unusual emerged from Zilog themselves, but the Z8000 inclusion of fast communications links in and Z800 never caught on in a big way. preference to GPIO lines or an RS232 interface During this time, a community of academic and rather than the benefits these things provided commercial developers had grown around the (Morse, 2014). technology; user groups such as The World On the commercial front a lot of products were occam and Transputer User Group (WoTUG), and developed around the Inmos suggested TRAM The North American Transputer User Group format. This was a PCB with a base unit size (NATUG) grew and gained large followings. For slightly longer than credit card size, which could some time, the community supported several be plugged into a motherboard with connectors conferences a year averaging 250 delegates along the short sides. Designs requiring a larger each. A lot of experience was gained in the use of the very fine grained parallelism which was connectors carried mostly a number of OS Link offered by the transputer. An interesting interfaces. Bringing out address or data bus would observation was made that the programmers with have been contrary to the basic principle of the a background in hardware design fared better with transputer. According to (Furber, 2017), the the design of these highly parallel systems than design of TRAMS was well received and many did those with a traditional computer science devices were put on it, including high resolution background. This experience has undoubtedly graphics cards, RS232 and RS432 serial had its effect on the software community at large; interfaces along with the expected T4 or T8 CPU a very large number of engineers have at least plus memory. heard of the transputer, and quite a number of done by software (the operating system kernel) The transputer is a programmable device on a that gives slices of CPU time to every task that is single chip with a stunning performance. The ready to run (time slicing). But with the transputer, importance of the transputer is that it provides a however, this multi-tasking kernel and scheduler higher level of abstraction in the design of information systems, due to its inherent support microcode, which makes the transputer ideally for multiprocessing (Furber, 2017). (Bhowmick suited for multi-tasking applications (very fast and Prasad, 2017), said opined that context switching) (Laplante and Milojicic, 2016). multiprocessing is the only way to provide the high Transputers during its era saw its purposes in performance levels demanded by some present- satisfying several applications. (MATSUI, 2015) day applications at a moderate cost. Due to Identified some of the areas the transputer had limitations of a physical nature, technology cannot gained grounds: High speed multiprocessor provide sufficient increase in performance, so new systems, Workstations and workstation clusters, techniques are needed. Multiprocessing is Supercomputers, Real time processing, Scientific definitely the most important one. and mathematical applications, Digital signal The key innovation of the transputer is its inherent processing, Accelerator processors, Distributed concurrency. In all processors multi-tasking is databases, System simulation, https://escipub.com/global-journal-of-artificial-intelligence/ 4 Nzenwata Uchenna J et al., GJAI, 2019; 1:5 Telecommunications, Microprocessor Graphics processing, Image processing, Pattern applications, Industrial control, Robotics, Fault recognition, Artificial intelligence, etc. tolerant systems, Medical instrumentation, TRANSPUTER ARCHITECTURE DESIGN AND Architectural Design NETWORK The INMOS transputer is the first single-chip The transputer, manufactured by INMOS, is a microprocessor to provide a high speed single chip Very Large Scale Interface (VLSI) processor, fast inter-processor communications, device with processor, memory, and and explicit support for multiple processes and communications links. This represents a slight multiple processor systems. Transputers are deviation from microprocessor designed to be part of a multiprocessor system, so architecture. The common features of transputers the performance of an individual processor is not are: High speed integer processor with micro- especially critical. If more processing power is codes process scheduler; On-chip fast static needed, more processors can simply be added. memory; Up to four links for communication with Figure 2 below shows the block diagram of a other transputers; Internal timers; and External generic transputer.
Load more

Recommended publications
  • Inmos T800 Transputer)
    PARALLEL ALGORITHM DEVELOPMENT FOR A SPECIFIC MACHINE (INMOS T800 TRANSPUTER) BY WILLIAM STAUB 1 This paper will desribe from start to finish the parallel algorithm program development for a specific transputer (Inmos T800) network. It is essential to understand how the hardware manages parallel tasks and how information is exchanged between the transputers before writing a parallel program. A transputer (figure1, page3) is a circuit containing a processor, some memory to store programs and data, and several ports for exchanging, or transferring information with other transputers or with the outside world. By designing these circuits so that they could be connected together with the same simplicity with which transistors can be in a computer, the transputer was born. One of the most important factor was the introduction of a high-level language, occam [MAY83], whose features were directly supported by this transputer’s hardware and that made the transputer a building block for parallel computers. However a Locical System C compiler was developed for wider know usage. A prominent factor to utilizing this circuitry was the ease with which transputers could be connected to each other with as little as a few electrical wires. The four bi- directional input/output (I/O) ports of the transputer are designed to interface directly with the ports of other transputers, his feature allows for several transputers to fit on a small footprint, with very little extra logic circuits, making it possible to easily fit four transputers with some memory on a PC daughter board (ISA bus). 2 Figure 1: Transputer block-diagram and examples of interconnection networks.
    [Show full text]
  • A Low Cost, Transputer Based Visual Display Processor G.J. Porter, B
    Transactions on Information and Communications Technologies vol 3, © 1993 WIT Press, www.witpress.com, ISSN 1743-3517 A low cost, transputer based visual display processor G.J. Porter, B. Singh, S.K. Barton Department of Electronic and Electrical Engineering, University of Bradford, Richmond Road, Bradford, West Yorkshire, UK ABSTRACT As major computer systems and in particular parallel computing resources become more accessible to the engineer, it is becoming necessary to increase the performance of the attached video display devices at least pro-rata with those of the computational elements. To this end a number of device manufacturers have developed or are in the process of developing new display controllers, dedicated to the task of improving the display environments of the super computers in use today by engineers. There is however a price to be paid for this development, in terms of monetary cost and in the design effort involved in integrating the new technology into existing systems. This paper will present a solution to this problems. Firstly, by showing how to utilise available transputer technology to upgrade the display capability of existing systems by transferring some of the available processing power from the computational elements of the system to the display controller. Secondly, by utilising a low cost off-the-shelf Transputer Module based video display unit. The new video display processor utilises a three transputer pipeline formed from as Scan Converter Unit, a Span Encoder Unit and a Span Filler Unit, and can be further expanded by increasing the functionality and/or parallelism of each stage if required. 1.
    [Show full text]
  • A Distributed Transputer-Based Architecture Using a Reconfigurable Synchronous Communication Protocol
    A DISTRIBUTED TRANSPUTER-BASED ARCHITECTURE USING A RECONFIGURABLE SYNCHRONOUS COMMUNICATION PROTOCOL Marie Josette Brigitte Vachon B.A.Sc. Royal Military College, Kingston, 1984 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA August 1989 © Marie Josette Brigitte Vachon s 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of E^(Lm\OAL. k)ZF.P\*iU The University of British Columbia Vancouver, Canada Date IC AVC I J8 7 DE-6 (2/88) Abstract A reliable, reconfigurable, and expandable distributed architecture supporting both bus and point- to-point communication for robotic applications is proposed. The new architecture is based on Inmos T800 microprocessors interconnected through crossbar switches, where communication between nodes takes place via point-to-point bidirectional links. Software development is done on a host computer, Sun 3/280, and the executable code is downloaded to the distributed architecture via the bus. Based on this architecture, an operating system has been designed to provide communication and input/output support.
    [Show full text]
  • Design of a Neural Network Simulator on a Transputer Array
    DESIGN OF A NEURAL NETWORK SIMULATOR ON A TRANSPUTER ARRAY Gary Mclntire James Villarreal, Paul Baffes, and Advanced Systems Engineering Dept. Ford Monica Rua Artificial Intelligence Section, Aerospace, Houston, TX. NASNJohnson Space Center, Houston, TX. Abstract they will be commercially available. Even if they were available today, they would be A high-performance simulator is being built generally unsuitable for our work because to support research with neural networks. All they are very difficult (usually impossible) to of our previous simulators have been special reconfigure programmably. A non-hardwired purpose and would only work with one or two VLSl neural network chip does not exist today types of neural networks. The primary design but probably will exist within a year or two. If goal of this simulator is versatility; it should done correctly, this would be ideal for our be able to simulate all known types of neural simulations. But the state of the art in networks. Secondary goals, in order of reconfigurable simulators are supercomputers importance, are high speed, large capacity, and and parallel processors. We have a very fast ease of use. A brief summary of neural simulator running on the SX-2 supercomputer networks is presented herein which (200 times faster than our VAX 11/780 concentrates on the design constraints simulator), but supercomputer CPU time is imposed. Major design issues are discussed yfzy costly. together with analysis methods and the chosen For the purposes of our research, solutions. several parallel processors were investigated Although the system will be capable of including the Connection Machine, the BBN running on most transputer architectures, it Butterfly, and the Ncube and Intel Hypercubes.
    [Show full text]
  • Operating RISC: UNIX Standards in the 1990S
    Operating RISC: UNIX Standards in the 1990s This case was written by Will Mitchell and Paul Kritikos at the University of Michigan. The case is based on public sources. Some figures are based on case-writers' estimates. We appreciate comments from David Girouard, Robert E. Thomas and Michael Wolff. The note "Product Standards and Competitive Advantage" (Mitchell 1992) supplements this case. The latest International Computerquest Corporation analysis of the market for UNIX- based computers landed on three desks on the same morning. Noel Sharp, founder, chief executive officer, chief engineer and chief bottle washer for the Superbly Quick Architecture Workstation Company (SQAWC) in Mountain View, California hoped to see strong growth predicted for the market for systems designed to help architects improve their designs. In New York, Bo Thomas, senior strategist for the UNIX systems division of A Big Computer Company (ABCC), hoped that general commercial markets for UNIX-based computer systems would show strong growth, but feared that the company's traditional mainframe and mini-computer sales would suffer as a result. Airborne in the middle of the Atlantic, Jean-Helmut Morini-Stokes, senior engineer for the UNIX division of European Electronic National Industry (EENI), immediately looked to see if European companies would finally have an impact on the American market for UNIX-based systems. After looking for analysis concerning their own companies, all three managers checked the outlook for the alliances competing to establish a UNIX operating system standard. Although their companies were alike only in being fictional, the three managers faced the same product standards issues. How could they hasten the adoption of a UNIX standard? The market simply would not grow until computer buyers and application software developers could count on operating system stability.
    [Show full text]
  • The Helios Operating System
    The Helios Operating System PERIHELION SOFTWARE LTD May 1991 COPYRIGHT This document Copyright c 1991, Perihelion Software Limited. All rights reserved. This document may not, in whole or in part be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine readable form without prior consent in writing from Perihelion Software Limited, The Maltings, Charlton Road, Shepton Mallet, Somerset BA4 5QE. UK. Printed in the UK. Acknowledgements The Helios Parallel Operating System was written by members of the He- lios group at Perihelion Software Limited (Paul Beskeen, Nick Clifton, Alan Cosslett, Craig Faasen, Nick Garnett, Tim King, Jon Powell, Alex Schuilen- burg, Martyn Tovey and Bart Veer), and was edited by Ian Davies. The Unix compatibility library described in chapter 5, Compatibility,im- plements functions which are largely compatible with the Posix standard in- terfaces. The library does not include the entire range of functions provided by the Posix standard, because some standard functions require memory man- agement or, for various reasons, cannot be implemented on a multi-processor system. The reader is therefore referred to IEEE Std 1003.1-1988, IEEE Stan- dard Portable Operating System Interface for Computer Environments, which is available from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Pis- cataway, NJ 08855-1331, USA. It can also be obtained by telephoning USA (201) 9811393. The Helios software is available for multi-processor systems hosted by a wide range of computer types. Information on how to obtain copies of the Helios software is available from Distributed Software Limited, The Maltings, Charlton Road, Shepton Mallet, Somerset BA4 5QE, UK (Telephone: 0749 344345).
    [Show full text]
  • I.T.S.O. Powerpc an Inside View
    SG24-4299-00 PowerPC An Inside View IBM SG24-4299-00 PowerPC An Inside View Take Note! Before using this information and the product it supports, be sure to read the general information under “Special Notices” on page xiii. First Edition (September 1995) This edition applies to the IBM PC PowerPC hardware and software products currently announced at the date of publication. Order publications through your IBM representative or the IBM branch office serving your locality. Publications are not stocked at the address given below. An ITSO Technical Bulletin Evaluation Form for reader′s feedback appears facing Chapter 1. If the form has been removed, comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JLPC Building 014 Internal Zip 5220 1000 NW 51st Street Boca Raton, Florida 33431-1328 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1995. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Abstract This document provides technical details on the PowerPC technology. It focuses on the features and advantages of the PowerPC Architecture and includes an historical overview of the development of the reduced instruction set computer (RISC) technology. It also describes in detail the IBM Power Series product family based on PowerPC technology, including IBM Personal Computer Power Series 830 and 850 and IBM ThinkPad Power Series 820 and 850.
    [Show full text]
  • Occam User Group
    for all users of occam and the transputer N912 January 1990 Contents EDITORIAL 2 Contributions to the newsletter 3 Occam user group publications 3 North American transputer users group publications 4 FORTHCOMING 4 Twelfth occam user group technical meeting 4 North American transputer users group spring meeting 5 Third Japanese transputer/ occam international conference 5 Thirteenth occam user group technical meeting 6 North American transputer users group fall meeting 6 Transputing 1991 7 REPORTS 9 Inaugural meeting of the occam user group: Latin America 9 Eleventh occam user group technical meeting 10 Why did the transputer cross The Pond? 14 Second seminar of the Swedish transputer user group 15 continued on back cover Meiko In-Sun Computing Surface Hardware (see page 98) occam is a trade mark of the INMOS Group of Companies 2 occam user group newsletteT EDITORIAL ~ ~ New groups seem to be springing up all around the world; this issue of nan the newsletter carries contact addresses for the first time for groups in U:E ~ Sweden and Latin America. We have contributions from as far afield as Brazil, the Basque country, and Bristol. It is all here: from exotic hardware (see for example pages 19, 82, 98 and many of the product announcements) to expressions of concern that software should be as unexciting as possible (see pages 22, 27). I would particularly like to draw your attention to the initiative to promote the occam language (see page 84); and to the CODE system from C-DAC (see pages 86 and18), an impromptu presentation of which stole the show in the exhibition at the OUG technical meeting in Edinburgh.
    [Show full text]
  • 1 Architecture Reference Manual 2 T414 Transputer Product Data
    Contents 1 Architecture reference manual 2 T414 transputer product data 3 T212 transputer product data 4 C011 link adaptor product data 5 C012 link adaptor product data omrnos® Reference manual • transputer architecture 8, inmos, IMS and occam are trade marks of the INMOS Group of Companies. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however no responsibility is assumed for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No licence is granted under any patents, trademarks or other rights of the INMOS Group of Companies. Copyright INMOS Limited, 1986 72 TRN 048 02 2 Contents 1 Introduction 5 1.1 Overview 6 1.2 Rationale 7 1.2.1 System design 7 1.2.2 Systems architecture 8 1.2.3 Communication 9 2 Occam model 11 2.1 Overview 11 Occam overview 12 2.2.1 Processes 12 2.2.2 Constructs 13 2.2.3 Repetition 15 2.2.4 Replication 15 2.2.5 Types 16 2.2.6 Declarations, arrays and subscripts 16 2.2.7 Procedures 17 2.2.8 Expressions 17 2.2.9 Timer 17 2.2.10 Peripheral access 18 2.3 Configuration 18 3 Error handling 19 ~------------------------------------------------------~-- _4___ P_rogram_ develo-'-p_m_e_n_t__________ _ 20 4.1- Performance measurement 20 ------------------ ~~--~------~~--~-------------------~-- 4.2 Separate compilation of occam and other languages 20 4.3 Memory map and placement 21 5 Physical architecture 22 5.1 INMOS serial links 22 5.1.1 Overview 22 5.1.2 Electrical specification of links 22 ------5~.~2---=S-ys-t-e--m-se-r-v~ic-e-s-~-------------------------------~23 ---------- 5.2.1 Powering up and down, running and stopping 23 5.2.2 Clock distribution 23 5.3 Bootstrapping from ROM or from a link 23 ------5-.-4--P-e-r-ip-h-eral interfacing 24 6 Notation conventions 26 6.1 Signal naming conventions 26 7 Transputer product numbers 27 3 Preface This manual describes the architecture of the transputer family of products.
    [Show full text]
  • White Paper Northforge Innovations Inc
    Modern Packet Switch Design White Paper Northforge Innovations Inc. September 2016 1 Introduction This white paper surveys the architectural evolution of Ethernet packet switches, featuring an overview of early packet switch design and the forces that have driven modern design solutions. These forces, which include increased interface speed, increased number of ports, Software-Defined Networking (SDN), Deep Packet Inspection (DPI), and Network Functions Virtualization (NFV) have had a major impact on the architecture and design of modern packet switches. All Packet Switches Are Divided Into Three Parts The networking industy has been building LAN-based packet switches (including under this rubric, LAN Bridges, MPLS Switches, and IP Routers) since the early-mid 1980s. The three functional components of a packet switch have been stable since the beginning. • Data plane – The primary job of a packet switch is to move packets from an input interface to an output interface. Moving the data from input to output is the job of the data plane (sometimes called the forwarding plane). • Control plane – The data plane decides which output port to select for each arriving packet based on a set of tables that are built by the control plane. For an Ethernet Switch, the control plane includes the process that learns MAC addresses, the spanning tree protocol, etc. For an IP router, the control plane includes the various IP routing protocols (e.g., OSPF and IS-IS). • Management plane – All packet switches require some configuration. In addition, they include mechanisms for fault detection and reporting, statistics collection, and troubleshooting. This is all done by the management plane.
    [Show full text]
  • A Brief History of Debian I
    A Brief History of Debian i A Brief History of Debian A Brief History of Debian ii 1999-2020Debian Documentation Team [email protected] Debian Documentation Team This document may be freely redistributed or modified in any form provided your changes are clearly documented. This document may be redistributed for fee or free, and may be modified (including translation from one type of media or file format to another or from one spoken language to another) provided that all changes from the original are clearly marked as such. Significant contributions were made to this document by • Javier Fernández-Sanguino [email protected] • Bdale Garbee [email protected] • Hartmut Koptein [email protected] • Nils Lohner [email protected] • Will Lowe [email protected] • Bill Mitchell [email protected] • Ian Murdock • Martin Schulze [email protected] • Craig Small [email protected] This document is primarily maintained by Bdale Garbee [email protected]. A Brief History of Debian iii COLLABORATORS TITLE : A Brief History of Debian ACTION NAME DATE SIGNATURE WRITTEN BY September 14, 2020 REVISION HISTORY NUMBER DATE DESCRIPTION NAME A Brief History of Debian iv Contents 1 Introduction -- What is the Debian Project? 1 1.1 In the Beginning ................................................... 1 1.2 Pronouncing Debian ................................................. 1 2 Leadership 2 3 Debian Releases 3 4 A Detailed History 6 4.1 The 0.x Releases ................................................... 6 4.1.1 The Early Debian Packaging System ..................................... 7 4.2 The 1.x Releases ................................................... 7 4.3 The 2.x Releases ................................................... 8 4.4 The 3.x Releases ................................................... 8 4.5 The 4.x Releases ..................................................
    [Show full text]
  • Microprocessors: from Basic Chips to Complete Systems
    - 237 - MICROPROCESSORS: FROM BASIC CHIPS TO COMPLETE SYSTEMS R. W. Dobinson,*) University of Illinois, Urbana, Illinois, USA. "Good-morning, good morning!", the General said When we met him last week on our way to the line. Now the soldiers he smiled at are most of them dead, And we're cursing his staff for Incompetent swine. "He's a cheery old card," grunted Harry to Jack As they slogged up to Arras with rifle and pack. * * * * But he did for them both by his plan of attack. Siegfried Sassoon April 1917 1. AIMS OF THESE LECTURES Microprocessor technology has, since its conception and birth in the early 1970's, entered very many areas of our lives. No end to its growth is in sight, and new uses appear almost daily. The semiconductor industry continues to produce ever more powerful integrated circuits (known far and wide as chips); more functionality and speed at lower cost is every salesman's cry. These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They will show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/O) devices, etc. It is not my intention to discuss in detail the many different microprocessors now available on the market, nor will a complete catalogue of support chips be presented. Time will not permit this. Instead, emphasis will be placed on explaining the basic principles of different types of chip. As far as possible X will avoid talking too much about any specific devices; thus I will spend some time discussing a generic microprocessor accessing generic memory and talking to the outside world via generic I/O devices.
    [Show full text]