Microprocessor Theory and Applications with 68000/68020 and Pentium M. RAFIQUZZAMAN, Ph.D. Professor California State Polytechnic University Pomona, California and President Rafi Systems, Inc. WILEY A JOHNWILEY & SONS, INC., PUBLICATION This Page Intentionally Left Blank Microprocessor Theory and Applications with 68000/68020 and Pentium This Page Intentionally Left Blank Microprocessor Theory and Applications with 68000/68020 and Pentium M. RAFIQUZZAMAN, Ph.D. Professor California State Polytechnic University Pomona, California and President Rafi Systems, Inc. WILEY A JOHNWILEY & SONS, INC., PUBLICATION Copyright 0 2008 by John Wiley & Sons, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. 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QA76XM6895R34 2008 004.1654~22 2008011009 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1 To my wge, Kusum; my son, Tito; and my brothel; Elan This Page Intentionally Left Blank CONTENTS PREFACE XI11 CREDITS XV 1. INTRODUCTION TO MICROPROCESSORS 1 1.1 Explanation of Terms 2 1.2 Microprocessor Data Types 4 1.2.1 Unsigned and Signed Binary Numbers 5 1.2.2 ASCII and EBCDIC Codes 7 1.2.3 Unpacked and Packed Binary-Coded-Decimal Numbers 7 1.2.4 Floating-point Numbers 8 1.3 Evolution of the Microprocessor 9 1.4 Typical Features of 32-bit and 64-bit Microprocessors 15 1.5 Microprocessor-based System Design Concepts 16 1.6 Typical Microprocessor Applications 19 1.6.1 A Simple Microprocessor Application 20 1.6.2 Examples of Typical Microprocessor Applications 21 2. MICROCOMPUTER ARCHITECTURE 23 2.1 Basic Blocks of a Microcomputer 23 2.2 Typical Microcomputer Architecture 24 2.2.1 System Bus 24 2.2.2 Clock Signals 25 2.3 Single-Chip Microprocessor 26 2.3.1 Register Section 26 2.3.2 Control Unit 30 2.3.3 Arithmetic-Logic Unit 32 2.3.4 Functional Representations of Simple and Typical Microprocessors 32 2.3.5 Simplified Explanation of Control Unit design 34 2.4 Program Execution by Conventional Microprocessors 38 2.5 Program Execution by typical 32-bit Microprocessors 38 2.5.1 Pipelining 39 2.5.2 Branch Prediction Feature 44 2.6 Scalar and Superscalar Microprocessors 45 2.7 RISC vs. CISC 45 Questions and Problems 47 vii ... Vlll Contents 3. MICROPROCESSOR MEMORY ORGANIZATION 49 3.1 Introduction 49 3.2 Main memory 50 3.2.1 Read-only Memory 51 3.2.2 Random-Access Memory 52 3.2.3 READ and WRITE Timing Diagrams 52 3.2.4 Main Memory Organization 54 3.2.5 Main Memory Array Design 55 3.3 Microprocessor on-chip memory management unit and cache 58 3.3.1 Memory Management Concepts 58 3.3.2 Cache Memory Organization 63 Questions and Problems 68 4. MICROPROCESSOR INPUT/OUTPUT 71 4.1 Introduction 71 4.2 Simple I/O Devices 72 4.3 Programmed I/O 74 4.4 Unconditional and Conditional Programmed I/O 76 4.5 Interrupt I/O 78 4.5.1 Interrupt Types 80 4.5.2 Interrupt Address Vector 80 4.5.3 Saving the Microprocessor Registers 81 4.5.4 Interrupt Priorities 81 4.6 Direct Memory Access (DMA) 84 4.7 Summary of I/O 86 Questions and Problems 87 5. MICROPROCESSOR PROGRAMMING CONCEPTS 89 5.1 Microcomputer Programming Languages 89 5.2 Machine Language 90 5.3 Assembly Language 90 5.3.1 Types of Assemblers 91 5.3.2 Assembler Delimiters 92 5.3.3 Specifying Numbers by Typical Assemblers 93 5.3.4 Assembler Directives or Pseudoinstructions 93 5.3.5 Assembly Language Instruction Formats 95 5.3.6 Instruction Set Architecture (ISA) 97 5.3.7 Typical Instruction Set 98 5.3.8 Typical Addressing Modes 102 5.3.9 Subroutine Calls in Assembly Language 104 5.4 High-Level Language 104 5.5 Choosing a programming language 105 5.6 Flowcharts 106 Questions and Problems 107 6. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68000 109 6.1 Introduction 109 6.2 68000 Registers 111 6.3 68000 Memory Addressing 112 6.4 Assembly Language Programming with the 68000 113 Contents ix 6.5 68000 Addressing Modes 117 6.5.1 Register Direct Addressing 117 6.5.2 Address Register Indirect Addressing 118 6.5.3 Absolute Addressing 122 6.5.4 Program Counter Relative Addressing 123 6.5.5 Immediate Data Addressing 124 6.5.6 Implied Addressing 125 6.6 68000 Instruction Set 125 6.6.1 Data Movement Instructions 128 6.6.2 Arithmetic Instructions 134 6.6.3 Logic Instructions 150 6.6.4 Shift and Rotate Instructions 152 6.6.5 Bit Manipulation Instructions 156 6.6.6 Binary-Coded-Decimal Instructions 157 6.6.7 Program Control Instructions 160 6.6.8 System Control Instructions 163 6.6.9 68000 Stack 166 6.7 68000 Delay Routine 168 Questions and Problems 170 7. 68000 HARDWARE AND INTERFACING 175 7.1 68000 Pins And Signals 175 7.1.1 Synchronous and Asynchronous Control Lines 177 7.1.2 System Control Lines 179 7.1.3 Interrupt Control Lines 181 7.1.4 DMA Control Lines 181 7.1.5 Status Lines 181 7.2 68000 Clock and Reset Signals 181 7.2.1 68000 Clock Signals 181 7.2.2 68000 Reset Circuit 182 7.3 68000 Read and Write Cycle Timing Diagrams 185 7.4 68000 Memory Interface 188 7.5 68000 I10 192 7.5.1 68000 Programmed I10 192 7.5.2 68000 Interrupt System 201 7.5.3 68000 DMA 206 7.6 68000 Exception Handling 207 7.7 68000/2732/6116/682 1-Based Microcomputer 208 7.8 Multiprocessing with the 68000 Using the TAS Instruction and the AS Signal 212 Questions and Problems 217 8. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68020 221 8.1 Introduction 22 1 8.2 68020 Functional Characteristics 222 8.3 68020 Registers 225 8.4 68020 Data Types, Organization, and CPU Space Cycle 227 8.5 68020 Addressing Modes 22 8 8.5.1 Address Register Indirect (AM) with Index and 8-Bit Displacement 23 1 8.5.2 ARI with Index (Base Displacement, bd: Value 0 or 16 Bits or 32 Bits) 232 X Contents 8.5.3 Memory Indirect 232 8.5.4 Memory Indirect with PC 233 8.6 68020 Instructions 237 8.6.1 68020 New Privileged Move Instructions 238 8.6.2 Return and Delocate Instruction 238 8.6.3 CHK/CHK2 and CMP/CMP2 Instructions 239 8.6.4 Trap-on-Condition Instructions 243 8.6.5 Bit Field Instructions 245 8.6.6 PACK and UNPK Instructions 247 8.6.7 Multiplication and Division Instructions 250 8.6.8 68000 Enhanced Instructions 254 8.6.9 68020 Subroutines 254 Questions and Problems 256 9. 68020 HARDWARE AND INTERFACING 261 9.1 Introduction 26 1 9.1.1 68020 Pins and Signals 26 1 9.1.2 68020 Dynamic Bus Sizing 265 9.1.3 68020 Timing Diagrams 27 1 9.2 68020 System Design 274 9.2.1 Memory Decode Logic for Memory and VO 275 9.2.2 68020-27C256 Interface 276 9.2.3 68020- 2256C/CH (SRAM) Interface 277 9.2.4 68020 Programmed I/O 279 9.3 68020 Exception processing 282 9.4 68020-based Voltmeter 283 9.4.1 Voltmeter Design Using Programmed I/O 285 9.4.2 Voltmeter Design Using Interrupt I/O 289 9.5 Interfacing a 68020-Based Microcomputer to a Hexadecimal Keyboard and a Seven-Segment Display 293 9.5.1 Basics of Keyboard and Display Interface to a Microcomputer 294 9.5.2 68020 Interface to a Hexadecimal Keyboard and a Seven- Segment Display 296 Questions and Problems 302 10.