Getting Started with Modelsim and Xilinx ISE Tools

Getting Started with ModelSim and Xilinx ISE tools

ModelSim – Create the work area 1. Start ModelSim: Start → All Programs → Engineering → Modelsim 6.5b. 2. Create a new directory for your ModelSim project files and change to that directory. 1. Use File → Change Directory... to change the current directory. 2. Use File → New → Folder to create a new directory. 3. (Alternatively, you can type “cd” and “mkdir” at the console to do the same things.) 3. Create a new directory to put the ModelSim project files and/or HDL source code in (ex. hw1). Change to that directory and run vsim &. 4. Go to File → New → Library …. The name work should be set in the Library Name field. Click Ok to create the new library. 5. Create or copy HDL source files to directory. 1. Create option: 1. Click File → New → Source → Verilog or VHDL. 2. Type the HDL description in the source file window. 3. Save and name the file. 2. Copy option: 1. Copy the HDL source files to the directory.

ModelSim – Compiling and simulating 1. Compile the source files. Click Compile → Compile …. Select all HDL source files to compile in the window and then click Compile. Close the compile window by clicking Done. 1. If there are any errors, open up the source file and go to the line number indicated in the error message. Fix each error and recompile. 2. Start the simulation by clicking Simulate → Start Simulation …. 1. Expand library work and select your test bench module. 2. Click Optimization Options... and select Apply full visibility to all modules (full debug). Click Ok. 3. Click Ok again to then start the simulation. 3. In the instances window (on the left of the screen), right click on the test bench module name and click Add → To Wave → All items in region. 4. Restart and rerun the simulation by typing in the console window “restart; run 1 us” (this will run for 1 us. You can change this to run for longer or shorter times.) 5. With the waveform viewer window active (just click on it to activate it), then zoom full the window. This can be done one of several different ways: 1. Strokes – Hold down the middle mouse button and drag the mouse to the upper left direction and release. 2. Toolbar – Click the Zoom Full toolbar icon. 3. Keyboard key – Hit the “F” shortcut key. 4. Menu – Click Wave → Zoom → Zoom Full. 6. The waveform viewer window (by default) shows the extended name of each signal. This can be toggled to show the shortened name by looking for the icons at the bottom-left of the waveform viewer window. The top-left icon (when hovering the mouse of it) should read Toggle leaf names ↔ full names. Click on this icon. 7. Change the radix of some signals, such as buses, to hex or decimal value by right-clicking on the signal and clicking Radix → . Xilinx ISE tools – Creating a new project 1. Start Xilinx ISE tools: Start → All Programs → Engineering → Xilinx ISE Design Suite 13.2. 2. Create a new Xilinx project (File → New Project...). 3. Choose a name and location for the project and click Next. 4. Specify the following device: 1. Family: Virtex 4 2. Device: XC4VLX100 3. Package: FF1148 4. Speed: -12 5. Set the following additional parameter: 1. Simulator: ModelSim-SE Mixed 6. Click Next. 7. After reviewing the Project Summary, click Finish. 8. Click Project → Add Source and select your source files (these may be in another directory – you can either copy them over to your new Xilinx project directory, or simply link to them).

Xilinx ISE tools – Synthesizing your module 1. Above the hierarchy window, select the Implementation view. 2. In the Hierarchy window, select your top-level module. If it is not already set as the top-level, then right-click on it and click Set as Top Module. 3. In the Processes window, double-click on Synthesize to synthesize the module to hardware. (This will create an RTL schematic of the hardware description.) 4. When it is done, you can view the synthesis report by right-clicking on Synthesize, and clicking on View Text Report. Sections of interest are: 1. Device utilization summary – (number of slice registers, slice luts, etc.) 2. Timing summary – (estimated maximum clock frequency)