Aperture Uncertainty and ADC System Performance Application Note

AN-501

APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Aperture Uncertainty and ADC System Performance by Brad Brannon and Allen Barlow

APERTURE UNCERTAINTY Figure 1 illustrates how an error in the sampling instant results Aperture uncertainty is a key ADC concern when performing in an error in the sampled voltage. Mathematically, the IF sampling. The terms aperture jitter and aperture uncertainty magnitude of the sampled voltage error is defined by the time are synonymous and are frequently interchanged in the derivative of the signal function. Consider a sine wave input literature. Aperture uncertainty is the sample-to-sample signal variation in the encoding process. It has three distinct effects on ( ) = (2sin π ftAtv ) (1) system performance. First, it can increase system noise. Second, it can contribute to the uncertainty in the actual phase of the The derivative is sampled signal itself giving rise to increases in error vector (tdv ) = (2cos2 ππ ftfA ) (2) magnitude. Third, it can heighten intersymbol interference dt (ISI). However, in typical communications applications, an aperture uncertainty that is sufficiently small to meet system The maximum error occurs when the cosine function equals 1, noise constraints results in negligible impact on phase that is, at t = 0. uncertainty and ISI. For example, consider the case of sampling dv(0) (3) an IF of 250 MHz. At that speed, even 1 ps of aperture jitter can = 2πfA dt max limit any ADC’s SNR to only 56 dB, while for the same conditions, the phase uncertainty error is only 0.09 degrees rms We see from Figure 1 that dv is the error in the sampled voltage based on a 4 ns period. This is quite acceptable even for a corresponding to the jitter dt. For conceptual clarity, if we demanding specification such as GSM. The focus of this relabel dv as Verr and dt as ta (aperture error) and rearrange the analysis is, therefore, on overall noise contribution due to factors, we get aperture uncertainty. err = 2πftAV a (4)

If ta is given as an rms value, the derived Verr is also rms. Although this is the error at maximum input slew and represents an upper bound rather than a nominal, this simple model proves surprisingly accurate and useful for estimating the degradation in SNR as a function of sample clock jitter. dv JITTER AND SNR As Equation 4 indicates, the error in the sampled voltage increases linearly with input frequency, so at high frequencies, ERROR VOLTAGE for example, in IF sampled receiver applications, clock purity becomes extremely important. Sampling is a mixing operation: the input signal is multiplied by a local oscillator or in this case, a sampling clock. Because multiplication in time is convolution

ENCODE in the frequency domain, the spectrum of the sample clock is convolved with the spectrum of the input signal. Considering dt 01399-001 that aperture uncertainty is wideband noise on the clock, it Figure 1. RMS Jitter vs. RMS Noise shows up as wideband noise in the sampled spectrum, periodic and repeated around the sample rate.

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Because ADC encode inputs have very high bandwidth, the Next, an FFT is done at high (IF) frequency. The high frequency effects of clock input noise can extend out many times the chosen should be as high as possible. Again, the SNR value sample rate itself and alias back into the baseband of the without harmonics is measured. This time jitter is a contributor converter. Therefore, this wideband noise degrades the noise to noise and solving Equation 6 for ta yields floor performance of the ADC. Consider a sinusoidal input 2 2 ⎛ −SNR ⎞ ⎛1+ ε ⎞ signal of amplitude A. Utilizing Equation 4, the SNR for an ⎜10 20 ⎟ − ⎜ ⎟ ⎜ N ⎟ ADC limited by aperture uncertainty is ⎝ ⎠ ⎝ 2 ⎠ (8) ta = A 2πf SNR = log20 −= (2log20 πft ) (5) V a err where: Equation 5 illustrates why systems that require high dynamic SNR = the high frequency SNR just measured range and high analog input frequencies also require a low jitter ε = the value determined in the low frequency measurement. encode source. For an analog input of 200 MHz and only EXAMPLE: JITTER AND THE AD9246 300 femtoseconds rms clock jitter, SNR is limited to only 68.5 dB, well below the level commonly achieved at lower The example shown here utilizes the AD9246 evaluation board, speeds by 12-bit converters. Note in Equation 5 that the jitter a 14-bit, 125 MSPS ADC. An external clock oscillator such as a limit of SNR is independent of the converter resolution. (For Wenzel Sprinter or Ultra-Low Noise provides a suitable encode the case just mentioned, a 14-bit converter would do no better.) source. A mainstream RF synthesizer from Rohde & Schwarz or Agilent can be used for the analog source. Typically, these Aperture jitter is not always the performance limiter. Equation 6 generators have insufficient phase noise performance for use as shows its effect in superposition with other noise sources. The the encode source. For more information about configuring first term in the brackets is the jitter from Equation 5. To that, Analog Devices evaluation boards, please consult the individual we must add terms for quantization noise, DNL, and thermal product data sheet.

WALL OUTLET noise. For other analytic purposes, each of these could be 100V TO 240V AC broken out separately, but for simplicity in isolating the effect of 47Hz TO 63Hz 3.3V –+ jitter, we combine them here in a single additional term. 6V DC SWITCHING 2A MAX POWER 2/1 SUPPLY 2 CHB VCC ⎡ ⎤ GND 2 ⎛1+ ε ⎞ (6) PARALLEL SNR −= ⎢()2log20 π tf a + ⎜ N ⎟ ⎥ CMOS OUTPUTS ⎣⎢ ⎝ 2 ⎠ ⎦⎥ HSC-ADC-EVALB-DC PC EVALUATION FIFO DATA RUNNING ROHDE & SCHWARZ, BOARD CAPTURE ADC SMHU, BOARD ANALYZER where: 2V p-p SIGNAL BAND-PASS XFMR SYNTHESIZER FILTER INPUT CHA PARALLEL USB ROHDE & SCHWARZ, CMOS CONNECTION f = analog input frequency. SMHU, CLK OUTPUTS 2V p-p SIGNAL SPI SPI SPI ta = aperture uncertainty (jitter). SYNTHESIZER 01399-002 ε = “composite rms DNL” in LSBs, including thermal noise. Figure 2. Aperture Uncertainty Measurement Setup with AD9246 Customer N = number of bits. Evaluation Board This simple equation provides considerable insight into the Figure 3 is a 5 average, 64 K FFT of the AD9246 sampling a 2.3 noise performance of a data converter. MHz sine wave at 125 MSPS. Analog Devices’ ADC AnalyzerTM Software (www.analog.com/fifo) collects and processes the data MEASURING SUBPICOSECOND JITTER to report SNR without harmonics. From the plots, the SNR is Aperture uncertainty is readily determined by examining SNR 72.05 dBFS. without harmonics as a function of analog input frequency. Two measurements are required for the calculation. The first measurement is done at a sufficiently low analog input frequency that the effects of aperture uncertainty are negligible. Since jitter is negligible, Equation 6 can be simplified and rearranged to solve for ε, the “composite DNL.”

−SNR N 20 −×=ε 1102 (7) Here, SNR is the low frequency value just measured.

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Device: AD9246 0 Device No.: 1 Figure 5 overlays plots of Equation 5 for various jitter values –10 Avcc: 1.8 Volts (the sloped lines) with ideal, quantization noise limited Dvcc: 1.8 Volts –20 Encode: 125. MSPS performance at various resolutions (the horizontal lines), and is –30 Analog: 2.3 MHz a useful guide for quickly determining jitter limits based on SNR: 71.06 dB –40 SNRFS: 72.05 dBFS –50 analog input frequency and SNR requirements. UDSNR: 96.62 dB NF: 30.69 dB –60 100 SINAD: 70.87 dB –70 16 BITS Fund: –0.999 dBfs 2nd: –90.62 dBc –80 3rd: –86.59 dBc 2 3 –90 + 90 4th: –104.15 dBc 6 5th: –108.51 dBc –100 14 BITS 4 6th: –94.04 dBc 5 –110 WoSpur: –90.53 dBc + 0 0 80 0.5 .2 .12 2 p 1 5 p 5 THD: –84.55 dBc –120 s ps ps s ps SFDR: 86.59 dBc –130 12 BITS Noise Floor: –117.21 dBFS 0105 15202530354045505560 Samples: 65536 SNR (dB) 70 FREQUENCY (MHz) Windowing: None 01399-003 Figure 3. 2.3 MHz FFT 10 BITS 60 Using this value for SNR in Equation 7 gives a “composite DNL (ε)” for this converter of 3.09 LSB. 50 10 100 1000

Next, the degradation in SNR as a function of analog input INPUT (MHz) 01399-005 frequency is found. Figure 4 shows data from the same setup and Figure 5. Signal-to-Noise Ratio Due to Aperture Jitter clock, but using an analog input frequency of 201 MHz. Here, the CLOCK DISTRIBUTION noise floor has risen and the resulting SNR is 69.05 dBFS. System clocks commonly must be distributed to multiple Device: AD9246 0 converters, and additionally to the FPGAs, ASICs, and DSPs Device No.: 1 –10 Avcc: 1.8 Volts included in the signal chain. There are several ways to distribute Dvcc: 1.8 Volts –20 Encode: 125. MSPS clocks with the low jitter demanded by the converters. –30 Analog: 49.004 MHz SNR: 67.98 dB –40 SNRFS: 69.05 dBFS If the sample clock is generated as a sinewave, it can be –50 UDSNR: 93.4 dB distributed using power dividers and delivered to the ADC with NF: 33.69 dB –60 SINAD: 66.75 dB a transformer as shown in Figure 6. This solution is simple and –70 Fund: –1.069 dBfs 3 2 2nd: –78.21 dBc –80 works well for many applications, especially in situations 3rd: –74.41 dBc + –90 involving single-ended to differential conversion. 4th: –103.12 dBc 6 5th: –104.29 dBc –100 5 4 6th: –93.26 dBc –110 However, more often than not the clock is a logic signal sourced WoSpur: –90.65 dBc + THD: –72.85 dBc –120 directly from a PLL, VCO, or VCXO. In these cases, it is SFDR: 74.41 dBc –130 advantageous to use logic gates to fan out the signal and to drive the Noise Floor: –114.2 dBFS 0105 15202530354045505560 Samples: 65536 data converters. Table 1 summarizes the typical jitter that can be FREQUENCY (MHz) Windowing: None 01399-004 achieved with a variety of logic families. It should be noted that Figure 4. 201 MHz FFT many of the older families, and even current FPGAs, cannot deliver Using this SNR and the previous solution for ε, Equation 8 gives acceptable performance. Some newer, high-speed devices do provide acceptable jitter and have the ability to translate single- − 05.69 2 2 ⎛ ⎞ ⎛ + 092.31 ⎞ ended signals into differential signals as shown in Figure 7. ⎜10 20 ⎟ − ⎜ ⎟ ⎜ ⎟ 14 ⎝ ⎠ ⎝ 2 ⎠ Table 1. t = = rmsfs197 (9) a π ×102012 6 Gate Type Jitter FPGA1 33 to 50 ps This value, 197 fs, is the combined aperture uncertainty for the 74LS00 4.94 ps AD9246 plus the clock oscillator. Since total noise squared is the 74HCT00 2.20 ps sum of the squares of individual contributors, the jitter of the 74ACT00 0.99 ps ADC itself is readily determined if the jitter of the source clock MC100EL16 (PECL) 0.70 ps is known. Here a Wenzel ULN clock oscillator with about 50 fs AD9510 Clock Synthesis and Distribution 0.22 ps jitter is used, giving a jitter for the ADC of about 190 fs. These NBSG16 (Reduced Swing ECL) 0.20 ps simple measurements confirm that it is possible to measure very 1 Does not include the jitter introduced by input structure or internal routing small aperture uncertainty numbers using readily available gates, or the jitter associated with the use of internal DLL/PLL structures. hardware and simple numeric calculations. Based on product data sheet peak-to-peak values ranging from ±100 ps to ±300 ps peak.

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CLOCK ADT1–1WT In addition, the AD9510 includes many other features not SOURCE CLK+ 0.1µF AD9444 available in discrete logic such as selectable output types (LVDS, CLK– PECL, and CMOS) and programmable fine delays. Figure 10 HSMS2812 DIODES shows how the AD9510 can be used in a typical low jitter 1399-006 0 solution. Figure 6. Distribution and Differential Encode Options VS GND RSET CPRSET VCP VT DISTRIBUTION PLL 0.1µF REF AD9510 REF ENCODE REFIN R DIVIDER PHASE ECL/ CHARGE REFINB FREQUENCY CP PECL 0.1µF AD9444 DETECTOR PUMP N DIVIDER ENCODE SYNCB, FUNCTION RESETB PDB PLL STATUS SETTINGS

VT 01399-007 CLK1 CLK2 Figure 7. Active Differential Drive Circuit CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST LVPECL OUT0 Clock trees employing cascaded gates are commonly used in /1, /2, /3... /31, /32 digital circuits (see Figure 8), but jitter accumulates as the clock OUT0B LVPECL OUT1 progresses down the tree. /1, /2, /3... /31, /32 OUT1B LVPECL ADC ENCODE INPUT OUT2 /1, /2, /3... /31, /32 OUT2B ADC DATA LATCH SCLK LVPECL SYSTEM CLOCK SDIO SERIAL OUT3 CONTROL /1, /2, /3... /31, /32 SDO PORT OUT3B CSB LVDS/CMOS OUT4 DAC CLOCK INPUT /1, /2, /3... /31, /32 OUT4B LVDS/CMOS DACDATALATCH OUT5 /1, /2, /3... /31, /32 ΔT OUT5B (A) LVDS/CMOS OUT6 /1, /2, /3... /31, /32 ΔT SYSTEM CLOCK OUT6B LVDS/CMOS ADC ENCODE INPUT OUT7 /1, /2, /3... /31, /32 OUT7B (B) 01399-008 01399-009 Figure 8. Clock Distribution Chains Figure 9. AD9510 Clock Synthesis and Distribution

In a cascade of just three NBSG16 gates (one of the better 16 performers), the cumulative rms jitter increases to 350 fs, which AD6633 AD9786 TX is a significant impact on system performance of an IF sampling IF = ~190MHz MAIN TX system. It is better to avoid conventional clock trees altogether, 92.16MHz 491.52MHz and instead, approach clock generation and distribution as a LOOP FILTER 32.768MHz system level function. AD9510 DSP REFERENCE

Devices such as the AD9510 have optimized the clock paths to VCXO minimize total rms noise. By comparing Figure 8 and Figure 9, 92.16MHz 92.16MHz it is clear that the AD9510 offers the same function for clock 14 distribution as that in Figure 8, but with an additive jitter of AD6636 AD9246 RX only 220 fs. In addition, this part includes an ultra low noise IF = ~190MHz PLL similar to the ADF4106 that allows complete clock cleanup, MAIN RX synthesis, and distribution in a single package. 92.16MHz 92.16MHz 14 AD6636 AD9246 RX

IF = ~190MHz DIVERSITY

RX 01399-010 Figure 10. Typical Clock Distribution Application

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