Standard Cell Layout from VerilogHDL
Using the Design Mentor Graphics IC Studio
Santa Clara University
Department of Electrical Engineering
Prepared by Darshil Shah Under Guidance of Dr. Samiha Mourad & Dr. Richard Sun Date of Last Revision: September 21, 2009 Table of Contents
1. Objective……………………………………………………………………..……1
2. Setup & Preparation……………………………………………………………....1
3. Synthesize VerilogHDL code……………………………………………..………2
4. Launching Design Architect-IC…………………………………..……………….5
5. Schematic Entry………………………………………………………..………….6
6. Simulation……………………………………………………………………..…..9
7. Creating Design Viewpoint……………………………………………..………...9
8. Launching IC Station…………………………………………………………...... 9
9. Auto Placement and Routing…………………………………………...………..10
10. DRC & LVS Check………………………………………………………..…….18
1. Objective
This document contains a step-by-step tutorial for Mentor Graphics Design Architect tool to do generate layout from HDL for 16:1 Mux using ADK Library. Main objective of this tutorial is to use automatic Place & Route tool establish layout. 2. Setup & Preparation
The set of directives listed below is applicable to users of the Engineering Design Center at Santa Clara University. If you are working in a different environment please check with your system administrator.
The steps below are necessary only for the first time to setup the Mentor Graphics environment by changing the settings in your .profile file.
1. Add the following lines in your .profile: setup mentor-2008.1 alias swd=”export MGC_WD=\’pwd\’” export MGC_WD=/home/
1
3. Synthesize VerilogHDL Code
On Comman-Line : source .cshrc
The Verilog Netlist is generated using the Command-line Mode using Spectrum.
Command List for Spectrum can be found by executing: ¾ spectrum
Execute the script to generate the Verilog netlist using the following command on Command-Line: ¾ spectrum –file script_name
2
Copy Synthesis Libraries to your home directory using the command: ¾ cp /opt/mentor-2008.1/adk3_1/technology/leonardo/*.* /home/
Here is an example script_name for 16:1 Mux, set exclude_gates {PadOut PadInC} // To exclude the gates from netlist load_library tsmc018_typ // load Library read { mux_16to1.v mux_8to1.v mux_4to1.v mux_2to1.v } // reading all files in design optimize # -hierarchy preserve // used with optimize to keep the hierarch in design report_area -cell report_delay -critical_path set vhdl_write_use_packages {library ieee,adk; use ieee.std_logic_1164.all; use adk.adk_components.all;} apply_rename_rules -ruleset VERILOG auto_write mux_16to1_netlist.v
3
4
4. Launching Design Architect-IC
On command line ¾ To setup mentor: o source .cshrc ¾ To open Design Architect-IC : o adk_daic
This launches the Design Architect-IC v2008.1_1.1 window shown below.
Note: Unselect all: F2 key
5
5. Schematic Entry
To create the Schematic Sheet from the Design Atchitech-IC, follow the steps given below.
¾ Click File -> Import Verilog to create new schematic.
¾ Click Netlist file. o Netlist File: $MGC_WD/mux_16to1_netlist.v o Output Directory: $MGC_WD o Mapping file: $ADK/technology/adk_map.vmp ¾ Click OK
6
¾ Check the Message Area.
¾ Once Import Verilog Netlist is complete, Click File -> Open -> Schematic to open schematic.
¾ Click OK. ¾ Schematic will be as shown in next figure.
7
¾ Click on Check & Save in the schematic_edit palette. ¾ Open Miscellaneous -> Generate Symbol , to generate the symbol. ¾ Check & Save and close Symbol. ¾ Click on the Prep for Layout on right side palatte, to create the view point. ¾ Update LVS for create the netlist of the design. ¾ Close the DA-IC.
8
6. Simulation
Simulation of the design can be done using the same procedure as shown in Simulation PDF on http://www.dc.engr.scu.edu/mentortu/2007/dig_sim.pdf
7. Creating Design Viewpoint
On the command line:
adk_dve mux_16to1_netlist -technology tsmc018
8. Launching IC Station
¾ On the command line: adk_ic
Make sure the ADK_TECH is set to desired technology, e.g. tsmc018
This launches the IC Station v2008.1_1.1 window shown below.
9
9. Auto Placement and Routing
1. Create an IC cell
Cell Name:$MGC_WD/mux_16to1
Attach Library: $ADK/technology/ic/process/
Process : $ADK/technology/ic/process/
Rule File: $ADK/technology/ic/process/
EDMM Schematic Viewpoint: :$MGC_WD/mux_16to1/sdl
¾ Click OK.
10
¾ Familiarize yourself with the IC Palettes shown in figure. ¾ Click on File -> Library -> Attach /$ADK/technology/ic/process/
2. AutoFloorplan the IC Cell
¾ On IC Palettes, Click on Floorplan below ICblocks. It will open Floorplan Palette.
¾ Click on the Autofp.
11
¾ It will make floorplan according to the EDMM ViewPoint.
¾ Fit the cell boundry using Fit button.
¾ This boxes indicates the row into which cell will be place during the Placement.
3. AutoPlace the Standard Cell
¾ On IC Palettes, Click on Place & Route below ICblocks. It will open Place & Route Palette.
¾ Click on the StdCel under Auto Place.
¾ Click on the Options in AUTOPLA ST C, it will open Standard Cell Placer Option.
¾ Select the Placement method according the design requirement,
12
¾ Click OK.
¾ Row can be included by going back in Floorplan Palette.
¾ Add -> Add Row – Area.
¾ It will place all Standard Cell from the library as shown in below.
¾ Change the Standard Cell Placer option to change the placement.
13
4. AutoPlace Ports
¾ Click on Ports under Auto Place. It will open the window shown below.
14
¾ Click OK.
¾ It will place all ports along the port bar, as shown in window below.
5. AutoRoute IC Cell
¾ Click All under Auto Route in Place & Route Palette.
¾ Click on Options, set it according requirement. Keep it default for simple design.
¾ Route Method can be changed also.
o Global only or Global and Detail
o Power or Row power or Power and critical
15
¾ Click OK.
16
¾ Automatic routing is done.
¾ Next task is to check for errors.
¾ Click Checking -> Shorts- All nets then click Ok. Check errors.
¾ Find Overflow: Click Overflow under All route.
¾ Overflow can be routed using the IRoute ( Interactive Route ) under P & R Edit in Place & Route Palette.
¾ Add Text to all ports for LVS Check.
¾ Save the IC Cell.
17
10. DRC & LVS Check
¾ DRC & LVS Rule File: /applications/mentor/2008.1/adk3_1/technology/ic/process/tsmcXXX.rules
¾ DRC and LVS of the design can be done using the same procedure as shown in DRC & LVS PDF on http://www.dc.engr.scu.edu/mentortu/2007/dig_ver.pdf
18