, Inc.

M68MPB916Y3UM/D

March 1998

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. c M68MPB916Y3

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USER'S MANUAL

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© , INC., 1998; All Rights Reserved

For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

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. distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney

c fees arising out of, directly or indirectly, any claim of personal injury or death associated with n such unintended or unauthorized use, even if such claim alleges that Motorola was negligent

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, regarding the design or manufacture of the part.

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Motorola and the Motorola logo are registered trademarks of Motorola Inc. SDI is a trademark of Motorola Inc.

Motorola Inc. is an Equal Opportunity/Affirmative Action Employer.

For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

CONTENTS

CONTENTS

CHAPTER 1 GENERAL INFORMATION

1.1 INTRODUCTION ...... 1-1 1.2 SPECIFICATIONS...... 1-2

. 1.3 EQUIPMENT REQUIRED...... 1-2

. . 1.4 CUSTOMER SUPPORT...... 1-3

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CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION

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r o 2.1 INTRODUCTION ...... 2-1

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c 2.2 HARDWARE PREPARATION...... 2-1 u 2.2.1 Clock Select Header (W1)...... 2-4 d 2.2.2 VDDA Select Header (W2)...... 2-5

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o 2.2.3 Voltage Reference High Select Header (W3)...... 2-6

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i 2.2.4 Voltage Reference Low Select Header (W4)...... 2-7

2.2.5 MCU Clock Source Select Header (W5)...... 2-8

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e 2.2.6 Using a 32 KHz Clock...... 2-9

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2.2.7 MCU ID Code Select Header (W6)...... 2-10

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2.2.8 VSSA Insertion Point (E1) ...... 2-10

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2.3 MEVB CONFIGURATION...... 2-11

c 2.4 MPB – MMDS INSTALLATION...... 2-13

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e CHAPTER 3 MEVB QUICK START GUIDE

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F 3.1 INTRODUCTION ...... 3-1 3.2 CONFIGURING THE MPB...... 3-1 3.3 CONFIGURING THE MPFB...... 3-1 3.3.1 MPFB Memory Devices...... 3-1 3.3.2 MPFB Jumper Headers...... 3-2 3.4 MEVB INSTALLATION INSTRUCTIONS...... 3-3 3.4.1 Power Supply – MPFB Connection...... 3-4 3.4.2 Personal Computer – BDM Connection...... 3-5 3.5 SOFTWARE INSTALLATION...... 3-5

M68MPB16Y3UM/D For More Information On This Product, iii Go to: www.freescale.com Freescale Semiconductor, Inc.

CONTENTS

CHAPTER 4 MEVB SUPPORT INFORMATION

4.1 INTRODUCTION ...... 4-1

CHAPTER 5 MAPI SUPPORT INFORMATION

5.1 INTRODUCTION ...... 5-1

CHAPTER 6 SCHEMATIC DIAGRAMS

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. . 6.1 INTRODUCTION ...... 6-1

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, FIGURES

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t 2-1. MPB Jumper Headers and Insertion Point Location Diagram (top view)...... 2-2 c 5-1. MAPI Interface Connector Layout...... 5-1 u 5-2. MAPI Interface Connector P1 Pin Assignments ...... 5-2

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n 5-3. MAPI Interface Connector P2 Pin Assignments ...... 5-3

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5-4. MAPI Interface Connector P3 Pin Assignments ...... 5-4

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i 5-5. MAPI Interface Connector P4 Pin Assignments ...... 5-5

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TABLES

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1-1. MPB Specifications ...... 1-2

c 2-1. Jumper Header Types ...... 2-3

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2-2. MPB Jumper Header Descriptions ...... 2-3

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e 3-1. MPFB Quick Start Jumper Header Configuration...... 3-2 r 4-1. Logic Analyzer Connector J7 Pin Assignments ...... 4-2

F 4-2. Logic Analyzer Connector J8 Pin Assignments ...... 4-2 4-3. Logic Analyzer Connector J9 Pin Assignments ...... 4-3 4-4. Logic Analyzer Connector J10 Pin Assignments ...... 4-3 4-5. Logic Analyzer Connector J11 Pin Assignments ...... 4-4 4-6. Logic Analyzer Connector J12 Pin Assignments ...... 4-4 4-7. Logic Analyzer Connector J13 Pin Assignments ...... 4-6 4-8. Logic Analyzer Connector J14 Pin Assignments ...... 4-8

iv For More Information On This Product, M68MPB16Y3UM/D Go to: www.freescale.com Freescale Semiconductor, Inc.

CONTENTS

TABLES (continued)

4-9. Logic Analyzer Connector J15 Pin Assignments ...... 4-9 4-10. Logic Analyzer Connector J16 Pin Assignments ...... 4-9 4-11. Logic Analyzer Connector J17 Pin Assignments ...... 4-10 4-12. Logic Analyzer Connector J18 Pin Assignments ...... 4-11 4-13. Logic Analyzer Connector J19 Pin Assignments ...... 4-12 4-14. Logic Analyzer Connector J20 Pin Assignments ...... 4-12

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M68MPB16Y3UM/D For More Information On This Product, v Go to: www.freescale.com Freescale Semiconductor, Inc.

CONTENTS

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vi For More Information On This Product, M68MPB16Y3UM/D Go to: www.freescale.com Freescale Semiconductor, Inc.

GENERAL INFORMATION

CHAPTER 1 GENERAL INFORMATION

1.1 INTRODUCTION

This manual provides general information, hardware preparation, installation

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. instructions, a quick start guide, and support information for the M68MPB916Y3 . MCU Personality Board (MPB). The MPB is one component of Motorola's

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n modular approach to MC68HC16Y3 and MC68HC916Y3 Unit-

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based product development. This modular approach lets you easily configure our

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r development systems to fit your requirements.

o t The MPB may be used in either the M68MMDS1632 Motorola Modular c Development System (MMDS) or the M68MEVB1632 Modular Evaluation

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d Board (MEVB). Alternately, you may install the MPB directly in your target

n system if the target system includes an modular active probe interconnect (MAPI)

o interface. The MCU device on the MPB defines which MCU is

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i emulated/evaluated by the MMDS or MEVB. Both systems are invaluable tools

for designing, debugging, and evaluating MCU operation of the M68HC16 and

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M68300 MCU Families. By providing the essential MCU timing and I/O

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circuitry, these systems simplify user evaluation of prototype hardware/software

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products.

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a MPB product includes:

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s M68MPB916Y3 MCU Personality Board (MPB)

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• Plastic overlay for use with the MEVB – pin outs for the logic analyzer

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r connectors on the MPFB (specifically for the MC68HC916Y3 MCU) F • Documentation

M68MPB16Y3UM/D For More Information On This Product, 1-1 Go to: www.freescale.com Freescale Semiconductor, Inc.

GENERAL INFORMATION

1.2 SPECIFICATIONS

Table 1-1 lists MPB specifications.

Table 1-1. MPB Specifications

Characteristic Specifications

On-Board Clock Case style: 14 or 8-pin hybrid crystal clock oscillator

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. (frequency as required by MCU).

. c External Clock dc – 20.97 MHz (or maximum MCU allows).

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MCU I/O ports HCMOS compatible

, r Temperature

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t Operating 0° to +40° C

c Storage -40° to +85° C u Relative humidity 0 to 90% (non-condensing)

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Power requirements +5 Vdc ± 5% @ 500 mA (max.)

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Dimensions

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MCU Personality Board 3.25 x 3.25 in. (82.6 x 82.6 mm)

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1.3 EQUIPMENT REQUIRED

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The external requirements for MPB operation are either an MEVB or MMDS

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e system. MMDS operation requirements are described in the M68MMDS1632

e Motorola Modular Development System User's Manual, M68MMDS1632/D. r Operation requirements for the MEVB are described in this manual and the F M68MPFB1632 Modular Platform Board User's Manual, M68MPFB1632/D.

1-2 For More Information On This Product, M68MPB16Y3UM/D Go to: www.freescale.com Freescale Semiconductor, Inc.

GENERAL INFORMATION

1.4 CUSTOMER SUPPORT

For information about a Motorola distributor or sales office near you call:

AUSTRALIA, Melbourne – (61-3)887-0711 JAPAN, Fukuoka – 81-92-725-7583 Sydney – 61(2)906-3855 Gotanda – 81-3-5487-8311 Nagoya – 81-52-232-3500 BRAZIL, Sao Paulo – 55(11)815-4200 Osaka – 81-6-305-1802

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. Sendai – 81-22-268-4333 . CANADA, B. C., Vancouver – (604)606-8502 Takamatsu – 81-878-37-9972 c ONTARIO, Toronto – (416)497-8181 Tokyo – 81-3-3440-3311

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I ONTARIO, Ottawa – (613)226-3491

, QUEBEC, Montreal – (514)333-3300 KOREA, Pusan – 82(51)4635-035 r Seoul – 82(2)554-5118 o CHINA, Beijing – 86-10-68437222 t MALAYSIA, Penang – 60(4)2282514 c DENMARK – (45)43488393 u MEXICO, Mexico City – 52(5)282-0230 d FINLAND, Helsinki – 358-9-6824-400 Guadalajara – 52(36)21-8977

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FRANCE, Paris – 33134 635900 PUERTO RICO, San Juan – (809)282-2300

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GERMANY, SINGAPORE – (65)4818188

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Langenhagen/Hannover – 49(511)786880

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Munich – 49 89 92103-0 SPAIN, Madrid – 34(1)457-8204

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Nuremberg – 49 911 96-3190

e Sindelfingen – 49 7031 79 710 SWEDEN, Solna – 46(8)734-8800

l Wiesbaden – 49 611 973050

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SWITZERLAND, Geneva – 41(22)799 11 11

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HONG KONG, Kwai Fong – 852-6106888 Zurich – 41(1)730-4074

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Tai Po – 852-6668333

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TAIWAN, Taipei – 886(2)717-7089

e INDIA, Bangalore – (91-80)5598615

r THAILAND, Bangkok – 66(2)254-4910 F ISRAEL, Herzlia – 972-9-590222 UNITED KINGDOM, Aylesbury – 441(296)395-252 ITALY, Milan – 39(2)82201 UNITED STATES, Phoenix, AZ – 1-800-441-2447

For a list of the Motorola sales offices and distributors: http://www.mcu.motsps.com/sale_off.html

M68MPB16Y3UM/D For More Information On This Product, 1-3 Go to: www.freescale.com Freescale Semiconductor, Inc.

GENERAL INFORMATION

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1-4 For More Information On This Product, M68MPB16Y3UM/D Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION

2.1 INTRODUCTION

This chapter provides unpacking instructions, hardware preparation information, and installation instructions for the MPB.

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. . When you unpack the MPB from its shipping carton, verify that all items are in c good condition. Save packing material for storing and shipping the MPB.

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r o Should the MPB arrive damaged, save all packing material, and

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c contact the carrier's agent.

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2.2 HARDWARE PREPARATION

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as how to configure the MPB for system operation. MPB installation in the

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MMDS and MEVB are also described.

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The MPB has been factory tested and is shipped with installed jumpers. A jumper

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l installed on a jumper header provides a connection between two points in the

a MPB circuit. There are two types of jumper headers on the MPB: three-pin and

c two-pin with a cut-trace short. A cut-trace short has a copper trace between the

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feed-through holes (bottom or solder side of the MPB). Table 2-1 describes each

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type of jumper header.

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F There are five jumper headers on the MPB (Table 2-2 is a quick reference guide for the jumper headers). These jumper headers may be re-configured to customize MPB functionality. The following paragraphs are a detailed description of each jumper header function. There is also an insertion point (E1) for connecting an external ground. Figure 2-1 shows the location of the MPB jumper headers and the insertion point.

NOTE Verify that all socketed parts are seated in their sockets.

M68MPB16Y3UM/D 2-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

CAUTION Depending on the application, it may be necessary to cut the wiring trace short (cut-trace short) on W2. Be careful not to cut adjacent PCB wiring traces or too deep on the multi-layer circuit board.

NOTE If the cut-trace short on a jumper header is cut, a user-supplied fabricated jumper must be installed on the jumper header to return the MPB to its default setting.

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Figure 2-1. MPB Jumper Headers and Insertion Point Location Diagram (top view)

2-2 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

Table 2-1. Jumper Header Types

Jumper Header Type Symbol Description

two-pin with cut-trace Two-pin jumper header with cut-trace short, designated as WX short (X = the jumper header number). After removing the cut-trace short, use a fabricated jumper to return the jumper header to its factory default state.

three-pin Three-pin jumper header, designated as WX (X = the jumper header number). Use a fabricated jumper to create a short between two of the three pins of the jumper header.

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. c Table 2-2. MPB Jumper Header Descriptions

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t W1 Jumper between pins 1 and 2 (factory default); selects the MPB on-board c 1 crystal clock source. u 2 d 3 Jumper between pins 2 and 3; selects an external clock source as the MCU

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EXTAL input signal.

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Jumper installed or cut-trace short intact (factory default); selects the on-board c W2 1

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VDDA power source.

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No jumper or cut-trace short; use an external power source by connecting an

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external power source to W2 pin 2.

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NOTE

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Jumper header W2 is not populated by the factory.

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c W3 1 Jumper installed on pins 1 and 2 (factory default); selects the MPB on-board

s VRH power source.

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e 3 Jumper installed on pins 2 and 3; selects external VRH power source.

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r W4 1 Jumper installed on pins 1 and 2 (factory default); selects the MPB on-board

F 2 VRL power source. 3 Jumper installed on pins 2 and 3; selects external VRL power source.

W5 1 Jumper installed on pins 1 and 2 (factory default); selects the MCU-internal 2 phase-lock-loop frequency synthesizer as the system clock. 3 Jumper installed on pins 2 and 3; selects the EXTAL input as the system clock. The MCU-internal phase-lock-loop frequency synthesizer is disabled.

W6 1 Jumper installed on pins 1 and 2 (factory default); selects an MC68HC916Y3 2 MCU as the MCU type for this MPB. 3 Jumper installed on pins 2 and 3; selects an MC68HC16Y3 MCU as the MCU type for this MPB.

M68MPB16Y3UM/D 2-3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.1 Clock Select Header (W1)

Jumper header W1 connects the MCU external clock (EXTAL) pin to either an on-board or external (target system) clock source. The drawing below shows the factory configuration: fabricated jumper on pins 1 and 2. This configuration selects the MPB on-board clock source; crystal oscillator in socket at located Y1. (This crystal provides for operation at the maximum rate the MCU allows via the internal phase-locked loop or direct clock input.) When the MPB is installed in the active probe or directly on a target system and the target system clock is used

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. as the MPB clock, move the fabricated jumper to W1 pins 2 and 3. This connects . the MCU EXTAL pin to the MAPI bus input pin. The frequency of the external

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n clock signal can be from dc to 20.97 MHz (or to the maximum the MCU allows).

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NOTE

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You can not drive the MPB clock circuit from an external source

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source is used to drive the MPB clock circuit, always use a logic

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driven clock such as a hybrid oscillator.

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2-4 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.2 VDDA Select Header (W2)

Jumper header W2 selects the MPB VDDA power source; either MPB power (VDDI) or an external source. The drawing below shows the factory configuration: cut-trace short on pins 1 and 2. This configuration connects filtered VDDI to VDDA. To use an external power source, remove the cut-trace short from W2 pins 1 and 2. Then connect the external power source to W2 pin 2. Removal of the cut-trace short isolates the MCU VDDA pin from the other MPB circuitry. Isolation lets you connect a precision VDDA source for accurate 10-bit analog/digital (A/D) generation. When connecting an external VDDA power

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. supply to the MPB connect the power supply ground to insertion point E1. For . more information on A/D generation refer to the Analog-To-Digital Converter

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n Reference Manual, ADCRM/AD.

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NOTES

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If the cut-trace short has been cut, a fabricated jumper must be

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installed on W2 to return it to the factory configuration.

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c Jumper header W2 is not populated by the factory.

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M68MPB16Y3UM/D 2-5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.3 Voltage Reference High Select Header (W3)

Jumper header W3 selects the voltage reference high (VRH) source; either MPB power (VDDA) or an external VRH source. The drawing below shows the factory configuration: fabricated jumper on pins 1 and 2. This configuration selects VDDA as the VRH source. To use an external VRH source, first place the fabricated jumper on W3 pins 2 and 3. Then connect the MCU VRH pin to the external VRH source. Each configuration defines which method is best when connecting the MCU VRH pin to the external VRH source:

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. • •MPB/MPFB – connect via the MPFB logic analyzer connector (refer to c Chapter 4 for the appropriate logic analyzer pin)

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•MPB/MMDS1632 – connect via the VRH pin of the target MCU socket

, r • •MPB/Target System – connect via the VRH pin of the target system

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t MAPI bus

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Alternately, you may remove the jumper and wire-wrap directly to W3 pin 2.

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Connecting directly to pin 2 is an option regardless of the configuration.

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2-6 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.4 Voltage Reference Low Select Header (W4)

Jumper header W4 selects the voltage reference low (VRL) source; either MPB power (VSSA) or an external VRL source. The drawing below shows the factory configuration: fabricated jumper on pins 1 and 2. This configuration selects VSSA as the VRL source. To use an external VRL source, first place the fabricated jumper on W4 pins 2 and 3. Then connect the MCU VRL pin to the external VRL source. Each configuration defines which method is best when connecting the MCU VRL pin to the external VRL source: •

. •MPB/MPFB – connect via the MPFB logic analyzer connector (refer to

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. Chapter 4 for the appropriate logic analyzer pin) c • •MPB/MMDS1632 – connect via the VRL pin of the target MCU socket

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, •MPB/Target System – connect via the VRL pin of the target system r MAPI bus

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d Alternately, you may remove the jumper and wire-wrap directly to W4 pin 2.

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Connecting directly to pin 2 is an option regardless of the configuration.

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W4

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M68MPB16Y3UM/D 2-7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.5 MCU Clock Source Select Header (W5)

Jumper header W5 selects the MCU clock; either the MCU-internal phase-lock- loop frequency synthesizer or the EXTAL input. The drawing below shows the factory configuration: fabricated jumper on pins 1 and 2. This configuration selects the MCU-internal phase-lock-loop frequency synthesizer as the clock. To use the EXTAL input as the clock, place the fabricated jumper on 2 and 3.

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NOTE

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J14 pin-4 and W16 on the MPFB are marked MODCLK, but this

m signal, when using an M68HC916Y3, is FASTREF. The

e M68HC916Y3 MEVB overlay is correct and marked FASTREF.

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Use W16 on the MPFB to select the MCU PLL clock input speed.

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2-8 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.6 Using a 32 KHz Clock

The factory installed crystal oscillator in location Y1 is rated at 4.194 megahertz. You may change Y1 to change the clock speed of the MPB. The only other oscillator you may install is 32 kilohertz. If you change Y1 to the slower value (32 KHz) you must replace the following capacitors and resistor (see diagram below): C60 – 1 µf C56 – 1 µf R52 – 18 kΩ

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M68MPB16Y3UM/D 2-9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.2.7 MCU ID Code Select Header (W6)

Jumper header W6 selects the MCU ID code; either the M68HC16Y3 MCU or M68HC916Y3 MCU. The drawing below shows the factory configuration: fabricated jumper on pins 1 and 2. Use this configuration when an M68HC16Y3 MCU is installed on the MPB. To use the MPB with an M68HC916Y3 MCU installed, place the fabricated jumper on 2 and 3.

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. W6

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c These jumper settings only apply to when using the M68HC916Y3

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MPB in an MMDS1632.

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2.2.8 VSSA Insertion Point (E1)

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Insertion point E1 is a plate through hole that lets you connect an external ground

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e to the MPB VSSA pin (refer to paragraph 2.2.2). Insert an external ground wire in

e E1 and solder it into the plate through hole.

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NOTE Insertion point E1 is not populated by the factory.

2-10 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.3 MEVB CONFIGURATION

The MEVB contains: • MPB – MCU-device-specific board that defines the MCU to be evaluated. • M68MPFB1632 Modular Platform Board (MPFB) – which provides the interface connections to the host computer, logic analyzer connections, and the platform for installing the MPB. For more information about the MPFB and MEVB system connections refer to the M68MPFB1632 Modular Platform Board User's Manual, M68MPFB1632/D. Chapter 3 of this

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. manual contains information to help you get started using your MEVB.

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, CAUTION

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To install the MPB on the MPFB (refer to Figure 2-2):

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m 1. Inspect all connectors for bent or damaged pins.

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2. Align the MPB reference mark with the MPFB reference mark.

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3. Rotate the MPB until the four MAPI bus connectors on its bottom mate

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l with the MAPI bus connectors on the top of the MPFB. (There is only one

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way to connect the MPB and the MPFB.)

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4. Firmly press the MPB onto the MPFB.

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F CAUTION Support the bottom side of MPFB when installing the MPB on the MPFB. Excessive flexing of the MPFB could damage the printed circuit.

M68MPB16Y3UM/D 2-11 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

.

.

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c

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t

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e

S

e

l Figure 2-2. MPB – MPFB Interconnection (with SDI interface connector)

a

c

s

e

e

r

F

After you have installed the MPB, install the plastic overlay on the MPFB: place the overlay over logic analyzer connectors J12 through J20 and press down. Holes in the overlay slide down over plastic clips on the MPFB. These clips hold the overlay in place.

2-12 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

HARDWARE PREPARATION AND INSTALLATION

2.4 MPB – MMDS INSTALLATION

The M68MMDS1632 Motorola Modular Development System (MMDS) consists of the station module and an active probe. The active probe consists of a three board set, two cables, and a box: • MPB – MCU-device-specific board that defines the MCU to be evaluated. • Enhanced Target Control Board (TCB) – the interface between the MPB, target system, and the station module. The TCB must be purchased separately. For more information about the TCB refer to the MMDS1632

. Motorola Modular Development System User's Manual,

. . MMDS1632UM/D. c • n Package Personality Board (PPB) – the board that connects the active probe

I

to the target system. The PPB must be purchased separately. For more

,

r information about the PPB refer to the appropriate PPB configuration o guide. t • c Active probe cables (2) – the interface between the active probe and the u station module. 01-RE90340W01 REV 0 and 01-RE90341W01 REV 0 are d printed on the active probe cables. The active probe cables come with the

n

TCB. For more information about the active probe cables refer to the

o

MMDS1632 Motorola Modular Development System User's Manual,

c

i

MMDS1632UM/D.

m • Active probe box – the protective enclosure for the TCB.

e

S

CAUTION

e

l Turn off MMDS and target system power when installing or

a removing MMDS components. Sudden power surges could

c

damage MMDS and target system integrated circuits.

s

e

To configure an active probe (refer to Figure 2-3):

e r 1. Inspect all connectors for bent or damaged pins.

F 2. Rotate the MPB until the four MAPI bus connectors on its bottom mate with the MAPI bus connectors on the top of the TCB. (There is only one way to connect the MPB and the TCB.) Firmly press the MPB and the TCB together. 3. Rotate the PPB until the four MAPI bus connectors on its top mate with the MAPI bus connectors on the bottom of the TCB. (There is only one way to connect the PPB and the TCB.) Firmly press the PPB and the TCB together.

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HARDWARE PREPARATION AND INSTALLATION

4. Connect one end of the 01-RE90341W01 REV 0 active probe cable to connector P6 on the MMDS control board; connect the other end to connector J6 on the TCB. Connect one end of the 01-RE90340W01 REV 0 active probe cable to connector P5 on the MMDS control board; connect the other end to connector J5 on the TCB. Secure the connector clamps on TCB connectors J5 and J6. The active probe is now ready to connect to the target system (refer to the PPB configuration guide for information on connecting the active probe to the target system.)

.

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Figure 2-3. Active Probe Interconnection (with Active Probe Box)

2-14 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB QUICK START GUIDE

CHAPTER 3 MEVB QUICK START GUIDE

3.1 INTRODUCTION

This quick start guide is intended for the user who may not be familiar with Motorola's development tools. This chapter explains the MEVB hardware and

.

. software set-up for M68MEVB916Y3 operation. Hardware set-up consists of . configuring the MPB and MPFB jumper headers. While software set-up consists

c

n of installing and running the appropriate macro script file within the debugger.

I

,

r For the purpose of this quick start guide the MPB jumper headers should be

o configured in their default positions. Chapter 2 of this manual contains the default t jumper header settings for the MPB.

c

u

d

n 3.2 CONFIGURING THE MPFB

o

c The MPFB includes jumper-selectable options such as chip select usage, memory

i

type selection and memory size selection for the pseudo ROM sockets, and reset

m

data control.

e

S

e 3.2.1 MPFB Memory Devices

l

a

Pseudo ROM refers to memory locations U2 & U4. The two pseudo ROM sockets

c

s provide a generic memory socket, and accepts a variety of RAM, EPROM, or

e EEPROM devices. The pseudo ROM sockets, as shipped from the factory, contain

e two 32K x 8 RAM devices. These memory are 28-pin package devices.

r

F

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MEVB QUICK START GUIDE

3.2.2 MPFB Jumper Headers

Configure your MPFB jumper headers per the instructions in Table 3-1. Table 3-1 contains information exclusively intended for quick start and ignores the other jumper headers.

Table 3-1. MPFB Quick Start Jumper Header Configuration

. Jumper

.

. Header Type Description

c

n W2 1 2 3 Install a jumper on pins 1 and 2 to configure pin 1 of the memory devices in the

I

pseudo ROM sockets (U2 & U4) as a standard address line.

,

r W3 1 2 3 Install a jumper on pins 1 and 2 to indicate that the memory devices in the

o

t pseudo ROM sockets (U2 & U4) have 28-pins.

c

u W4 1 2 3 Install a jumper on pins 1 and 2 to set the pseudo ROM port size (memory data

d width) as word.

n

W5 1 2 3 Install a jumper on pins 2 and 3 to enable the PRU.

o

c

i

W6 1 2 3 W6 selects the MCU operation mode. Each 3-pin jumper header set

m

corresponds to an MCU data line. While the reset pin is low, the reset data

e

values are driven on the data bus (D0 – D15). (The MEVB reset data circuit is

S

open drain; a high state is provided via a pull-up resistor.) Each reset data line

e

may be set high (H) or low (L). Consult the appropriate MCU user's manual,

l

data book, or technical summary for reset data information.

a

c

s

e

e

r

F

W10 1 2 Install a jumper on pins 1 and 2 to indicate that RAM is installed in the pseudo 3 4 ROM sockets (U2 & U4). 5 6

W12 1 2 Install a jumper on pins 3 and 4 to indicate that the two devices installed in the 3 4 5 6 pseudo ROM sockets (U2 & U4) are 32K x 8. 7 8 9 10

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MEVB QUICK START GUIDE

Table 3-1. MPFB Quick Start Jumper Header Configuration (continued)

Jumper Header Type Description

W14 1 2 3 Jumper header W14 selects the MCU signal for the memory devices in the fast RAM sockets (U9 & U10) and pseudo ROM sockets (U2 & U4). Pins 1 and 2 select the MCU chip select for the memory devices in the fast RAM sockets. While pins 2 and 3 of jumper header W14 select the chip select for the memory devices in the pseudo ROM sockets.

Jumper installed on CSBOOT pins 2 and 3 (factory default); use CSBOOT as

.

. the memory device chip enable for memory devices in the pseudo ROM

. sockets. c

n

I

W16 1 2 No jumper installed; the MCU FASTREF signal is pulled high (logic 1) via a

,

r resistor during reset.

o t NOTE

c

u J14 pin-4 and W16 on the MPFB are marked MODCLK, but this

d signal, when using an M68HC16Y3, is FASTREF. The M68HC16Y3

n MEVB overlay is correct and marked FASTREF. Use W16 on the

o MPFB to select the MCU PLL clock input speed.

c

i

W17 1 2 No jumper installed; the BERR signal is pulled high (logic 1) via a resistor

during reset.

m

e

W18 1 2 3 Install a jumper on pins 1 and 2 for unrestricted writes to the memory devices

S

in the pseudo ROM sockets (U2 & U4).

e

l

W19 1 2 3 Install a jumper on pins 1 and 2 to ground the A19 signal to the MPFB memory

a

arrays.

c

s

W22 1 2 3 Install a jumper on pins 2 and 3 to select the evaluation MCU (on the MPB) as

e

an M68HC16 MCU device.

e

r

F

3.3 MEVB INSTALLATION INSTRUCTIONS

MEVB installation requires a user-supplied power supply and host computer. The host computer must have a parallel port and must run MS-DOS, as required by ICD16. The following paragraphs explain MPFB connections. Refer to Chapter 2 for instructions to interconnect the MPB and MPFB.

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MEVB QUICK START GUIDE

3.3.1 Power Supply – MPFB Connection

Use MPFB connector J5 to connect a user-supplied power supply to the MEVB. Contact 1 is ground; black lever. Contact 2 is VDD (+5 volts); red lever. Use 20 or 22 AWG wire for power connections. For each wire, trim back the insulation 1/4 in. (.635 cm), lift the appropriate lever of J5 to release tension on the contacts, then insert the bare wire into J5 and close the lever. The MEVB requires a +5Vdc @ 1.0 amp power supply for operation. A 1.5 amp fuse is installed on the MPFB +5Vdc power supply input line.

.

.

.

c

n

I BLK

, RED

r

o

t

c

u

d

n GND

o

c

i

J5

m

e

S +5V

e

l

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s

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e

r

F CAUTIONS Do not use wire larger than 20 AWG in connector J5. Such wire could damage the connector. Turn off MEVB power when installing or removing the MPB from the MPFB. Sudden power surges could damage MEVB integrated circuits.

3-4 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB QUICK START GUIDE

3.3.2 Personal Computer – BDM Connection

Personal computer communication with the MEVB requires background debug mode (BDM) hardware. Connect your BDM hardware between your computer’s I/O port and the BDM header on the MPFB (MPFB connector J6). The drawing below shows signal assignments for connector J6. For additional information about your BDM software/hardware, including debugging and assembly information, see the appropriate user's manual.

.

.

. J6

c DS 1 •• 2 BERR*

n

I

••

, GND 3 4 BKPT* r ••

o GND 5 6 FREEZE t ••

c RESET 7 8 DSI u +5 Vdc 9 ••10 DSO

d

n

o

c

i

m 3.4 SOFTWARE INSTALLATION

e

S After you have set up the MEVB hardware you must install the software on your

computer. Follow the installation procedure in the appropriate software operations

e

l

manual.

a

c

The MCU must be initialized before the MEVB will function. The following is

s

one possible initialization for the MPB16Y3. You may adapt this example to your

e

e debugger. This initialization enables the maximum system clock frequency and r disables the software watchdog while enabling the bus monitor. CSBOOT is set to F zero-wait state and the block size set to 64K starting at $00000. The SRAM is enabled to reside at $10000 with the stack pointer initialized at $103FE and the instruction pointer (IP) initialized to $00200 (PK=0, IP=200).

Load your program at address $00200.

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MEVB QUICK START GUIDE

Below is the MPBY3.ICD initialization macro program listing. symbol SCIMCR FFA00 symbol SYNCR FFA04 symbol CSBARBT FFA48 symbol CSORBT FFA4A symbol START 00200 dmmw SCIMCR 40CF Set module mapping to $FFF000-$FFFFFF dmmw SYNCR B000 Set system clock frequency to 16.78 MHz watchdog Disable the watcdog timer dmmw CSBARBT 0003 Change CSBOOT block size to 64K

.

. dmmw CSORBT 7830 Change wait state to zero . mdf6 START Display program in PMM window c pk=0 Initialize CPU registers

n

I a=AA

, b=BB r e=0000

o t ix=0000 c iy=0000 u iz=0000 d hr=0000

n

ir=0000

o

k=0000

c

i sp=03fe Initialize the stack pointer

sk=1

m

symbol RAMBAH FFB04

e

symbol RAMMCR FFB00

S

dmmw RAMBAH 0001 Set SRAM base address

e

l dmmb RAMMCR 00 Enable SRAM array

a dmml 10000 4D6F746F Check SRAM: write Motorola 68HC16 advanced MCUs

c dmml 10004 726F6C61

s dmml 10008 20363848

e

dmml 1000C 43313620

e dmml 10010 41647661 r dmml 10014 6E636564

F dmml 10018 20204D43 dmml 1001C 55732020 dmml 10020 36384843 mdf3 10000 Display SRAM in DMM window ip=START Start entering your program here

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MEVB SUPPORT INFORMATION

CHAPTER 4 MEVB SUPPORT INFORMATION

4.1 INTRODUCTION

The information in this chapter is relevant when the MPB is used in an MEVB (the MPB installed on a MPFB). Signals on the MPFB logic analyzer connectors

.

. are defined by the MPB type. The tables of this chapter describe MPFB logic . analyzer connector signals when an M68MPB9916Y3 is installed on the MPFB.

c

n The signal descriptions on J12 – J20 are the logic analyzer pin-outs on the plastic

I

overlay supplied with the MPB.

,

r

o NOTE

t

c The signal descriptions in the following tables are for quick u reference only. The MC68HC916Y3 User's Manual, d MC68HC916Y3UM/AD, contains a complete description of the

n

MC68HC916Y3 MCU signals.

o

c

i

m

e Also contained in this chapter are MAPI bus interface layout and pin assignments

S information for MPB connectors P1, P2, P3, and P4.

e

l

Tables 4-1 through 4-14 list pin assignments for MPFB connectors J7 through

a

J20.

c

s

Table 4-1. Logic analyzer connector J7 Table 4-8. Logic analyzer connector J14

e

e Table 4-2. Logic analyzer connector J8 Table 4-9. Logic analyzer connector J15

r

F Table 4-3. Logic analyzer connector J9 Table 4-10. Logic analyzer connector J16

Table 4-4. Logic analyzer connector J10 Table 4-11. Logic analyzer connector J17

Table 4-5. Logic analyzer connector J11 Table 4-12. Logic analyzer connector J18

Table 4-6. Logic analyzer connector J12 Table 4-13. Logic analyzer connector J19

Table 4-7. Logic analyzer connector J13 Table 4-14. Logic analyzer connector J20

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MEVB SUPPORT INFORMATION

Table 4-1. Logic Analyzer Connector J7 Pin Assignments

Pin Mnemonic Signal

1, 2 SPARE No connection

3 OE(ALL) I/O PRU OUTPUT ENABLE – Input, active high; when low disables all PRU outputs.

4 – 11 PEPAR7 – PEPAR OUTPUTS – Output signals that show the PEPAR0 complement (negated contents) of the PEPAR register.

.

. . 12 – 19 PE7 – PE0 PORT E I/O SIGNALS – PRU replacement of the Port c E function.

n

I

20 GND GROUND

,

r

o t Table 4-2. Logic Analyzer Connector J8 Pin Assignments

c

u Pin Mnemonic Signal

d

n

1, 2 SPARE No connection

o

c

3 OE(ABG) I/O PRU OUTPUT ENABLE – Input, active high; when

i

low disables port A, port B, and port G outputs.

m

e 4 – 11 PA7 – PA0 PORT A I/O SIGNALS – PRU replacement of the Port

A function.

S

e

12 – 19 PB7 – PB0 PORT B I/O SIGNALS – PRU replacement of the Port

l

B function.

a

c 20 GND GROUND

s

e

e

r

F

4-2 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-3. Logic Analyzer Connector J9 Pin Assignments

Pin Mnemonic Signal

1, 2 SPARE No connection

3 OE(H) I/O PRU OUTPUT ENABLE – Input, active high; when low disables the port H outputs.

4 – 11 PH7 – PH0 PORT H I/O SIGNALS – PRU replacement of the Port H function.

. 12 – 19 PG7 – PG0 PORT G I/O SIGNALS – PRU replacement of the Port

.

. G function.

c

n 20 GND GROUND

I

,

r

o Table 4-4. Logic Analyzer Connector J10 Pin Assignments

t c Pin Mnemonic Signal

u d 1 +5V +5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A)

n

used by the MEVB logic circuits. (To make this pin no

o

connection, remove the jumper from header on the

c MPFB.)

i

m

2 SPARE No connection

e

3 AS ADDRESS STROBE – Active-low output signal that

S

indicates whether a valid address is on the address

e

bus.

l

a

4 – 19 A15 – A0 ADDRESS BUS BITS 15 – 0 – Sixteen bits of the 24-bit

c

address bus.

s

e

20 GND GROUND

e

r

F

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MEVB SUPPORT INFORMATION

Table 4-5. Logic Analyzer Connector J11 Pin Assignments

Pin Mnemonic Signal

1 +5V +5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A) used by the MEVB logic circuits. (To make this pin no connection, remove the jumper from header on the MPFB.)

2 SPARE No connection

.

. 3 DS DATA STROBE – Active-low output signal. During a

. read cycle, indicates that an external device should

c place valid data on the data bus. During a write cycle,

n

I indicates that valid data is on the data bus.

, r 4 – 19 D15 – D0 DATA BUS 15 – 0 – 16 bits of the MCU bi-directional o data bus lines.

t c 20 GND GROUND

u

d

n

Table 4-6. Logic Analyzer Connector J12 Pin Assignments

o

c

i

Pin Mnemonic Signal

m

1, 2 SPARE No connection

e

S 3 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MCU

internal system clock.

e

l

4 BERR BUS ERROR – Active-low signal that indicates that a

a

memory access error has occurred.

c

s

5 BKPT / BREAKPOINT – Active-low input signal that signals a

e

hardware breakpoint to the CPU.

e r DSCLK Development Serial Clock – Clock input signal for the F background debug mode.

6 FREEZE FREEZE – Output signal that indicates the CPU has acknowledged a breakpoint. QUOT QUOTIENT OUT – Output signal that furnishes the quotient bit of the polynomial divider for test purposes.

7 LAT-DSO / LATCHED INSTRUCTION PIPE 0 – Latched output (Latched signal of the first state of IPIPE0 for CPU16-based IPIPE0) MCUs; indicates instruction pipeline activity.

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MEVB SUPPORT INFORMATION

Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)

Pin Mnemonic Signal

8 LAT-DSI LATCHED INSTRUCTION PIPE 1 – Latched output (Latched IPIPE1) signal of the first state of IPIPE1 for CPU16-based MCUs; indicates instruction pipeline activity.

9 DSO / DEVELOPMENT SERIAL OUT – Serial data output signal for background debug mode. (IPIPE0) INSTRUCTION PIPE 0 for CPU16-based MCUs.

.

.

. 10 DSI / DEVELOPMENT SERIAL IN – Serial data input signal c for background debug mode.

n

I

(IPIPE1) INSTRUCTION PIPE 1 for CPU16-based MCUs.

, r 11 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low o input signal that allows asynchronous data transfers

t and dynamic bus sizing between the MCU and external

c devices.

u d 12 DSACK0 DATA AND SIZE ACKNOWLEDGE 0 – Active-low

n

input signal that allows asynchronous data transfers

o

and dynamic bus sizing between the MCU and external

c

i devices.

m 13 FC2 / FUNCTION CODE 2 – Output signal that identifies the

e

processor state and address space of the current bus

S cycle.

e CS5 CHIP SELECT 5 – Output signal that selects peripheral

l

or memory devices at programmed addresses.

a

c

14 FC1 FUNCTION CODE 1 – Output signal that identifies the

s

processor state and address space of the current bus

e

cycle.

e r 15 FC0 / FUNCTION CODE 0 – Output signal that identifies the F processor state and address space of the current bus cycle. CS3 CHIP SELECT 3 – Output signal that selects peripheral or memory devices at programmed addresses.

16 SIZ1 TRANSFER SIZE – Active-high output signals that Indicates the number of bytes to be transferred during a bus cycle.

17 SIZ0 TRANSFER SIZE 0 – Active-high output signals that Indicates the number of bytes to be transferred during a bus cycle.

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MEVB SUPPORT INFORMATION

Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)

Pin Mnemonic Signal

18 R/W READ/WRITE – Active-high output signal that indicates the direction of data transfer on the bus.

19 BGACK / BUS GRANT ACKNOWLEDGE – Active-low input signal that indicates that an external device has assumed bus mastership.

.

. CSE EMULATOR CHIP SELECT – Output signal that

. selects external emulation devices at internally-mapped

c addresses. CSE is used to emulate I/O ports.

n

I

, 20 GND GROUND

r

o t Table 4-7. Logic Analyzer Connector J13 Pin Assignments

c

u

d Pin Mnemonic Signal

n

1 +5V +5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A)

o

used by the MEVB logic circuits. (To make this pin no

c

i

connection, remove the jumper from header on the

MPFB.)

m

e

2 SPARE No connection

S

3 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low

e

l input signal that allows asynchronous data transfers

a and dynamic bus sizing between the MCU and external

c

devices.

s

4

e PULL-UP Not connected; pulled high through a resistor on the

e MPB.

r

F 5 HALT HALT – Active-low input/output signal that suspends external bus activity, to request a retry when used with BERR, or for single-step operation.

6 AS ADDRESS STROBE – Active-low output signal that indicates that a valid address is on the address bus.

7 DS DATA STROBE – Active-low output signal. During a read cycle, indicates that an external device should place valid data on the data bus. During a write cycle, indicates that valid data is on the data bus.

4-6 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued)

Pin Mnemonic Signal

8 BR / BUS REQUEST – Active-low input signal that indicates that an external device requires bus mastership. CS0 CHIP SELECT 0 – Output signal that selects peripheral or memory devices at programmed addresses.

9 BG / BUS GRANT – Active-low output signal that indicates that the MCU has relinquished the bus.

.

.

. CSM INTERNAL MODULE CHIP SELECT – Active-low c output signal that selects external emulation devices at n internally-mapped addresses. CSM is used to emulate

I

memory.

,

r 10 CSBOOT BOOT CHIP SELECT – An active-low output chip

o

t select for external boot startup ROM

c 11 CLKOUT SYSTEM CLOCK OUTPUT – MCU internal clock

u output signal.

d

n

12 A23 / ADDRESS BUS BIT 23 – One bit of the 24-bit address

o

bus.

c

i

CS10 CHIP SELECT 10 – Output signal that selects

peripheral or memory devices at programmed

m

addresses.

e

S 13 A22 / ADDRESS BUS BIT 22 – One bit of the 24-bit address

bus.

e

l

CHIP SELECT 9 – Output signal that selects peripheral

CS9

a

or memory devices at programmed addresses.

c

s 14 A21 / ADDRESS BUS BIT 21 – One bit of the 24-bit address

e bus.

e CHIP SELECT 8 – Output signal that selects peripheral

r CS8 or memory devices at programmed addresses.

F 15 A20 / ADDRESS BUS BIT 20 – One bit of the 24-bit address bus. CS7 CHIP SELECT 7 – Output signal that selects peripheral or memory devices at programmed addresses. 16 A19 / ADDRESS BUS BIT 19 – One bit of the 24-bit address bus. CS6 CHIP SELECT 6 – Output signal that selects peripheral or memory devices at programmed addresses. 17 – 19 A18 – A16 ADDRESS BUS 18 – 16 – Three bits of the 24-bit address bus.

20 GND GROUND

M68MPB16Y3UM/D 4-7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-8. Logic Analyzer Connector J14 Pin Assignments

Pin Mnemonic Signal

1, 2 SPARE No connection

3 DSACK0 DATA AND SIZE ACKNOWLEDGE 0 – Active-low input signal that allows asynchronous data transfers and dynamic bus sizing between the MCU and external devices.

.

. 4 FASTREF FASTREF – Selection of crystal or clock input

. frequency driven into the VCO for generation of the

c MCU system clock. 1=fast reference, 0=slow reference

n

I

, 5 TSC THREE STATE CONTROL – When TSC is logic high, r this input signal forces all output drivers to a high- o impedance state.

t c 6 RESET RESET – Active-low, bi-directional signal to start a u system reset.

d

n 7 PULL-UP Not connected; pulled high through a resistor on the

o MPB.

c

i

8 SPARE No connection

m

9 – 15 IRQ1 – IRQ7 TARGET INTERRUPT REQUEST 1 – 7 - Active-low

e

input signals from the target that asynchronously

S

provides an interrupt priority level to the CPU. IRQ1

e has the lowest priority, IRQ7 has the highest.

l

a 16 – 19 SPARE No connection

c

s 20 GND GROUND

e

e

r

F

4-8 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-9. Logic Analyzer Connector J15 Pin Assignments

Pin Mnemonic Signal

1 – 3 SPARE No connection

4 – 13 GND GROUND

14 PCLK AUXILIARY TIMER CLOCK INPUT – External input clock source for the GPT.

15 PWMB PULSE WIDTH MODULATION B – Repetitive output

. signals whose high time to low time ratio can be

.

. controlled by the CPU.

c

n 16 PWMA PULSE WIDTH MODULATION A – Repetitive output

I

signals whose high time to low time ratio can be , controlled by the CPU.

r

o

t 17 PAI PULSE ACCUMULATOR INPUT – Input signal that

c increments an 8-bit counter. u 18, 19 SPARE No connection

d

n

20 GND GROUND

o

c

i

m Table 4-10. Logic Analyzer Connector J16 Pin Assignments

e

S

Pin Mnemonic Signal

e

l 1 – 4 SPARE No connection

a

5 IC1 INPUT CAPTURE 1 – Input signal that latches the

c

contents of the GPT timer counter (TCNT) into the

s

input capture register TIC1 when a selected edge

e

occurs at the pin.

e

r 6 IC2 INPUT CAPTURE 2 – Input signal that latches the

F contents of the GPT timer counter (TCNT) into the input capture register TIC2 when a selected edge occurs at the pin.

7 IC3 INPUT CAPTURE 3 – Input signal that latches the contents of the GPT timer counter (TCNT) into the input capture register TIC3 when a selected edge occurs at the pin.

8 OC1 OUTPUT COMPARE 1 – Output signal that is generated when the GPT timer counter (TCNT) and TOC1 comparator register contain the same value.

M68MPB16Y3UM/D 4-9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-10. Logic Analyzer Connector J16 Pin Assignments (continued)

Pin Mnemonic Signal

9 OC2 OUTPUT COMPARE 2 – Output signal that is generated when the GPT timer counter (TCNT) and TOC2 comparator register contain the same value.

10 OC3 OUTPUT COMPARE 3 – Output signal that is generated when the GPT timer counter (TCNT) and

.

. TOC3 comparator register contain the same value.

. c 11 OC4 OUTPUT COMPARE 4 – Output signal that is n generated when the GPT timer counter (TCNT) and

I

TOC4 comparator register contain the same value.

,

r 12 IC4 / INPUT CAPTURE 4 – Input signal that latches the

o t contents of the GPT timer counter (TCNT) into the c input capture register TIC4 when a selected edge u occurs at the pin.

d OC5 OUTPUT COMPARE 5 – Output signal that is

n

generated when the GPT timer counter (TCNT) and

o

TOC5 comparator register contain the same value.

c

i

13 – 19 SPARE No connection

m

e

20 GND GROUND

S

e

l

Table 4-11. Logic Analyzer Connector J17 Pin Assignments

a

c

Pin Mnemonic Signal

s

e

1 – 4 SPARE No connection

e r 5 VSSA A/D GROUND – A/D ground reference.

F 6 – 11 AN5 – AN0 ANALOG TO DIGITAL CONVERSION 5 -0 – Analog input lines to the MCU device.

12 VRH VOLTAGE REFERENCE HIGH – Input reference supply voltage (high) line (must set jumper on the MPB).

13 VRL VOLTAGE REFERENCE LOW – Input reference supply voltage (low) line (must set jumper on the MPB).

14, 15 AN6, AN7 ANALOG TO DIGITAL CONVERSION 6 and 7 – Analog input lines to the MCU device.

4-10 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-11. Logic Analyzer Connector J17 Pin Assignments (continued)

Pin Mnemonic Signal

16 VSSA A/D GROUND – A/D ground reference.

17 – 19 SPARE No connection

20 VSSA A/D GROUND – A/D ground reference.

Table 4-12. Logic Analyzer Connector J18 Pin Assignments

.

.

.

c Pin Mnemonic Signal

n

I 1 – 4 SPARE No connection

, r 5 PCS0 / PERIPHERAL CHIP SELECT 0 – Active-low output o SPI peripheral chip select signal.

t c SS SLAVE SELECT – Bi-directional, active-low signal that u initiates serial transmission when SPI is in slave mode; d causes mode fault in master mode.

n

o

6 MOSI MASTER-IN, SLAVE-OUT – Serial input to SPI in

c master mode; serial output from SPI in slave mode.

i

7 MISO MASTER-OUT, SLAVE-IN – Serial output from SPI in

m

master mode; serial input to SPI in slave mode.

e

S

8 SCK SPI SERIAL CLOCK – In master mode, the clock

signal from the SPI; in slave mode the clock signal to

e

l the SPI.

a

c

9 TXDA TRANSMIT DATA A – Serial data output line to serial

s communication interface A.

e

e 10 RXDA RECEIVE DATA A – Serial data input line to serial r communication interface A.

F 11 TXDB TRANSMIT DATA B– Serial data output line to serial communication interface B.

12 RXDB RECEIVE DATA B – Serial data input line to serial communication interface B.

13 – 16 TPU0 – TPU3 TIME PROCESSOR UNIT CHANNELS – TPU input/output channels.

17 – 19 SPARE No connection

20 GND GROUND

M68MPB16Y3UM/D 4-11 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MEVB SUPPORT INFORMATION

Table 4-13. Logic Analyzer Connector J19 Pin Assignments

Pin Mnemonic Signal

1 – 4 SPARE No connection

5 – 12 TPU4 – TPU11 TIME PROCESSOR UNIT CHANNELS – TPU input/output channels..

13 – 19 SPARE No connection

.

. 20 GND GROUND

.

c

n

I Table 4-14. Logic Analyzer Connector J20 Pin Assignments

,

r Pin Mnemonic Signal

o

t 1 – 4 SPARE No connection

c u 5 – 8 GND GROUND

d

n

9 PCS2 PERIPHERAL CHIP SELECT 2 – Active-low output

o SPI peripheral chip select signal.

c

i

10 PCS1 PERIPHERAL CHIP SELECT 1 – Active-low output

m SPI peripheral chip select signal.

e

11 – 13 GND GROUND

S

14 T2CLK TPU CLOCK – External input clock source to the TPU.

e

l

a 15 – 18 TPU15 – TPU12 TIME PROCESSOR UNIT CHANNELS – TPU

c input/output channels.

s

19 SPARE No connection

e

e

r 20 GND GROUND

F

4-12 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

CHAPTER 5 MAPI SUPPORT INFORMATION

5.1 INTRODUCTION

The information in this chapter is relevant when the MPB is to be installed on a target system. The figures in this chapter show the MAPI interface connector

.

. layout and pin assignments for MPB connectors P1, P2, P3, and P4.

. c The connectors required to interface to the MAPI bus are:

n

I

2 Robinson Nugent 2 X30 plugs P50L-060P-AS-TGF

,

r

o 2 Robinson Nugent 2 X40 plugs P50L-080P-AS-TGF

t

c u CL

d

n

1

o

1 1

c

i

m

2.500

e

S

C

L

e

l

a

c

1.250

s

e

e r C F L 1 CL CL CL 1.250 2.500

Figure 5-1. MAPI Interface Connector Layout

M68MPB16Y3UM/D 5-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

VRH 1 nn 2 VSSA VRL 3 nn 4 VSSA AN6 5 nn 6 VSSA AN7 7 nn 8 VSSA VSSA 9 nn 10 VSSA IC1 11 nn 12 GND IC2 13 nn 14 GND IC3 15 nn 16 GND OC1 17 nn 18 GND

.

. OC2 19 nn 20 GND

. OC3 21 nn 22 GND

c OC4 23 nn 24 GND

n

I IC4/OC5 25 nn 26 GND

, PAI 27 nn 28 GND

r PWMA 29 nn 30 GND

o t PWMB 31 nn 32 GND c PCLK 33 nn 34 GND u GND 35 nn 36 GND d GND 37 nn 38 GND

n

GND 39 nn 40 GND

o

nn GND 41 42 GND

c

i nn GND 43 44 GND

nn

GND 45 46 GND

m

nn

e GND 47 48 GND

nn

S GND 49 50 GND

GND 51 nn 52 GND

e

l GND 53 nn 54 GND

a A23 / CS10 55 nn 56 GND

c nn A22 / CS9 57 58 GND

s nn A21 / CS8 59 60 GND

e nn A20 / CS7 61 62 GND

e nn

r A19 / CS6 63 64 GND nn F FC2 / CS5 65 66 GND FC1 67 nn 68 GND FC0 / CS3 69 nn 70 GND BGACK / CSE 71 nn 72 GND BG / CSM 73 nn 74 GND BR / CS0 75 nn 76 GND CSBOOT 77 nn 78 GND +5V 79 nn 80 VPP1

Figure 5-2. MAPI Interface Connector P1 Pin Assignments

5-2 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

VSSA 1 nn 2 AN0 VSSA 3 nn 4 AN1 VSSA 5 nn 6 AN2 VSSA 7 nn 8 AN3 VSSA 9 nn 10 AN4 VSSA 11 nn 12 AN5 VSSA 13 nn 14 VSSA GND 15 nn 16 GND

. No Connect 17 nn 18 +5V

.

. GND 19 nn 20 GND c A1 21 nn 22 A2 n A3 23 nn 24 A4

I

A5 25 nn 26 A6

, r A7 27 nn 28 A8 o A9 29 nn 30 GND

t A10 31 nn 32 A11

c A12 33 nn 34 A13

u nn d A14 35 36 A15 nn

n A16 37 38 A17

o nn A18 39 40 GND

c nn No Connect 41 42 +5V

i

nn

GND 43 44 GND

m

nn

GND 45 46 PCS0/SS

e GND 47 nn 48 MOSI

S

nn

GND 49 50 MISO

nn e GND 51 52 SCK

l

GND 53 nn 54 TXDA

a

nn GND 55 56 RXDA

c

nn GND 57 58 TXDB

s

nn

e GND 59 60 RXDB

e

r

F Figure 5-3. MAPI Interface Connector P2 Pin Assignments

M68MPB16Y3UM/D 5-3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

GND 1 nn 2 TPU0 GND 3 nn 4 TPU1 GND 5 nn 6 TPU2 GND 7 nn 8 TPU3 GND 9 nn 10 TPU4 GND 11 nn 12 TPU5 GND 13 nn 14 TPU6 GND 15 nn 16 TPU7 GND 17 nn 18 TPU8

.

. GND 19 nn 20 TPU9

. GND 21 nn 22 TPU10

c GND 23 nn 24 TPU11

n

I GND 25 nn 26 TPU12

, GND 27 nn 28 TPU13

r GND 29 nn 30 TPU14

o t GND 31 nn 32 TPU15 c GND 33 nn 34 T2CLK u GND 35 nn 36 GND d GND 37 nn 38 GND

n

GND 39 nn 40 GND

o

nn GND 41 42 PCS1

c

i nn GND 43 44 PCS2

nn

GND 45 46 GND

m

nn

e GND 47 48 GND

nn

S GND 49 50 GND

GND 51 nn 52 GND

e

l GND 53 nn 54 VSTBY

a GND 55 nn 56 DSO / IPIPE0

c nn GND 57 58 DSI / IPIPE1

s nn GND 59 60 HALT

e nn GND 61 62 RESET

e nn

r GND 63 64 BERR nn F GND 65 66 BKPT / DSCLK GND 67 nn 68 TSC GND 69 nn 70 FREEZE GND 71 nn 72 GND EXTAL 73 nn 74 GND GND 75 nn 76 CLKOUT GND 77 nn 78 GND +5V 79 nn 80 +5V

Figure 5-4. MAPI Interface Connector P3 Pin Assignments

5-4 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

+5V 1 nn 2 +5V GND 3 nn 4D0 D1 5 nn 6D2 D3 7 nn 8D4 D5 9 nn 10 D6 D7 11 nn 12 GND D8 13 nn 14 D9 D10 15 nn 16 D11

. D12 17 nn 18 D13

.

. D14 19 nn 20 D15 c GND 21 nn 22 GND n A0 23 nn 24 GND

I

DSACK0 25 nn 26 GND

, r DSACK1 27 nn 28 GND o PULL-UP 29 nn 30 GND

t PULL-UP 31 nn 32 GND

c DS 33 nn 34 GND

u nn d AS 35 36 GND nn

n SIZ0 37 38 GND

o nn SIZ1 39 40 GND

c nn R/W 41 42 GND

i

nn

FASTREF 43 44 GND

m

nn

IRQ1 45 46 GND

e IRQ2 47 nn 48 GND

S

nn

IRQ3 49 50 GND

nn e IRQ4 51 52 GND

l

IRQ5 53 nn 54 GND

a

nn IRQ6 55 56 GND

c

nn IRQ7 57 58 GND

s

nn

e +5V 59 60 VPP4

e

r

F Figure 5-5. MAPI Interface Connector P4 Pin Assignments

M68MPB16Y3UM/D 5-5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MAPI SUPPORT INFORMATION

.

.

.

c

n

I

,

r

o

t

c

u

d

n

o

c

i

m

e

S

e

l

a

c

s

e

e

r

F

5-6 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

SCHEMATIC DIAGRAMS

CHAPTER 6 SCHEMATIC DIAGRAMS

6.1 INTRODUCTION

This chapter contains the M68MPB916Y3 MCU Personality Board (MPB) schematic diagrams. These schematic diagrams are for reference only and may

.

. deviate slightly from the circuits on your MPB.

.

c

n

I

,

r

o

t

c

u

d

n

o

c

i

m

e

S

e

l

a

c

s

e

e

r

F

M68MPB16Y3UM/D 6-1 For More Information On This Product, Go to: www.freescale.com 4Freesc31ale Semiconducto2r, Inc... TABLE OF CONTENTS REVISIONS

1 TITLE & REVISITION STATUS ZONE REV DESCRIPTIONDATE APPROVED 2 NOTES 3 BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS O ORIGINAL RELEASE 02/11/94 L.H. 4 MODULAR ACTIVE PROBE INTERCONNECT P1 & P3 5 MODULAR ACTIVE PROBE INTERCONNECT P2 & P4 A ADDED PULLUPS TO PCS1* & PCS2* 11/15/94 B.B. 6 MCU & CLOCK D 7 PULLUPS/PULLDOWNS/PERSONALITY ID D 8 SIGNAL CROSS REFERENCES Freescale Semiconductor,Inc.

F o

r

M

o

Cr C G e o I

n t f o o : r w m w a t w i o DWG. NO. . f n 3S957 A 63ASE90507W r e O e n s c T a h l i e s . c P o Br o m d u c t

, MOTOROLA RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. MOTOROLA DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN. AND MEMORY REV: DRAWN BY: DATE: TECHNOLOGIES GROUP 6501 WILLIAM CANNON DRIVE WEST AUSTIN, TEXAS 78735 USA L.H. 02/11/94 TITLE: A SCHEMATIC - A DESIGN ENGINEER: DATE: L.H. 02/11/94 MPB16Y3C PROJECT LEADER: DATE: SIZE GEDTTL: BOARD DWG. NO. REV: L.H. 02/11/94 A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Tue Nov 15 17:58:05 1994 SHEET 1 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

D D

NOTES: 1. UNLESS OTHERWISE SPECIFIED: ALL RESISTORS ARE IN OHMS, 5%, 1/8 WATT. ALL CAPACITORS ARE IN UF. 50V. ALL VOLTAGES ARE DC. 2. INTERRUPTED LINES CODED WITH THE SAME LETTER OR LETTER COMBINATIONS ARE ELECTRICALLY CONNECTED. Freescale Semiconductor,Inc.

3. DEVICE TYPE NUMBER IS FOR REFERENCE F ONLY. THE NUMBER VARIES WITH THE o

MANUFACTURER. r

M 4. SPECIAL SYMBOL USAGE:

o * DENOTES - ACTIVE LOW SIGNAL.

Cr <> DENOTES - VECTORED SIGNALS. C G e

5. INTERPRET DIAGRAM IN ACCORDANCE o I

n WITH AMERICAN NATIONAL STANDARDS t f o INSTITUTE SPECIFICATIONS, CURRENT o : r REVISION, WITH THE EXCEPTION OF w m LOGIC BLOCK SYMBOLOGY. w a 6. CODE FOR SHEET TO SHEET REFERENCES t w

i IS AS FOLLOWS: o DWG. NO. . f n 5 C7 < > A 63ASE90507W r e SHEET OUTPUT O e

n ZONE INPUT s

c 7. VCC LOCATIONS T a

h UNLESS OTHERWISE SPECIFIED, VCC IS APPLIED TO: l i e PIN 8 OF ALL 8-PIN ICS s .

c PIN 14 OF ALL 14-PIN ICS P o Br PIN 16 OF ALL 16-PIN ICS o m PIN 20 OF ALL 20-PIN ICS, ETC. d

u 8. GROUND LOCATIONS

c UNLESS OTHERWISE SPECIFIED, GROUND IS APPLIED TO: t PIN 4 OF ALL 8-PIN ICS , PIN 7 OF ALL 14-PIN ICS PIN 8 OF ALL 16-PIN ICS PIN 10 OF ALL 20-PIN ICS, ETC. REV:

A A NOTES

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Tue Nov 15 18:04:33 1994 SHEET 2 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

+5V AND GND DECOUPLING VDDI/VSSI GENERATION FOR VDDE OF MCU AND OSCILLATOR +5V VDDI D +5V D L52 1 2

1UH 2 2 2 2 2 2 + 1 C1 + 1 C7 + 1 C2 2 2 C3 C51 C52 C53 C57 C62 10UF 10UF 10UF C54 C55 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 25V 25V 25V 0.1UF 0.1UF 1 1 1 1 1 1 2 TANT 2 TANT L1 2 TANT 1 1 1 2 FERRITE BEAD GND GND GND GND GND GND GND VSSI

2 2 2 2 2 2 C63 C64 C66 C67 C72 C73

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Freescale Semiconductor,Inc. 1 1 1 1 1 1 ADC MODULE F o VDDA/VSSA GENERATION

r GND GND GND GND GND GND

M

o VDDI (CUT TRACE ON BOARD) VDDA

Cr C

G L3 e W2 1 2 o I 1UH 1 2

n t + 1 C4 2 f o 10UF C5 o ADC MODULE E1 : L4 1 2 25V 1 0.1UF r TANT w m VRH & VRL SELECTION 1 2 w

a FERRITE BEAD t w i

o VDDA VSSA DWG. NO. . VSSI f n 3S957 A 63ASE90507W r e O 6B4< VRH W3 e

n 1 s 2 MAPI-VRH c 4C4> ADC MODULE T 3 a h 2 l

i ANALOG SIGNAL FILTERS e C71 AN<7..0> 4C4> 5C1> s 0.1UF

. 1 c P AN<0> o Br AN<1> o m

d VSSA AN<2>

u AN<3>

c W4 AN<4> t 6B4< VRL 1 , 2 3 AN<5> 4C4> MAPI-VRL AN<6> 1 C68 AN<7> 0.1UF 2 2 2 2 2 2 2 2 2 C6 C8 C9 C10 C11 C12 C70 C69 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF

VSSA VSSA REV: VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA

A A BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Thu Nov 17 10:06:11 1994 SHEET 3 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

D D

3B4< MAPI-VRH MAPI BUS P1 MAPI BUS P3 3B4< MAPI-VRL

6B4< 3B1< AN<6> Freescale Semiconductor,Inc.

AN<7> TPU<15..0>

F 6B4< 3B1< 6C4<> 7A4< P1 P3 o

7C4< 6C1<> IC1 1 2 1 A 2 TPU<0> r I/O A GND2 GND3 I/O 3 N 4 3 N 4 TPU<1> 5 I/O GND2 6 GND3 A# I/O M 7C4< 6C1<> IC2 I/O A# GND2 5 GND3 L3 I/O 6 TPU<2> 7 L 2 8 7 O 8 TPU<3> IC3 9 I/O O GND2 10 GND3 G I/O

o 7C4< 6C1<> I/OG GND2

9 GND4 I/O 10 TPU<4> Cr 11 12 11 A 12 TPU<5> C G I/O GND1 GND4 I/O e 7C4< 6C1<> OC1 13 A 14 13 N 14 TPU<6> 15 I/O N GND1 16 15 GND4 A I/O 16 TPU<7> o I/O A GND1 VSSA GND GND4 L I/O

I OC2 17 18 17 18 TPU<8> 7C4< 6C1<> I/O L GND1 GND4 O I/O

n 19 O 20 19 G 20 TPU<9>

t I/O GND1 GND4 I/O 7C4< 6C1<> OC3 21 G 22 21 # 22 TPU<10> f o 23 I/O # GND1 24 23 GND4 4 I/O 24 TPU<11> o OC4 25 I/O 1 GND1 26 GND4 I/O : 7C4< 6C1<> I/O GND1 r 25 GND I/O 26 TPU<12> w m 7C1< 6B1<> IC4/OC5 27 I/O GND 28 27 GND I/O 28 TPU<13> 29 I/O GND 30 29 GND I/O 30 TPU<14> w PAI 31 32 31 32 TPU<15> a 7C1< 6B1< I/O GND GND GND GND I/O 33 I/O GND 34 33 GND I/O 34 T2CLK 6B4< 7B1< t w 6B1> PWMA 35 I/O GND 36 35 GND I/O 36 i 37 38 37 38 o 39 I/O GND 40 GND I/O PWMB 39 40 DWG. NO. . 6B1> I/O GND GND I/O f

n 41 42 I/O GND 41 GND I/O 42 PCS1* 6B1<> A 7A1< 63ASE90507W r 7C1< 6B1< PCLK 43 44 43 44

VSSA I/O GND GND I/O e 45 46 45 46 PCS2* 6B1<> 7A1< O 47 I/O GND 48 47 GND I/O 48 e 49 I/O GND 50 49 GND I/O 50 n I/O GND GND I/O s 51 I/O GND 52 51 GND I/O 52 53 54 53 54 VSTBY

c 6C1< T I/O GND GND VSTBY CS<10>* 55 CS10 GND 56 55 GND DSO 56 a CS<9>* 57 58 57 58 h CS<8>* 59 CS9 GND 60 59 GND DSI 60 DSO 6D1> l GND HALT i CS8 GND

e CS<7>* 61 62 61 62 s CS<6>* 63 CS7 GND 64 63 GND RESET 64

. CS6 GND GND BERR CS<5>* 65 66 65 66 DSI 6D1<> c

P CS5 GND GND BKPT CS<4>* 67 CS4 GND 68 67 GND TSC 68 o CS<3>* 69 70 69 70 Br +5V CS<2>* 71 CS3 GND 72 71 GND FREEZE 72 HALT*

o 6C4<> m CSE/2 GND +5V GND GND +5V CS<1>* 73 CSM/1 GND 74 73 EXTAL GND 74 d CS<0>* 75 76 75 76 77 CS0 GND 78 77 GND CLKOUT 78 RESET* u CSBOOT GND GND GND 6C4<> 79 VDD VPP1 80 79 VDD VDD 80 c 6D1<> CS<10..0>* RN P50L-080S-BS-TGF RN P50L-080S-BS-TGF BERR* 6C4< t , 6D1> CSBOOT* BKPT* 6D1<

GND GND GND GND TSC 6D1<

FREEZE 6D1>

CLKOUT 6C4> REV: 6A1< VPP1 MAPI-EXTAL 6A1<

A A MODULAR ACTIVE PROBE INTERCONNECT P1 & P3

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Thu Nov 17 10:06:14 1994 SHEET 4 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

D D

MAPI BUS P4 MAPI BUS P2

7D1> 6D1> A<18..0>

6D4<> D<15..0> +5V 6D4<> DSACK0* Freescale Semiconductor,Inc.

+5V +5V AN<5..0>

F 3B1< 6B4< 6D4<> DSACK1* P4 P2 o

1 2 1 2 AN<0> r 7C4< AVEC* 3 VDD VDD 4 D<0> 3 GND2 A I/O 4 AN<1> D<1> 5 GND D0 6 D<2> 5 GND2 N I/O 6 M A AN<2> D<3> 7 D1 D2 8 D<4> 7 GND2 L I/O 8 AN<3> RMC* D<5> 9 D3 D4 10 D<6> 9 GND2 O I/O 10 AN<4>

o 7C4< D5 D6 GND2 G I/O

D<7> 11 D7 GND 12 11 GND2 # I/O 12 AN<5> Cr D<8> 13 14 D<9> 13 14 C

G D8 D9 GND2 2 I/O e 6D4<> DS* D<10> 15 16 D<11> D<12> 17 D10 D11 18 D<13> 15 16 o D12 D13 GND GND

I D<14> 19 20 D<15> NC 17 18 D14 D15 VSSA VPP2 VDD

n 6D4<> AS* 21 22 19 20 t GND GND A<1> 21 GND GND 22 A<2> f o A<0> 23 24 A<3> 23 A1 A2 24 A<4> VSSA o SIZ0 25 A0 GND 26 A<5> 25 A3 A4 26 A<6> : 6D4<> DSACK0 GND A5 A6 r 27 28 A<7> 27 A7 A8 28 A<8> w DSACK1 GND m 29 AVEC GND 30 A<9> 29 A9 GND 30 6C4<> SIZ1 31 RMC GND 32 A<10> 31 A10 A11 32 A<11> w 33 34 A<12> 33 34 A<13> a DS GND A12 A13 35 AS GND 36 A<14> 35 A14 A15 36 A<15> t w 6C4> R/W* 37 SIZ0 GND 38 A<16> 37 A16 A17 38 A<17> i 39 40 A<18> 39 40 o 41 SIZ1 GND 42 41 A18 GND 42 NC SS* DWG. NO. . R/W GND VPP3 VDD 6B1<> 7B4< f

n 43 44 43 44 7D4< 6D4<> FSREF MODCLK GND GND GND A 63ASE90507W r MOSI 6B1<> 7B4< e IRQ<1>* 45 46 45 46 O I/O GND GND3 I/O IRQ<2>* 47 48 47 A 48 MISO 6B1<> 7B4< e IRQ<3>* 49 I/O GND 50 49 GND3 N I/O 50 n I/O GND GND3 I/O s IRQ<4>* 51 52 51 A 52 SCK I/O GND GND3 L I/O 6B1<> 7B4< IRQ<5>* 53 54 53 54 c O T I/O GND GND3 I/O IRQ<6>* 55 I/O GND 56 55 GND3 G I/O 56 TXDA 6B1<> 7B4< a IRQ<7>* 57 58 57 # 58 h 59 I/O GND 60 59 GND3 3 I/O 60 RXDA 6B1<> 7B1< l

i VDD VPP4 GND3 I/O e s 7A4< 6D4<> IRQ<7..1>* RN P50L-060S-BS-TGF RN P50L-060S-BS-TGF TXDB 6B1<> 7B1< . c P RXDB 6B1<> 7B1< o Br GND GND GND GND GND o m d u

c 6A1< VPP4 t , REV:

A A MODULAR ACTIVE PROBE INTERCONNECT P2 & P4

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Thu Nov 17 10:06:18 1994 SHEET 5 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

VDDI +5V U1 +5V VDDI 10 VDDE VDDE 26 40 VDDE VDDE 47 57 VDDE YAMAICHI VDDE 72 5C4<> D<15..0> 95 VDDE VDDE 108 A<18..0> 5D4< 7D1> 120 VDDE VDDE 130 7D4< 5B4<> FSREF 143 VDDE CLAM SHELL VDDE 157 7A4< 5B4<> IRQ<7..1>* CS<10..0>* 4B4< D 70 SOCKET 136 D 5C4<> DSACK0* VDDI VDDI D<0> 119 D0 /PH0 FOR THE A0 100 A<0> 5C4<> DSACK1* D<1> 118 D1 /PH1 A1 12 A<1> CSBOOT* 4B4< D<2> 117 D2 /PH2 A2 13 A<2> D<3> 116 D3 /PH3 PB0/ A3 14 A<3> DSI 4B1<> D<4> 115 D4 /PH4 MC68HC16Y3 PB1/ A4 15 A<4> D<5> 114 D5 /PH5 PB2/ A5 16 A<5> DSO 4B1< D<6> 113 D6 /PH6 PB3/ A6 17 A<6> 5C4<> DS* D<7> 112 D7 /PH7 160 QFP PB4/ A7 18 A<7> BKPT* 4B1> D<8> 111 D8 /PG0 PB5/ A8 19 A<8> 5C4<> AS* D<9> 110 D9 /PG1 PB6/ A9 20 A<9> FREEZE 4A1< D<10> 109 D10/PG2 PB7/A10 22 A<10> 5C4<> SIZ0 D<11> 106 D11/PG3 PA0/A11 23 A<11> TSC 4B1> D<12> 105 D12/PG4 SCIM INTERFACE PA1/A12 24 A<12> 5C4<> SIZ1 D<13> 104 D13/PG5 PA2/A13 25 A<13> VSTBY 4B1> D<14> 103 D14/PG6 PA3/A14 28 A<14> 5C4< R/W* D<15> 102 D15/PG7 PA4/A15 29 A<15> PA5/A16 30 A<16> 4A1< CLKOUT 88 FSREF /PF0 PA6/A17 31 A<17> IRQ <1>* 87 32 A<18> Freescale Semiconductor,Inc. 4B1> BERR* IRQ <2>* 86 IRQ1* /PF1 PA7/A18 IRQ <3>* 85 IRQ2* /PF2 123 CS<0>* F IRQ3* /PF3 BR*/ CS0* 4B1<> HALT* IRQ <4>* 84 IRQ4* /PF4 BG*/ CSM* 124 CS<1>* o IRQ <5>* 83 125 CS<2>* IRQ5* /PF5 BGACK*/ CSE* 4B1<> RESET* IRQ <6>* 82 126 CS<3>* r IRQ <7>* 81 IRQ6* /PF6 PC0/FC0/ CS3* 127 CS<4>* IRQ7* /PF7 PC1/FC1/ ---- 128 CS<5>* M 99 PC2/FC2/ CS5* 131 CS<6>* 98 DSACK0*/PE0 PC3/A19/ CS6* 132 CS<7>*

o DSACK1*/PE1 PC4/A20/ CS7*

------/--- PC5/A21/ CS8* 133 CS<8>* Cr 134 CS<9>* C

G ------/--- PC6/A22/ CS9* e 93 135 CS<10>* 92 DS* /PE4 E/A23/CS10* IC1 4C4<> 7C4< o AS* /PE5 I 91 SIZ0 /PE6 CSBOOT* 122

n 90 IC2 4C4<> 7C4< t SIZ1 /PE7 140 f o R51 89 IPIPE1/DSI 141 IC3 4C4<> 7C4< o 21 74 R/W* IPIPE0/DSO 139 : CLKOUT DSCLK/BKPT r 78 BERR* FREEZE 79 OC1 4C4<> 7C4< w m 33 77 HALT* TSC 80 7A4< 4C1<> TPU<15..0> 76 RESET* OC2 4C4<> 7C4< w 65 a VSTBY OC3 4C4<> 7C4< t w TPU<0> 43 TPUCH0 PGP0/ IC1 155 i TPU<1> 44 154 OC4 4C4<> 7C4< o TPU<2> 45 TPUCH1 G PGP1/ IC2 153 DWG. NO. . TPUCH2 P PGP2/ IC3 f

n TPU<3> 46 152 IC4/OC5 TPUCH3 T T PGP3/ OC1 4C4<> A 7C1< 63ASE90507W r TPU<4> 49 151

TPUCH4 P PGP4/ OC2 e TPU<5> 50 150 PAI 4C4> O TPU<6> 51 TPUCH5 U M PGP5/ OC3 149 e TPU<7> 52 TPUCH6 O PGP6/ OC4 148 PWMA n TPUCH7 D PGP7/IC4/OC5 4C4< 7C1< s TPU<8> 53 TPUCH8 PAI 147 TPU<9> 54 U 146 PWMB

c M 4B4< 7C1< T TPUCH9 L PWMA TPU<10> 55 TPUCH10 O PWMB 145 a TPU<11> 56 E 144 PCLK h D 4B4> TPU<12> 59 TPUCH11 U PCLK l

i TPUCH12 e TPU<13> 60 L 35 MISO 5B1<> 7B4< s TPU<14> 61 TPUCH13 E PQS0/ MISO 34

. TPUCH14 PQS1/ MOSI TPU<15> 62 Q 36 MOSI 5B1<> 7B4< c

P TPUCH15 PQS2/ SCK 4C1> T2CLK 63 T2CLK S PQS3/PCS0*/SS* 33 o 97 SCK

r M 5B1<> 7B4< BVDDA PQS4/ PCS1* 96 o m PQS5/ PCS2* PMC4/RXDB 42 SS* 5B1<> 7B4< d 9 M 39 VRH 1 VDDA C PMC5/TXDB 38 PCS1*

u 3B4> 4B1<> 7A1< 160 VRH A C PMC6/RXDA 37 VRL D I PMC7/TXDA c AN<0> 7 PCS2* 4B1<> 7A1< 3B4> VRL AN<1> 6 AN0/PADA0 C 138 t AN<2> 5 AN1/PADA1 (VPP ON 916Y3) N/C 64 RXDB 5B1<> 7B1< , AN<3> 4 AN2/PADA2 M (VPP ON 916Y3) N/C AN3/PADA3 O AN<4> 3 AN4/PADA4 XTAL 66 NC TXDB 5B1<> 7B1< AN<5> 2 D 68 2 2 AN<6> 159 AN5/PADA5 U EXTAL C58 C59 RXDA 5B1<> 7B1< AN<7> 158 AN6/PADA6 L 0.1UF 0.1UF 8 AN7/PADA7 E 1 1 TXDA 5B1<> 7B4< 5C1> 4C4> AN<7..0> VSSA 156 VSSE 142 VPP1 4A4> VSSE 129 VSSA VSSE 121 VPP4 5B4> VDDSYN 67 VSSE 107 GND GND VDDI 71 MODCLK/VDDSYN VSSE 94 XFC VSSE REV: 1 69 73 MAPI-EXTAL 4A1> VSSSYN VSSE 58 W5 L51 C60 VSSE 1 1000PF 1 21 VSSI VSSE 48 21 2 C56 75 41 W1 Y1 2 101 VSSI VSSE 27 3 1UH 2100PF VSSI VSSE 3 2 137 VSSI VSSE 11 MCUEXTAL 2 8 OUT14 + 1 C65 1 1 XTALOSC 14 PIN DIP SOCKET FOR 1UF C61 R52 11 OUT8 25V 0.1UF 20K SMT-SO 8 OR 14 PIN CANS / DIPS. 2 TANT 2 1 A XFC A L2 GND MCU & CLOCK 21 VSSSYN FERRITE BEAD SIZE GEDTTL: BOARD DWG. NO. REV: VSSI VSSI A GEDABV: MPB16Y3C 63ASE90507W A NOTE: 1) PLACE THE CAP BETWEEN VDDSYN & XFC AS CLOSE TO MCU PINS AS POSSIBLE. LAST_MODIFIED=Thu Nov 17 10:06:22 1994 SHEET 6 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

MCU PERSONALITY CODE: MC68HC16Y1=108HEX & MC68HC916Y1=109HEX (USING A<10..1>)

RN4 A<18..0> 5D4< 6D1> 220K MC68HC916Y1 NC 6 16 R53 +5V NC 7 5 NC W6 220K NC 8 12 A<2> 21 NC 9 4 A<3> A<1> 1 NC 10 13 2 D NC 11 3 A<5> 3 D 1 14 A<6> 15 2 A<7> MC68HC16Y1

A<8> A<10> R4 220K A<4> 21 +5V R5 220K R3 GND A<9> 21 220K 5B4<> FSREF 12 6D4<> R1 220K 5C4<> AVEC* 1 2

R2 Freescale Semiconductor,Inc. 220K RMC* 1 2

F 5C4<> o

4C4<> IC1 r 6C1<>

M 4C4<> IC2 RN2 +5V

o 6C1<> 1M

IC4/OC5 4C4<> 6B1<> Cr 4C4<> IC3 9 16 C G e 6C1<> 10 6 NC 11 7 NC PCLK 4B4> o OC1 12 5 I 4C4<>

n 6C1<> 13 1 t 14 2 PWMB 6B1> f o 4C4<> OC2 15 3 o NC 8 4 : 6C1<> r PWMA 6B1> w m 4C4<> OC3 6C1<> w PAI

a 4C4> 4C4<> OC4 t w 6C1<> i o DWG. NO. . f

n SS* 5B1<> +5V A 63ASE90507W r 6B1<> RN5 e O 5B1<> MOSI 1M e 1 16

n 6B1<> s 2 5 NC

MISO 3 6 NC

c 5B1<> T 6B1<> 4 7 NC RXDA 5B1<> 6B1<> a 15 8 NC h 5B1<> SCK NC 11 14 l i e 6B1<> TPU<0> 9 13 TXDB 5B1<> 6B1<> s TPU<1> 10 12 . 5B1<> TXDA c P 6B1<> RXDB 5B1<> 6B1<> o Br o m RN3 +5V d 1M u TPU<2> 8 16

c TPU<3> 7 9 T2CLK 4C1> TPU<4> 6 15 TPU<10> t TPU<5> 5 14 TPU<11> , TPU<6> 4 13 TPU<12> TPU<7> 3 12 TPU<13> TPU<8> 2 11 TPU<14> TPU<9> 1 10 TPU<15>

4C1<> TPU<15..0> 6C4<>

5B4<> IRQ<7..1>* RN1 +5V REV: 6D4<> 1M PCS1* 4B1<> 6B1<> IRQ<1>* 4 16 IRQ<2>* 13 9 IRQ<3>* 3 8 PCS2* 4B1<> 6B1<> IRQ<4>* 14 5 NC IRQ<5>* 2 6 NC IRQ<6>* 15 7 NC IRQ<7>* 1 10 NC A NC 12 11 NC A PULL-UPS / PULL-DOWNS / PERSONALITY ID

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Thu Nov 17 10:06:24 1994 SHEET 7 OF 8 4312

4Freesc31ale Semiconducto2r, Inc...

*** Signal Cross-Reference *** TXDB 5B1<> 6B1<> 7B1< --- for the entire design -- VPP1 4A4> 6A1< D VPP4 5B4> 6A1< D A <18..0> 5D4< 6D1> 7D1> VRH 3B4> 6B4< AN <7..0> 3B1< 4C4> 5C1> 6B4< VRL 3B4> 6B4< AS * 5C4<> 6D4<> VSTBY 4B1> 6C1< AVEC * 5C4<> 7C4< BERR * 4B1> 6C4< BKPT * 4B1> 6D1< CLKOUT 4A1< 6C4> CS <10..0> * 4B4< 6D1<> CSBOOT * 4B4< 6D1> D <15..0> 5C4<> 6D4<> DS * 5C4<> 6D4<> DSACK0 * 5C4<> 6D4<> Freescale Semiconductor,Inc.

DSACK1 * 5C4<> 6D4<>

F DSI 4B1<> 6D1<> o DSO 4B1< 6D1>

r

FREEZE 4A1< 6D1> M FSREF 5B4<> 6D4<> 7D4<

o HALT * 4B1<> 6C4<>

Cr C

G IC1 4C4<> 6C1<> 7C4< e IC2 4C4<> 6C1<> 7C4< o I IC3 4C4<> 6C1<> 7C4<

n t

f IC4/OC5 4C4<> 6B1<> 7C1< o o IRQ <7..1> * 5B4<> 6D4<> 7A4< : r

w MAPI-EXTAL 4A1> 6A1< m MAPI-VRH 3B4< 4C4> w a MAPI-VRL 3B4< 4C4> t w

i MISO 5B1<> 6B1<> 7B4< o DWG. NO. . MOSI 5B1<> 6B1<> 7B4< f n 3S957 A 63ASE90507W r OC1 4C4<> 6C1<> 7C4< e O OC2 4C4<> 6C1<> 7C4< e

n OC3 4C4<> 6C1<> 7C4< s

c OC4 4C4<> 6C1<> 7C4< T

a PAI 4C4> 6B1< 7C1< h l

i PCLK 4B4> 6B1< 7C1< e s PCS1 * 4B1<> 6B1<> 7A1< . c P PCS2 * 4B1<> 6B1<> 7A1< o Br PWMA 4C4< 6B1> 7C1< o m PWMB 4B4< 6B1> 7C1< d R/W * 5C4< 6C4> u RESET * 4B1<> 6C4<> c

t RMC * 5C4<> 7C4<

, RXDA 5B1<> 6B1<> 7B1< RXDB 5B1<> 6B1<> 7B1< SCK 5B1<> 6B1<> 7B4< SIZ0 5C4<> 6D4<> SIZ1 5C4<> 6C4<> SS * 5B1<> 6B1<> 7B4< T2CLK 4C1> 6B4< 7B1<

TPU <15..0> 4C1<> 6C4<> 7A4< REV: TSC 4B1> 6D1< TXDA 5B1<> 6B1<> 7B4<

A A SIGNAL CROSS REFERENCES

SIZE GEDTTL: BOARD DWG. NO. REV: A GEDABV: MPB16Y3C 63ASE90507W A

LAST_MODIFIED=Tue Nov 15 18:03:45 1994 SHEET 8 OF 8 4312

Freescale Semiconductor, Inc.

SCHEMATIC DIAGRAMS

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6-10 M68MPB16Y3UM/D For More Information On This Product, Go to: www.freescale.com