Wireless Information Transmission System Lab.
Introduction to System IC and Design Flow
Hung-Chih Chiang
Institute of Communications Engineering National Sun Yat-sen University Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
2 IC Industry Co-Operation Model
IDM
Sales Channel / Service Provider
System House (Brand/OEM/ODM)
Design House (Fabless) Siemens Motorola Toshiba IP/Design Service EDA Tool Company Provider
Photo Mask/Foundry Service
Packaging Service
Chip Level Debugging IC Testing Service and Reliability Testing Service
3 Taiwan IC Industry and Supporting System
Equipment Capital & HR
EDA Foundry Design Assembly Testing Supporting IDM Services
Transportation Custom Science Park Mask Wafer Chemicals Lead Frame etc. Materials
Source: ITRI, DigiTimes
4 Role of a Design House in an IC Supply Chain
Product Development Photo Mask In-house or sub-contract •Market Survey •Product Planning •Chip Design
Design House Final Test, QC
Chip Manufacturing Packaging
Wafer Testing Marketing and Sales
In-house or sub-contract Design House
Source： Weltrend Semiconductor, Inc
5 IC其實是高科技印刷出版產業
Product Mask Wafer Final Sales & Package R&D &Wafer CP Test Test Logistics
IC設計公司 晶圓代工廠 封測公司 封測公司 封測公司 IC設計公司
Turn-key Service
作家/出版商 印刷廠 印刷廠 印刷廠 印刷廠 出版商
製版 作品撰稿 品管檢查 裝訂 成品檢視 配銷 &印刷
Source： IC 設計業與半導體供應鍊 By Jeff Tsai 6 Chip Production Flow
Spec. Market/Competitors/IP/Spec.
EDA Tools ASIC Design HW/SW Design and Verification
Wafer Test Manufacture Mask (Chip Probing) and Modification EDA Tools Package
Production Run Pilot Run
Chip No good Chip Final Test Chip Verification Debugging Debugging Tools Ok
Reliability Test Chip No good Ready Ok
7 Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
8 SoC Concept
Analog Memory PCB
ASIC CPU Chip
System on a Board
Analog IP Memory IP Chip IP I P CPU System on a Chip
9 SoC Technology System-on-a-chip (SoC) technology is the packaging of all the necessary electronic circuits and parts for a "system" (such as a cell phone or digital camera) on a single integrated circuit.
10 Soc Advantages Minimize System Cost PCB, passive components Assembling Testing Compact System Size Board layout vs. chip layout Reduce System Power Consumption I/O, passive components, core voltage and current levels Increase System Performance Interconnecting delay
11 Years 2002 – 2008 Worldwide Communication SoC Market Values
Unit: Million U.S. Dollars
Product 2002 2003 2004 2005 2006 2007 2008
Digital Cellular 7,480 9,463 12,560 15,210 15,855 17,202 19,013
LAN Wireless 138 333 492 662 777 938 1,134
Mobile Infrastructure 325 344 418 537 511 479 481
Other Mobile Comms. 378 520 673 859 1,077 1,215 1,440
LAN 140 184 248 316 348 392 446
Premises and CO Line Card 167 161 188 201 199 204 219
Broadband Remote Access 918 1,313 1,617 1,793 1,717 1,837 1,978
Public Infrastructure 304 360 481 607 667 810 934
Other Wired Comms. 428 568 811 1,128 1,175 1,365 1,515
Total Communications 10,278 13,246 17,488 21,313 22,326 24,442 27,160 Source: Dataquest (2004/06) 12 Example1: Siemens C35i Phone
13 1. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP. 2. 32.768kHz crystal 3. NIY 14 4. Bottom connector 15 12 5. FLASH 6. Power supply IC 11 16 7. VCO 8. Epcoc B4846; SAW filter, 225.0MHz 17 10 9. PCB pads to Battery 18 9 10. 13MHz crystal 8 11. Tx VCO 19 12. Hitachi PF08112B; Power amplifier 20 7 13. External antenna connetor with switch. 14. Diplex filter 6 21 15. NIY 1 16. Epcos B4127 SAW filter 942.5MHz 17. NIY 2 18. PCB pads to SIM card holder 19. Synthesizer (?) 3 5 20. Hitachi HD155124F– Bright II; GSM Transceiver Circuit 21. Infineon PMB2906: Analog interface IC (E-GAIM). Interfaces analogue signals (I/Q, voiceband, PA-control, charging control signals) to the digital domain 4
13 Example2: Philips DAB Receiver
Data
IF A/D MPEG MPEG Audio Audio Tuner OFDM Demodulation Channel Decoding Decoder DAC AGC L R
Micro- controller
Integration vs. Diversity & Process
14 System Integration Trend- Cfone
~2000 2001-2002 2003-2004 2005
Transistors Diodes Synthesizer IC PA PA PA Frequency Converter LNA RF/IF RF Switch RF RF VCOs Filters PA … Single Chip CPU/DSP Audio Processor Digital Baseband Memories Power Management Baseband Analog Baseband Baseband A/D Power management D/A … Memories Flash Memories Flash Memories
Resistors Inductors Passive Capacitors Passive components Passive components Passive components …
Source: 工研院經資中心ITIS計畫(2002/10) 15 TI- DRP GSM cellular phone solution
RF Codec Digital Power Amplifier ADC and DAC Baseband
Frequency Transceiver Memory Synthesizer
Power Management
Digital and RF Power Amplifier SOC ½ Board size ½Power ½ Silicon Area Power Management Memory
16 Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
17 Affecting Factors for System Integration Process Migration Faster digital to implement RF Density & yield improving
IP Resources Reusable IP Cooperate or merge
EDA Tools Support System integration tools System verification tools
18 Histories of Key IC Components
Logic 1st Bipolar Transistor Belllab in 1956 st integrated1 memory-cell NEC in 1966 1st Bipolar ECL IBM in 1957 Memoryst 1Kb 13T MOS DRAM Intel/Honeywell in 1970 1st IC Fairchild in 1960 st 2Kb 1EPROM Intel in 1971 1st TTL Fairchild in 1962 st 1T DRAM1 Siemens in 1972 1st CM OS Fairchild in 1963 st mux-addressed1 16Kb DRAM Mostek in 1977 1st 4-bit NMOS uP Intel in 1974 st 4Kb 1pseudo-SRAM Intel in 1979 1st 32-bit CMOS uP Belllab in 1981 st 16Kb1 EEPROM Intel in 1980 1st 32-bit RISC uP Standford+Berkeley in 1984 st 256Kb1 Flash Toshiba in 1985 1st 100Mhz CMOS uP Intel in 1991 st 256b1 FRAM Ramtron in 1988 1st 64-bit CMOS uP-200Mhz DEC in 1992 st multi-level1 32Mb Flash Intel in 1995 1st st 1 out-of-orde r-execution uP Intel in 1995 DSP sampled-data1 band-pass Filter Belllab in 1960 st 32-bit 1Ghz uP-0.18u Intel in 2000 st analog1 shift-register Philips in 1972 Analog 1st PLL IC Signetics in 1969 st switched-capacitor1 Filte r Berkeley in 1978 1st MOS voice-encoder Berkeley in 1976 st DSP1 Belllab in 1980 1st switch-capacitor Filter Berkeley in 1977 st floating-point1 32-bit DSP Bellab in 1985 1st echo-canceller Belllab in 1983 st Vide1 o DSP NEC in 1987 1st 1-chip Pager Philips in 1991 st CM OS1 re ad-c ha nne l Hitachi in 1993 1st GSM Transceiver Belllab in 1995 st low-power1 16-bit DSP Matsushida in 1993
st 1 1024-QAM1 cable-modem DSP Broadcom in 1998 st 5Ghz OFDM-BB 80Mb/s Imec in 2000 Source: ISSCC 50th years 19 Moore’s Law and Extensions
Source: Intel Gordon Moore (ISSCC2003): - Moore’s Law will extend another 10-15 years. - But no exponential is forever, so delayed Moore’s Law (valid in the past 50 years) will be more realistic for the next 10-15 years. 20 Technology Migration TSMC Logic Technology Roadmap
CL018LP CLN90LP CLN90LP Low Power CL015LP CLN65LP 1.2V/2.5V 1.2V/3.3V CL013LP
CLN90GT CL013LV(LK) CL018LV 1.2V/2.5V High Speed CL015LV CLN011LV CLN65HS CL013LV 1.2V/1.8, CLN90GT 2.5,3.3V 1.2V/1.8V
1.2~0.15um CLN90G General 1.0V/2.5V CLN65G Purpose CL013G 1.2V/2.5,3.3V CLN90G 1.0V/1.8,3.3V
Available Technologies 2004 2005 2006 Source: TSMC Technology Roadmap (Fall 2004)
21 IP Resources
IP Libraries (in-company) IP Providers Faraday, Global UniChip, PGC, FameG, … Artisan, ARM, MIPS, Synopsys, Mentor, … Cooperation Partners/Merge companies Free IP (*Usually need some efforts to verify functions and get them work) OpenCores: http://www.opencores.org FPGA CPU News: http://www.fpgacpu.org http://www.mindspring.com/~tcoonan/newpic.html
22 EDA Tool Markets
6,000 PCB Design 單 位 5,000 IC CAD ： CAE/Misc. 百 CAE/Gate Level 萬 4,000 美 CAE/RTL 元 CAE/ESL 3,000
2,000
1,000
0 2000 2001 2002 2003(e) 2004(e) 2005(f) 2006(f) 2007(f)
資料來源：工研院IEK (2004/04)
23 SoC Challenges IP Resource IP library, IP provider, IP quality, IP cost Chip Integration IP cores with different manufacturer processes (logic, memory, analog, high V, …) Chip Design Verification EDA Tools that support system verification at all or mixed design phases Chip Testing Soft/firm/hard cores (logic, memory, analog, …) with or without test circuits, or with different testing strategies
24 Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
25 System-in-a-Package (SiP)
SiP concept
Analog Memory
ASIC CPU
Packaged Chip
die
substrate
26 Benefits of SiP SiP benefits: Reduced developing schedule Reduced developing cost Possible mounting of different technologies Increased yields enabled by smaller chip size
27 SiP Examples
Examples of practical SiP
Stack Double side Side by Side
28 Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
29 Typical System IC Architecture
30 Traditional Sequential ASIC Design Flow
Specification Specification Define
System Modeling Algorithm and Architecture Design
Circuit Design & Functional Verification HDL/Schematic Circuit Design and function-simulation
Logical Synthesis & Timing Verification Logic Synthesis and Pre-simulation
P & R & Physical Verification Physical Design and Post-simulation
Prototype Build & Test Prototype
31 Parallel System IC Design Flow
System Design and Verification
Physical Timing Hardware Software
Hardware Software Physical Specification: Timing Specification: Specification Specification area, power, clock tree IO timing, clock design frequency Algorithm Application prototype development & macro development decomposition Preliminary Block timing AP prototype Block selection Time floorplan specification / design testing
Updated Block synthesis & Block verification Application floorplans placement development Updated Top-level HDL Application floorplans testing Trial placement Top-level synthesis Top-level Application verification testing
Placement and Route -> Tapeout
32 Specifications Specification Requirements: Hardware Functionality External interfaces to other hardware Software interface (register definitions) Timing Performance Area and power constraints Software Functionality Timing Performance Hardware Interface Software structure, kernel 33 Specification
Two Useful Specification Techniques: Formal specifications: The desired characteristics of a design are defined independently of any implementation. Once a formal specification is generated, format methods such as property checking can be used to prove that a specific implementation meets the specification. Executable specifications: An executable specification is typically an abstract model for the hardware/software been specified written in in C, C++, SystemC, HVL, Verilog, or VHDL.
34 System Level Design Processes
CREATE system specification
DEVELOP system model
DETERMINE DEVELOP SPECIFY & DEVELOP HW/SW partition HW architecture model Prototype SW REFINE & TEST architecture model (HW/SW co-simulation)
SPECIFY SPECIFY HW block SW
Block1 spec.
Block2 spec.
35 Features of System Level Design Tools (Synopsys System Studio )
Extensive support for SystemC, the emerging architecture-level modeling language. Enables complete end-to-end system simulation of the SoC in realistic virtual environments. Find and correct system-level bugs when design costs are low, by monitoring and analysis features. Easy-to-use, unified development environment with both graphical and language abstractions that capture the entire system in a hierarchical fashion. Enables designers to visualize their designs in graphical schematic and symbol views, source code views, interface views and header views. Quickly close on complex architectures that can be used as reference models in the ensuing RTL design and verification flow. Enables the development of embedded software through the inclusion of cycle- accurate processor models.
36 System Level Design Stages Function Design Creating and verifying a functional model of the application
Application-driven architectural design Creating a high-level description of the platform Mapping the functional application on the platform Verifying the resulting architecture model Finding the optimal platform
Platform-oriented architecture design Creating a low-level description of the platform Fine-tuning the hardware architecture
37 System Level Design Abstraction Levels
Abstraction Granularity of models Simulation Architecture Performance level technology exploration analysis
Message Generic HW components 1000x speed Application-level Platform-level (HW characterizes by external Host-based simulator Very flexible component = black box) properties (universal attributes) (C/C++ or systemC) Prospective(a priori)
Transaction Transactional models of HW 100x speed Platform-level Component-level components Transaction level Less flexible Confirmative (a simulator (SystemC) posteriori)
Register Cycle accurate models of HW 1x speed Physical level Detailed Transfer components RTL simulator + ISS Almost not flexible Or FPGA-based prototyping
38 Design Flow for Increased Chip Complexity
Front End Back End
RTL Logical Place & Design Synthesis Route
RTL Netlist Sign off
RTL Synthesis & Synthesis,,Place & Prototyping Route
RTL Sign off
39 Traditional Front-end Design Flow
Front-End IC Design Flow
Design Specification
RTL Design and Simulation RTL Verilog Library File Code .vg or .VG Logic Synthsis Constraint File
Static Timing Anaysis / Design Rules Check Pre_sim SDF File Front-End Change_Names / Write Timing (SDF) Pre_sim Verilog Gate-level Netlist Code .vg or .VG Pre-layout Pre_sim EDIF Gate-level Simulation Netlist GTL Verilog Code .vg or .VG Floorplan, 1st Sign-Off Placement and Route
40 RTL Simulation Tools
Verilog-XL (Cadence) : a standard sign off simulator. NC-Verilog (Cadence) : a compiled simulator, works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. NC VHDL (Cadence) : VHDL simulator. NC SIM (Cadence) : for Verilog and VHDL co-simulation. VCS (Synopsis) : a compiled simulator like NC-Verilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools. Scirocco (Synopsis) : VHDL simulator. Finsim (Fintronic) : 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. Modelsim (Mentor): popular and cheap simulator, has got good debugging capabilities, a nice GUI and can deal with Verilog and VHDL co-simulation. This simulator can be used for block level design and verification. But sign-off should not be done with this simulator. Smash (Dolphin) : mixed signal, Verilog, VHDl simulator
41 Debugging/Testbench/Rule check Tools
Verdi/Debussy (SprintSoft) : Waveform display/probe. RTL/gate-level schematic generation. Finite State Machine analysis. Source code tracing, … Modelsim (Model Technology): Waveform display/compare. Code coverage statistics. Data flow tracing. Memory window, … VERA (Synopsys): Enables scalable and re-useable testbenches with OpenVera. LEDA (Synopsys): Design rule and coding style check.
42 Synthesis Tools
Design Complier (Synopsys) : the most popular logic synthesizer, bottom-up approach.
Silicon Ensemble PKS/Ambit (Cadence): a fast logic synthesizer, top-down approach.
Synplify ASIC (Synplicity): A new ASIC synthesis tool.
CoCentric SystemC Compiler (Synopsys) : A SystemC to RTL compiler.
43 Synthesis Methodology Compile Strategies Bottom-up – Synopsys Design Complier Traditional method used in building up hierarchy Each module is individually synthesized Uses manual time budgets or a default budget May not produce optimal design Prone to error in manually specified time budgets
Hierarchical (Top-down) – Cadence Ambit Build hierarchical design objects with constraints applied at the top-most level Entire design hierarchy is optimized together Only top level time budgets are required Requires fewer files and produces more optimal design than with bottom-up approach
44 Bottom-Up synthesis Approach
Always specify at least a default time budget! Time budgets are easiest with registered outputs
(Ambit) set_input_delay 2 –clock clk [find –port –input *] set_external_delay 2 –clock clk [find –port –output *]
DQ DQ DQ CK CK CK
D Q DQ CK CK
Block1 Block2
45 Hierarchical Synthesis Approach
Hierarchical synthesis avoids inter-module time budgeting An entire design hierarchy is optimized together Sub-designs are optimized in full context of top of hierarchy Only top level time budgets are required (Ambit) do_xform_optimize_slack -time_budget do_optimize -time_budget
Top
DQ
CK
DQ CK DQ
CK Buttom1 Buttom2
46 SoC Synthesis Recommend a bottom-up approach. Each IP/macro should have its own synthesis script to ensure the right internal timing.
Chip-level Synthesis Consist only connecting the macros and resizing the output drive buffers.
47 Whole Chip Partitioning
The top-levels of design hierarchy should be interconnect only
I/O PAD High Speed IO
Test Modules Clock Core Generation/ DSP PLL
Core Core
RAM Embeded CPU External Core Memory Core Controller
48 Layout Design Flow Overview
Hierarchical Multi-million gate APR and gate level floorplan.
Timing Driven/Power Driven/CTS (Clock Tree Synthesis) APR.
Signal integrity (antenna/cross talk/voltage drop/electron-migration) violation analysis and removal.
SOC integration.
LVS/DRC/ERC physical verification.
Scan chain re-ordering service
Advanced 3D RC extraction (Gate Level and Transistor Level)
SDF generate and skew report
ECO/LVL
49 Clock Tree Insertion
• Small buffer -> big buffer
CLK Source
Layer 1 buffer
Layer 2 buffer
FF FF FF FF FF FF FF FF FF
50 Traditional Cell-Base Back-End Design Flow
Cell-Base Back-End IC Design Flow
Pre-layout Gate-level simulation GTL Verilog Code .vg or .VG Cell Library Tech File Floorplan Library Mapping File Placement and Route Netlist File
Post-layout Timing Analysis/Design Rules Check Back-End Physical Verification LVS
APR SDF Out
51 Traditional Cell-Base Back-End Design Flow
Post APR Not O.K Gate-level O.K Simulation No (Avanti Flow) Logic Synthesis Optimization Milkyway2Star ? Load SDF and Netlist Files Yes Layer GRD APR ECO Milkyway2Star GDS II Out Mapping File File APR SDF Out SDF Out DRC/ERC/ Run Set File LVS
Yes SDF Out ? Res TCAD File Post Layout O.K No GRD File Gate-level simulation Skip Cell File Star-RC Tech File Not O.K 2nd Sign-Off Runset File Logic Synthesis Optimization Star-DC Tech File Load SDF and Netlist Files Pio File
APR ECO
APR SDF Out Tape Out GDS II File
52 APR/ Layout Editor Tools
Silicon Ensemble (Cadence) : APR: good for interface with Cadence synthesizer. SoC Encounter (Cadence) : RTL to GDSII. Astro/Apollo (Synopsis): APR: the most popular APR tool. Laker (SprintSoft): Layout Editor: on-line rule driven & point to point routing Virtuoso (Cadence): Layout Editor Enterprise (Synopsys): Layout Editor Tanner (Mentor Graphics): Layout Editor
53 Layout Verification/Power & Timing Analysis Tools Herculus (Synopsys) : Hierarchical layout verification, fast. Dracula (Cadence): Flattened layout verification, slow. Calibre DRC/ERC/LVS (Mentor Graphics): Hierarchical layout verification, fast. PowerMill (Synopsys): Power management and diagnostic. TimeMill (Synopsys): Dynamic timing analysis and verification.
54 RC Extraction/ Transistor Level Verification Tools
Hyper Extract (Cadence) : RC extraction
Star-RC/Star-RCXT (Synopsys) : A popular RC extraction tool
Calibre PEX (Mentor Graphic) : RC extraction
HSpice (Synopsys): Transistor level verification: accurate but slow.
Star-SimXT/Star-Sim(Synopsys): Transistor level verification: fast but not as accurate as HSpice.
P-Spice: Transistor level verification: for PC users.
NanoSim: Mixed-signal verification for multi-million transistor Soc’s.
55 Circuit Simulation Conditions Operation Temperature Low (-55°C~0°C) Typical (25°C) High(80°C~120°C)
Spice Model FF/TT/SS/FS/SF
56 Electronic System Level (ESL) Tools Purpose: System-level design HW/SW co-design Architecture exploration Virtual prototyping Co-simulation/co-verification
Requirements: Mixed level, mixed-language, mixed-signal simulation and debugging Abundant IP libraries and models Integrated developing environment
57 ESL Tools System Studio (Synopsys):
Incisive Function Verification Platform (Cadence):
SystemVision(Mentor Graphics):
58 System-on-a-Programmable-Chip (SoPC) SoPC - FPGA with the following features Embedded processor core On-chip peripherals and memory Millions of gates in FPGA logic cells System level tools provided
SoPC advantages over SoC Reconfigurable Fast prototyping Save NRE charges
59 SoPC Solution
FPGA Model Virtex-II Pro、Virtex-4 FX Stratix II、APEX 20KE
Micro-processor PowerPC 405/ CoreConnect ARM 922T/ /Bus system AMBA
Micro-controller MicroBlaze (32 bits) NIOS II (32 bits) PicoBlaze (8 bits) NIOS (32/16 bits)
Other IP Memory、Peripherals、… Memory、Peripherals、…
Integrated EDK SoPC Builder Development Tools SoPC solutions from main FPGA providers
60 Outline
IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues
61 Chip Failure Analysis Tools FIB (Focused Iron Beam) Laser EMMI (EMission MIcroscope) Probe Station E-Beam X-Ray, SAM (Scanning Acoustic Microscope)
62 FIB Flow
Ok Ok Verify Verify Trace Layout De-cap IC Execute FIB De-capped Chip FIB Chip Done
No No good good
Fail
z Good for re-wiring digital logics.
z May not work well for analog circuits due to contact and wire resistance.
63 De-cap
64 FIB Example:
Cut and line operation May need to use dummy cells to modify logic circuits Increase or decrease the number of serially connected resistors to adjust analog parameters
65 EMMI Example:
Leakage
66 E-Beam Example:
67 X-Ray Example:
Wire bond …..
68 Reliability Testing (1)
可靠性驗證項目 參考測試條件 參考測試標準 靜電放電 人體模型(Human Body Model): MIL-STD-883F (ElectroStatic -2k/4k/8kV M3015.7 and JESD22- Discharge，ESD) 機器模型(Machine Model): A114C.01 -100/200/400V JESD22-A115A 元件充電模型(Charged-Device JESD22-C101 Model): -200/500/1000V
閂鎖(Latch up) Max. Vsupply，IT up to ±200mA JESD78 and AEC Q100-004-Rev-C 工作壽命試驗 Max. Supply Voltage， MIL-STD-883F (Operation Life TA=125℃ M1005.8 Test) Test Time: 168/500/1000Hours 低溫工作壽命試驗 Tjs=-20℃ MIL-STD-883E M1005 (Low Temperature Test Time: 168/500/1000Hours and IEC68-2-1 test A Operation Life Test) 69 Reliability Testing (2)
可靠性驗證項目 參考測試條件 參考測試標準
溫溼度偏壓壽命試驗 Max. Vsupply，TA=85℃，85%RH JESD22-A101B (Temperature Humidity Test Time: 500/1000Hours Bias Life) 高加速溫濕度試驗 Tjs=130℃，85%RH， JESD22-A110B (Highly-accelerated Test Time: 72Hours Temperature and Humidity Stress Test) 壓力鍋試驗(Pressure 121℃，100%RH，2ATM， JESD22-A102C Cooker Test) Test Time: 168Hours 熱衝擊(Thermal Shock) Liquid-to-Liquid，-65℃~150℃， MIL-STD-883F >5 Minutes Dwell Time，200Cycles M1011.9 JESD22-A106B
70 Reliability Testing (3)
可靠性驗證項目 參考測試條件 參考測試標準 溫度循環試驗 Air-to-Air，-65℃~150℃， MIL-STD-883F (Temperature Cycle Test) >10 Minutes Dwell Time， M1010.8 200Cycles JESD22-A104C 高溫儲存試驗(High Tjs=150℃， JESD22-A103C Temperature Storage Test) Test Time: 1000Hours 低溫儲存測試(Low TA=-65℃， JESD22-A119 Temperature Storage Test) Test Time: 168/500/1000Hours 溫溼保存條件 TCT -40℃~60℃，5 cycles， JESD22-A113D (Precondition) 烘烤125℃/24Hours， 30℃/60%RH/192Hours， IR Reflow 3 cycles 焊接性(Solderability) Steam 1/4/8/16 Hours， MIL-STD-883E Dry Bake 150℃，16Hours， M2003.7 245±5℃，5±0.5秒 JESD22-B102D
71