Introduction to System IC and Design Flow Hung-Chih Chiang
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Co-Simulation Between Cλash and Traditional Hdls
MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator. -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
Formal Hardware Specification Languages for Protocol Compliance Verification
Formal Hardware Specification Languages for Protocol Compliance Verification ANNETTE BUNKER and GANESH GOPALAKRISHNAN University of Utah and SALLY A. MCKEE Cornell University The advent of the system-on-chip and intellectual property hardware design paradigms makes pro- tocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally in- tended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the devel- opment of the language, an evaluation of the language’s utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered. Categories and Subject Descriptors: B.4.3 [Input/Output and Data Communications]: Inter- connections (Subsystems)—Interfaces; B.4.5 [Input/Output and Data Communications]: Reli- ability, Testing, and Fault-Tolerance—Hardware reliability; B.7.2 [Integrated Circuits]: Design aids—Verification; C.2.2 [Computer-Communication Networks]: Network Protocols—Protocol verification; D.3.3 [Programming Languages]: Language Constructs and Features—Data types -
Using Modelsim to Simulate Logic Circuits in Verilog Designs
Using ModelSim to Simulate Logic Circuits in Verilog Designs For Quartus Prime 16.0 1 Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show how to perform functional and timing simulations of logic circuits implemented by using Quartus Prime CAD software. The reader is expected to have the basic knowledge of the Verilog hardware description language, and the Altera Quartus® Prime CAD software. Contents: • Introduction to simulation • What is ModelSim? • Functional simulation using ModelSim • Timing simulation using ModelSim Altera Corporation - University Program 1 May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 2 Background Designers of digital systems are inevitably faced with the task of testing their designs. Each design can be composed of many modules, each of which has to be tested in isolation and then integrated into a design when it operates correctly. To verify that a design operates correctly we use simulation, which is a process of testing the design by applying inputs to a circuit and observing its behavior. The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs. The general flow of a simulation is shown in Figure1. Figure 1. The simulation flow. There are two main types of simulation: functional and timing simulation. The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit. Signals are propagated through the circuit using logic and wiring delays of zero. This simulation is fast and useful for checking the fundamental correctness of the 2 Altera Corporation - University Program May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 designed circuit. -
Introduction to Verilog HDL
Introduction to Verilog HDL Jorge Ramírez Corp Application Engineer Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Outline Lexical elements • HDL Verilog Data type representation Structures and Hierarchy • Synthesis Verilog tutorial Operators • Assignments Synthesis coding guidelines Control statements • Verilog - Test bench Task and functions Generate blocks • Fine State Machines • References Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez HDL VERILOG Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez What is HDL? • Hard & Difficult Language? – No, means Hardware Description Language • High Level Language – To describe the circuits by syntax and sentences – As oppose to circuit described by schematics • Widely used HDLs – Verilog – Similar to C – SystemVerilog – Similar to C++ – VHDL – Similar to PASCAL Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Verilog • Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. • Gateway was acquired by Cadence in 1989 • Verilog was made an open standard in 1990 under the control of Open Verilog International. • The language became an IEEE standard in 1995 (IEEE STD 1364) and was updated in 2001 and 2005. Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez SystemVerilog • SystemVerilog is the industry's first unified hardware description and verification language • Started with Superlog language to Accellera in 2002 • Verification functionality (base on OpenVera language) came from Synopsys • In 2005 SystemVerilog was adopted as IEEE Standard (1800-2005). The current version is 1800-2009 Synopsys University Courseware Copyright © 2011 Synopsys, Inc. -
UVM Verification Framework
UVM Verification Framework Mads Bergan Roligheten Electronics System Design and Innovation Submission date: June 2014 Supervisor: Kjetil Svarstad, IET Co-supervisor: Vitaly Marchuk, Atmel Norway AS Norwegian University of Science and Technology Department of Electronics and Telecommunications i Problem description Atmel has a wide range of IP designs and a good, reusable and efficient verification framework is extremely important to have short time to market. UVM (Universal Verification Methodology) is a methodology for functional verification using Sys- temVerilog, which is a set of standardized libraries of SystemVerilog. The student will investigate how UVM can be used to build a reusable verification framework. He has to take decisions on the following tasks: - Synchronization between transaction level and RTL design; - Packing and unpacking transactions and driving them to the design under test; - Configuration database and reusability; - Constrained randomization; - Functional coverage and test execution control; The verification framework can be used on any open source RTL. This is interesting and challenging work on top edge of industry verification. It requires knowledge of SystemVerilog, object-oriented programming and digital systems. Assignment given: January 2014 Supervisor: Kjetil Svarstad, IET Assignment proposer / Co-supervisor: Vitaly Marchuk, Atmel Norway AS ii Abstract iii Abstract The importance of verification is increasing with the size of hardware designs, and reducing the effort required for is necessary to increase productivity. This thesis covers the creation of a reusable verification framework for processor verification using the Universal Verification Methodology (UVM). The framework is used to verify three simple processor designs to evaluate its potential for reuse. The three processors include a synchronous, asynchronous and a stack based processor. -
C 2011 MICHAEL KAHN KATELMAN a META-LANGUAGE for FUNCTIONAL VERIFICATION
c 2011 MICHAEL KAHN KATELMAN A META-LANGUAGE FOR FUNCTIONAL VERIFICATION BY MICHAEL KAHN KATELMAN DISSERTATION Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 2011 Urbana, Illinois Doctoral Committee: Professor Jos´eMeseguer, Chair and Director of Research Professor Arvind, Massachusetts Institute of Technology Associate Professor Grigore Ros, u Professor Josep Torrellas ABSTRACT This dissertation perceives a similarity between two activities: that of coordi- nating the search for simulation traces toward reaching verification closure, and that of coordinating the search for a proof within a theorem prover. The programmatic coordination of simulation is difficult with existing tools for dig- ital circuit verification because stimuli generation, simulation execution, and analysis of simulation results are all decoupled. A new programming language to address this problem, analogous to the mechanism for orchestrating proof search tactics within a theorem prover, is defined wherein device simulation is made a first-class notion. This meta-language for functional verification is first formalized in a parametric way over hardware description languages using rewriting logic, and subsequently a more richly featured software tool for Verilog designs, implemented as an embedded domain-specific language in Haskell, is described and used to demonstrate the novelty of the programming language and to conduct two case studies. Additionally, three hardware description languages are given formal semantics using rewriting logic and we demonstrate the use of executable rewriting logic tools to formally analyze devices implemented in those languages. ii This dissertation is dedicated to MIPS Technologies, Inc., in appreciation for having provided me with the opportunity to closely observe the functional verification effort of the 74K microprocessor. -
Introduction to Simulation of VHDL Designs Using Modelsim Graphical Waveform Editor
Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus II 13.1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the Graphical Waveform Editor in the ModelSim Simulator. It shows how the simulator can be used to perform functional simulation of a circuit specified in VHDL hardware description language. It is intended for a student in an introductory course on logic circuits, who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation. Contents: • Design Project • Creating Waveforms for Simulation • Simulation • Making Changes and Resimulating • Concluding Remarks Altera Corporation - University Program 1 October 2013 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 13.1 2 Background ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits. This tutorial gives a rudimentary introduction to functional simulation of circuits, using the graphical waveform editing capability of ModelSim. It discusses only a small subset of ModelSim features. The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response. The user can use the Waveform Editor to represent the input signals as waveforms. In this tutorial, the reader will learn about: • Test vectors needed to test the designed circuit • Using the ModelSim Graphical Waveform Editor to draw test vectors • Functional simulation, which is used to verify the functional correctness of a synthesized circuit This tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware description language. -
Programmable Logic Design Quick Start Handbook
00-Beginners Book front.fm Page i Wednesday, October 8, 2003 10:58 AM Programmable Logic Design Quick Start Handbook by Karen Parnell and Nick Mehta August 2003 Xilinx • i 00-Beginners Book front.fm Page ii Wednesday, October 8, 2003 10:58 AM PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • © 2003, Xilinx, Inc. “Xilinx” is a registered trademark of Xilinx, Inc. Any rights not expressly granted herein are reserved. The Programmable Logic Company is a service mark of Xilinx, Inc. All terms mentioned in this book are known to be trademarks or service marks and are the property of their respective owners. Use of a term in this book should not be regarded as affecting the validity of any trade- mark or service mark. All rights reserved. No part of this book may be reproduced, in any form or by any means, without written permission from the publisher. PN 0402205 Rev. 3, 10/03 Xilinx • ii 00-Beginners Book front.fm Page iii Wednesday, October 8, 2003 10:58 AM ABSTRACT Whether you design with discrete logic, base all of your designs on micro- controllers, or simply want to learn how to use the latest and most advanced programmable logic software, you will find this book an interesting insight into a different way to design. Programmable logic devices were invented in the late 1970s and have since proved to be very popular, now one of the largest growing sectors in the semi- conductor industry. Why are programmable logic devices so widely used? Besides offering designers ultimate flexibility, programmable logic devices also provide a time-to-market advantage and design integration. -
Ph.D. Candidate CSE Dept., SUNY at Buffalo
Jaehan Koh ([email protected]) Ph.D. Candidate CSE Dept., SUNY at Buffalo Introduction Verilog Programming on Windows Verilog Programming on Linux Example 1: Swap Values Example 2: 4-Bit Binary Up-Counter Summary X-Win32 2010 Installation Guide References 4/2/2012 (c) 2012 Jaehan Koh 2 Verilog o A commonly used hardware description language (HDL) o Organizes hardware designs into modules Icarus Verilog o An open-source compiler/simulator/synthesis tool • Available for both Windows and linux o Operates as a compiler • Compiling source code written in Verilog (IEEE-1364) into some target format o For batch simulation, the compiler can generate an intermediate form called vvp assembly • Executed by the command, “vvp” o For synthesis, the compiler generates netlists in the desired format Other Tools o Xilinx’s WebPack & ModelSim o Altera’s Quartus 4/2/2012 (c) 2012 Jaehan Koh 3 Verilog Programming on Windows o Use Icarus Verilog Verilog Programming on Linux o Remotely have access to CSE system 4/2/2012 (c) 2012 Jaehan Koh 4 Downloading and Installing Software o Icarus Verilog for Windows • Download Site: http://bleyer.org/icarus/ Edit source code using a text editor o Notepad, Notepad++, etc Compiling Verilog code o Type “iverilog –o xxx_out.vvp xxx.v xxx_tb.v” Running the simulation o Type “vvp xxx_out.vvp” Viewing the output o Type “gtkwave xxx_out.vcd” o An output waveform waveform file xxx_out.vcd (“value change dump”) can be viewed by gtkwave under Linux/Windows. 4/2/2012 (c) 2012 Jaehan Koh 5 Icarus Verilog under CSE Systems o Have access to [timberlake] remotely using • [X-Win 2010] software • [Cygwin] software How to check if the required software is installed • Type “where iverilog” • Type “where vvp” Edit source code using a text editor o Vim, emacs, etc. -
Vysok´E Uˇcení Technick´E V Brnˇe
VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ POCˇ ´ITACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ ´I PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR BRNO 2015 VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ POCˇ ´ITACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS METODY AKCELERACE VERIFIKACE LOGICKYCH´ OBVODU˚ NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ ´I PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR VEDOUC´I PRACE´ Doc. Ing. ZDENEKˇ KOTASEK,´ CSc. SUPERVISOR BRNO 2015 Abstrakt Priˇ vyvoji´ soucasnˇ ych´ cˇ´ıslicovych´ system´ u,˚ napr.ˇ vestavenˇ ych´ systemu´ a pocˇ´ıtacovˇ eho´ hardware, je nutne´ hledat postupy, jak zvy´sitˇ jejich spolehlivost. Jednou z moznostˇ ´ı je zvysovˇ an´ ´ı efektivity a rychlosti verifikacnˇ ´ıch procesu,˚ ktere´ se provad´ ejˇ ´ı v ranych´ faz´ ´ıch navrhu.´ V teto´ dizertacnˇ ´ı praci´ se pozornost venujeˇ verifikacnˇ ´ımu prˇ´ıstupu s nazvem´ funkcnˇ ´ı verifikace. Je identifikovano´ nekolikˇ vyzev´ a problemu´ tykaj´ ´ıc´ıch se efektivity a rychlosti funkcnˇ ´ı verifikace a ty jsou nasledn´ eˇ reˇ senyˇ v c´ılech dizertacnˇ ´ı prace.´ Prvn´ı c´ıl se zameˇrujeˇ na redukci simulacnˇ ´ıho casuˇ v prub˚ ehuˇ verifikace komplexn´ıch system´ u.˚ Duvodem˚ je, zeˇ simulace inherentneˇ paraleln´ıho hardwaroveho´ systemu´ trva´ velmi dlouho v porovnan´ ´ı s behemˇ v skutecnˇ em´ hardware. Je proto navrhnuta optimalizacnˇ ´ı technika, ktera´ umist’uje verifikovany´ system´ do FPGA akceleratoru,´ zat´ım co cˇast´ verifikacnˇ ´ıho prostredˇ ´ı stale´ beˇzˇ´ı v simulaci. -
Parallel Systemc Simulation for Electronic System Level Design
Parallel SystemC Simulation for Electronic System Level Design Von der Fakultät für Elektrotechnik und Informationstechnik der Rheinisch–Westfälischen Technischen Hochschule Aachen zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften genehmigte Dissertation vorgelegt von Diplom–Ingenieur Jan Henrik Weinstock aus Göttingen Berichter: Universitätsprofessor Dr. rer. nat. Rainer Leupers Universitätsprofessor Dr.-Ing. Diana Göhringer Tag der mündlichen Prüfung: 19.06.2018 Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar. Abstract Over the past decade, Virtual Platforms (VPs) have established themselves as essential tools for embedded system design. Their application fields range from rapid proto- typing over design space exploration to early software development. This makes VPs a core enabler for concurrent HW/SW design – an indispensable design approach for meeting today’s aggressive marketing schedules. VPs are essentially a simulation of a complete microprocessor system, detailed enough to run unmodified target binary code. During simulation, VPs provide non-intrusive debugging access as well as re- porting on non-functional system parameters, such as execution timing and estimated power and energy consumption. To accelerate the construction of a VP for new systems, developers typically rely on pre-existing simulation environments. SystemC is a popular example for this and has become the de-facto reference for VP design since it became an official IEEE stan- dard in 2005. Since then, however, SystemC has failed to keep pace with its user’s demands for high simulation speed, especially when embedded multi-core systems are concerned. Because SystemC only utilizes a single processor of the host computer, the underlying sequential discrete event simulation algorithm becomes a performance bottleneck when simulating multiple virtual processors.