Wireless Information Transmission System Lab. Introduction to System IC and Design Flow Hung-Chih Chiang Institute of Communications Engineering National Sun Yat-sen University Outline IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues 2 IC Industry Co-Operation Model IDM Sales Channel / Service Provider System House (Brand/OEM/ODM) Design House (Fabless) Siemens Motorola Toshiba IP/Design Service EDA Tool Company Provider Photo Mask/Foundry Service Packaging Service Chip Level Debugging IC Testing Service and Reliability Testing Service 3 Taiwan IC Industry and Supporting System Equipment Capital & HR EDA Foundry Design Assembly Testing Supporting IDM Services Transportation Custom Science Park Mask Wafer Chemicals Lead Frame etc. Materials Source: ITRI, DigiTimes 4 Role of a Design House in an IC Supply Chain Product Development Photo Mask In-house or sub-contract •Market Survey •Product Planning •Chip Design Design House Final Test, QC Chip Manufacturing Packaging Wafer Testing Marketing and Sales In-house or sub-contract Design House Source： Weltrend Semiconductor, Inc 5 IC其實是高科技印刷出版產業 Product Mask Wafer Final Sales & Package R&D &Wafer CP Test Test Logistics IC設計公司 晶圓代工廠 封測公司 封測公司 封測公司 IC設計公司 Turn-key Service 作家/出版商 印刷廠 印刷廠 印刷廠 印刷廠 出版商 製版 作品撰稿 品管檢查 裝訂 成品檢視 配銷 &印刷 Source： IC 設計業與半導體供應鍊 By Jeff Tsai 6 Chip Production Flow Spec. Market/Competitors/IP/Spec. EDA Tools ASIC Design HW/SW Design and Verification Wafer Test Manufacture Mask (Chip Probing) and Modification EDA Tools Package Production Run Pilot Run Chip No good Chip Final Test Chip Verification Debugging Debugging Tools Ok Reliability Test Chip No good Ready Ok 7 Outline IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues 8 SoC Concept Analog Memory PCB ASIC CPU Chip System on a Board Analog IP Memory IP Chip IP I P CPU System on a Chip 9 SoC Technology System-on-a-chip (SoC) technology is the packaging of all the necessary electronic circuits and parts for a "system" (such as a cell phone or digital camera) on a single integrated circuit. 10 Soc Advantages Minimize System Cost PCB, passive components Assembling Testing Compact System Size Board layout vs. chip layout Reduce System Power Consumption I/O, passive components, core voltage and current levels Increase System Performance Interconnecting delay 11 Years 2002 – 2008 Worldwide Communication SoC Market Values Unit: Million U.S. Dollars Product 2002 2003 2004 2005 2006 2007 2008 Digital Cellular 7,480 9,463 12,560 15,210 15,855 17,202 19,013 LAN Wireless 138 333 492 662 777 938 1,134 Mobile Infrastructure 325 344 418 537 511 479 481 Other Mobile Comms. 378 520 673 859 1,077 1,215 1,440 LAN 140 184 248 316 348 392 446 Premises and CO Line Card 167 161 188 201 199 204 219 Broadband Remote Access 918 1,313 1,617 1,793 1,717 1,837 1,978 Public Infrastructure 304 360 481 607 667 810 934 Other Wired Comms. 428 568 811 1,128 1,175 1,365 1,515 Total Communications 10,278 13,246 17,488 21,313 22,326 24,442 27,160 Source: Dataquest (2004/06) 12 Example1: Siemens C35i Phone 13 1. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP. 2. 32.768kHz crystal 3. NIY 14 4. Bottom connector 15 12 5. FLASH 6. Power supply IC 11 16 7. VCO 8. Epcoc B4846; SAW filter, 225.0MHz 17 10 9. PCB pads to Battery 18 9 10. 13MHz crystal 8 11. Tx VCO 19 12. Hitachi PF08112B; Power amplifier 20 7 13. External antenna connetor with switch. 14. Diplex filter 6 21 15. NIY 1 16. Epcos B4127 SAW filter 942.5MHz 17. NIY 2 18. PCB pads to SIM card holder 19. Synthesizer (?) 3 5 20. Hitachi HD155124F– Bright II; GSM Transceiver Circuit 21. Infineon PMB2906: Analog interface IC (E-GAIM). Interfaces analogue signals (I/Q, voiceband, PA-control, charging control signals) to the digital domain 4 13 Example2: Philips DAB Receiver Data IF A/D MPEG MPEG Audio Audio Tuner OFDM Demodulation Channel Decoding Decoder DAC AGC L R Micro- controller Integration vs. Diversity & Process 14 System Integration Trend- Cfone ~2000 2001-2002 2003-2004 2005 Transistors Diodes Synthesizer IC PA PA PA Frequency Converter LNA RF/IF RF Switch RF RF VCOs Filters PA … Single Chip CPU/DSP Audio Processor Digital Baseband Memories Power Management Baseband Analog Baseband Baseband A/D Power management D/A … Memories Flash Memories Flash Memories Resistors Inductors Passive Capacitors Passive components Passive components Passive components … Source: 工研院經資中心ITIS計畫(2002/10) 15 TI- DRP GSM cellular phone solution RF Codec Digital Power Amplifier ADC and DAC Baseband Frequency Transceiver Memory Synthesizer Power Management Digital and RF Power Amplifier SOC ½ Board size ½Power ½ Silicon Area Power Management Memory 16 Outline IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues 17 Affecting Factors for System Integration Process Migration Faster digital to implement RF Density & yield improving IP Resources Reusable IP Cooperate or merge EDA Tools Support System integration tools System verification tools 18 Histories of Key IC Components Logic 1st Bipolar Transistor Belllab in 1956 Memory 1st integrated memory-cell NEC in 1966 1st Bipolar ECL IBM in 1957 1st 1Kb 3T MOS DRAM Intel/Honeywell in 1970 1st IC Fairchild in 1960 1st 2Kb EPROM Intel in 1971 1st TTL Fairchild in 1962 1st 1T DRAM Siemens in 1972 1st CM OS Fairchild in 1963 1st mux-addressed 16Kb DRAM Mostek in 1977 1st 4-bit NMOS uP Intel in 1974 1st 4Kb pseudo-SRAM Intel in 1979 1st 32-bit CMOS uP Belllab in 1981 1st 16Kb EEPROM Intel in 1980 1st 32-bit RISC uP Standford+Berkeley in 1984 1st 256Kb Flash Toshiba in 1985 1st 100Mhz CMOS uP Intel in 1991 1st 256b FRAM Ramtron in 1988 1st 64-bit CMOS uP-200Mhz DEC in 1992 1st multi-level 32Mb Flash Intel in 1995 1st out-of-orde r-execution uP Intel in 1995 DSP 1st sampled-data band-pass Filter Belllab in 1960 1st 32-bit 1Ghz uP-0.18u Intel in 2000 1st analog shift-register Philips in 1972 Analog 1st PLL IC Signetics in 1969 1st switched-capacitor Filte r Berkeley in 1978 1st MOS voice-encoder Berkeley in 1976 1st DSP Belllab in 1980 1st switch-capacitor Filter Berkeley in 1977 1st floating-point 32-bit DSP Bellab in 1985 1st echo-canceller Belllab in 1983 1st Vide o DSP NEC in 1987 1st 1-chip Pager Philips in 1991 1st CM OS re ad-c ha nne l Hitachi in 1993 1st GSM Transceiver Belllab in 1995 1st low-power 16-bit DSP Matsushida in 1993 1st 1024-QAM cable-modem DSP Broadcom in 1998 1st 5Ghz OFDM-BB 80Mb/s Imec in 2000 Source: ISSCC 50th years 19 Moore’s Law and Extensions Source: Intel Gordon Moore (ISSCC2003): - Moore’s Law will extend another 10-15 years. - But no exponential is forever, so delayed Moore’s Law (valid in the past 50 years) will be more realistic for the next 10-15 years. 20 Technology Migration TSMC Logic Technology Roadmap CL018LP CLN90LP CLN90LP Low Power CL015LP CLN65LP 1.2V/2.5V 1.2V/3.3V CL013LP CLN90GT CL013LV(LK) CL018LV 1.2V/2.5V High Speed CL015LV CLN011LV CLN65HS CL013LV 1.2V/1.8, CLN90GT 2.5,3.3V 1.2V/1.8V 1.2~0.15um CLN90G General 1.0V/2.5V CLN65G Purpose CL013G 1.2V/2.5,3.3V CLN90G 1.0V/1.8,3.3V Available Technologies 2004 2005 2006 Source: TSMC Technology Roadmap (Fall 2004) 21 IP Resources IP Libraries (in-company) IP Providers Faraday, Global UniChip, PGC, FameG, … Artisan, ARM, MIPS, Synopsys, Mentor, … Cooperation Partners/Merge companies Free IP (*Usually need some efforts to verify functions and get them work) OpenCores: http://www.opencores.org FPGA CPU News: http://www.fpgacpu.org http://www.mindspring.com/~tcoonan/newpic.html 22 EDA Tool Markets 6,000 PCB Design 單 位 5,000 IC CAD ： CAE/Misc. 百 CAE/Gate Level 萬 4,000 美 CAE/RTL 元 CAE/ESL 3,000 2,000 1,000 0 2000 2001 2002 2003(e) 2004(e) 2005(f) 2006(f) 2007(f) 資料來源：工研院IEK (2004/04) 23 SoC Challenges IP Resource IP library, IP provider, IP quality, IP cost Chip Integration IP cores with different manufacturer processes (logic, memory, analog, high V, …) Chip Design Verification EDA Tools that support system verification at all or mixed design phases Chip Testing Soft/firm/hard cores (logic, memory, analog, …) with or without test circuits, or with different testing strategies 24 Outline IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues 25 System-in-a-Package (SiP) SiP concept Analog Memory ASIC CPU Packaged Chip die substrate 26 Benefits of SiP SiP benefits: Reduced developing schedule Reduced developing cost Possible mounting of different technologies Increased yields enabled by smaller chip size 27 SiP Examples Examples of practical SiP Stack Double side Side by Side 28 Outline IC Industry and Chip Production Flow System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) System IC Design Flow Chip Debugging Tools and Reliability Issues 29 Typical System IC Architecture 30 Traditional Sequential ASIC Design Flow Specification Specification Define System Modeling Algorithm and Architecture Design Circuit Design & Functional Verification HDL/Schematic Circuit Design and function-simulation Logical Synthesis & Timing Verification Logic Synthesis and Pre-simulation P & R & Physical Verification Physical Design and Post-simulation