Asynchronous Signals Acceptable in a Making Asynchronous Signals Acceptable in a Synchronous Society

Making Asynchronous Signals Acceptable In A Making Asynchronous Signals Acceptable In A Synchronous Society

+ a A

“Any sufﬁciently advanced technology is indistinguishable from magic.” Clarke

p.1 Making Asynchronous Signals Acceptable In A Normal D ﬂip-ﬂop operation.

Timing Properties of Flip-Flops

Normal D flip-flop operation. FIG. 2-1 The normal operation of the rising-edge edge-triggered D flip-flop. The input is sampled just before and during the active clock edge. The stored data output appears a short time after the clock edge. Time from input sample to clock edge

INPUT 1D Q INPUT CLOCK C1 CLOCK Rising edge Q Time from clock edge to output is active

FIG. 2-2 If the D input changes just before or during the rising clock edge: the ﬂip-ﬂop may store the old input, the new input, or even half-way in between. To avoid ambiguity disallow input changes in a time region around the clock edge. Region where data must hold still

INPUT 1D Q INPUT CLOCK C1 CLOCK Q

p.2 Making Asynchronous Signals Acceptable In A Normal D ﬂip-ﬂop operation.

Setup, Propagation and Hold Times There are three time intervals associated with the active clock edge in D flip-flops: • The setup time, the interval before the clock where the data must be held stable. • The hold time, the interval after the clock where the data must be held stable. Most modern flip-flops have a zero or a negative hold time. A negative hold time allows the data to change slightly before the clock edge. • the clock to output propagation delay. tCHQV (time from Clock High to Q Valid). FIG. 2-3 The setup and hold times for a flip-flop. The hold time may be negative.

Region where data must hold still

Setup time INPUT INPUT 1D Q Setup time Hold time CLOCK C1 Hold time negative CLOCK Q tCHQV Clock High to Q Valid

p.3 Making Asynchronous Signals Acceptable In A Normal D ﬂip-ﬂop operation.

Example: Setup, Hold and tCHQV FIG. 2-4 Setup time, hold time, and propagation delay. For a 74AC74 CMOS ﬂip-ﬂop. The D INPUT signal shows several possible legal transitions. Region where data should not change 74AC74 D INPUT Setup Hold Prop time time Delay 3 ns Setup time tCHQV 0 ns Hold time 3 ns 0 ns 1 ns min CLOCK 6.5 max

1.5 ns -1.5ns typ Q 1 ns tCHQV, Prop Delay

In the table, the minimum/maximum delays are the ones one uses in most designs. The manufacturer will guarantee those. The typical delay is not very rigorously deﬁned.

p.4 Making Asynchronous Signals Acceptable In A Summary of the Restricted Region

Summary of the Restricted Region The setup and hold times define a restricted time region around the active clock-edge. The flip-flop’s input signal must not change in that region or the flip-flop’s output may: 1) follow the change in D. 2) not follow D. 3) follow it halfway (go metastable).

D INPUT Setup time Hold time CLOCK

Q Q followed D Q Q did not follow D Q went Q metastable

Metastability Metastability is when a flip-flop balances at “1/2” trying to make up its mind whether to go to a 1 or 0. The flip-flop will eventually go to either a 1 or a 0. Usually this will happen in less than a clock cyle. Normally metastability is a problem only for flip-flops running near their maximum speed.

p.5 Making Asynchronous Signals Acceptable In A Synchronous and Asynchronous Signals

Synchronous and Asynchronous Signals A synchronous signal is one which cannot change in the restricted region around the clock edge. An asynchronous signal can and will change anywhere.

FIG. 2-5 Three different D inputs. The upper two are synchronous; they do not change in the restricted region. The lower one is asynchronous; it has a transition inside the restricted region.

Restricted Region Assume D in they don’t 1D Q D in; Synchronous become CLOCK C1 D in; Synchronous asynchronous off stage. D in; Asynchronous CLOCK

p.6 Making Asynchronous Signals Acceptable In A Making an Asynchronous Signal Synchronous

Any signal which passes through a ﬂip-ﬂop is synchronous.

The clock-to-output propagation delay, tCHQV, will give enough delay to move the Q edges out of the restricted region. The Q signal in FIG. 2-6 is synchronous and results from sending the upper signal through a D flip-flop. FIG. 2-6 The Q output of a flip-flop is synchronous. The exceptions are unlikely and mentioned below. Restricted Region

D 1D Q D; Asynchronous CLOCK C1 Q; Synchronous

CLOCK tCHQV

Making an Asynchronous Signal Synchronous Conditions to assure synchronous output Sending an asynchronous signal through a D ﬂip-ﬂop will sychronize it provided:

a) t CHQV)Min >tHOLD This should not happen in any ﬂip-ﬂop designed since ‘75

b) Metastability is not a problem. It is a problem for ﬂip-ﬂops running close to maximum clock speed.

p.7 Making Asynchronous Signals Acceptable In A Making an Asynchronous Signal Synchronous

When is an Input In the Restricted Region Captured? Don’t consider inputs with pulses shorter than a clock cycle, Fast pulse one must use an asynchronous pulse-catching circuit. Clk Consider inputs over 2 clock cycles long. Then an asynchronous input change in the restricted region, • will be captured on this clock edge • or the next clock edge. FIG. 2-7 Synchronizing an asynchronous input. The change in the restricted region will either be caught on the 1st, or on the 2nd edge. SYNCHRONOUS Nonhousebroken CIRCUIT asynchronous D; Asynchronous caught on 1st edge input Q; Synchronous tCHQV, caught on 2nd edge Q D 1D C1 clean CLOCK Hold time CLOCK synchronized output

An asynchronous input may be synchronized by sending it through a D ﬂip-ﬂop before allowing it into a synchronous circuit.

p.8 Making Asynchronous Signals Acceptable In A Input Races Into Synchronous Circuits

Input Races Into Synchronous Circuits A race between an input and the clock The state machine shown has the x input going into two different flipflops. This is satisfactorily until x rises in the restricted region around the clock edge. Then, whether x is captured or not, depends on the individual flip-flops timing. Since there are two flipflops, A might capture x while B did not. This would send the machine to state A,B = 1,1 which is not what was desired. FIG. 2-8 This illustrates how feeding an asynchronous input into two flipflops may cause an error.

11 State Next State DA Asynch 1D A A B X=0 X=1 X C1 00 00 01 10 X=0 X=1 01 01 00 01 10 D B 10 00 10 B 1D Asynchronous 11 00 00 CLK C1 X A+ = A X B+ = B X

DA This might give A = 0 or 1 If it gave AB = 11 as the next state, this would be completely wrong as would DB This might give B = 0 or 1 be AB = 00 Restricted Region

p.9 Making Asynchronous Signals Acceptable In A Input Races Into Synchronous Circuits

Feeding X to a single synchronizing ﬂip-ﬂop, removes the problem.

FIG. 2-9 The problem is cured by synchronizing the signal X. Then both ﬂipﬂops react to the same X. The only states that can be reached from 00 are 01 and 10.

11 D (Sanitary X) A 1D A -11 00 XSAN C1 X=0 X=1 XSAN=0 X =1 SAN 000 100 X 1D 01 X =0 10 C1 SAN XSAN=1 D 001 B 1D B 110 Using XSAN as input FF-X instead of X. C1

FF-X is not included A+ = A X B+ = B X State graph in these states. SAN SAN including FF-X CLK

X XSAN XSANITARY IS A GOOD SYNCHRONOUS SIGNAL

DA DA AND DB ARE NOW SYNCHRONOUS DB Restricted Region

p.10 Making Asynchronous Signals Acceptable In A Synchronization Without Extra Flipﬂops.

Synchronization Without Extra Flipflops. An extra synchronizing flip-flop may not be necessary. The two child states 01 and 10 in FIG. 2-9. differ by two variables. Thus the X input affects two flip-flops. In FIG. 2-10 the two children differ in only one state variable. The X input affects only one flip-flop (one state variable). This flip-flop (state variable) is the one X is connected to. The parent and the child can differ in many state variables. The children must have adjacent states on the Karnaugh map (one variable different). FIG. 2-10 This state table has a branch where the asynchronous input is sensed. The two child states of the branch differ in only one variable. This makes the input directly affect only one flip-flop. There will be no race if X changes near the clock edge.

10 State Next State D A 1D A A B X=0 X=1 PARENT C1 00 STATE 00 01 11 X=0 X=1 X 01 00 00 01 11 D 10 00 00 B 1D B CHILD STATES C1 11 00 00

A+ = A B X B+ = A B

p.11 Making Asynchronous Signals Acceptable In A Synchronization Without Extra Flipﬂops.

Assigning State Variables With Asynchronous Inputs An asynchronous input must change only one flip-flop at a time. It must not simultaneously feed two flipflops. Often a single D-flip-flop is added to synchronize the input. However this is usually unnecessary. Proper state assignment will allow the input to change only one flip-flop.

A single bit difference in the states is equivalent to a single ﬂip-ﬂop changing.

FIG. 2-11 This state assignment is safe if X only changes one ﬂip-ﬂop. The states affected by X must differ by only one state variable. This means states S1 and S2 must be adjacent on a Karnaugh map.

00 01 11 10 0 S1 is adjacent to S2 X=0 S0 X=1 1 S1 S2 S1 S2 Correctly grouped ∆=1 state assignment S1=101 S2=111

p.12 Making Asynchronous Signals Acceptable In A Synchronization Without Extra Flipﬂops.

State Assignment for a 4-Way Branch The variables must be logically unrelated (not encoded). See next section Two children with the same X must be adjacent. Two children with the same Y must be adjacent.

FIG. 2-12 In a two-variable 4-way branch, Two children with the same X must be adjacent, like (S1, S2), (S3, S4). Then placing the pairs (S1, S2) and (S3, S4) together forces Y to change the same ﬂip ﬂop (B) for both pairs. state variable controlled by X AB C \ S1 is adjacent to S2; Both have Y=1 00 01 11 10 S3 is adjacent to S4; Both have Y=0 0 S1 is adjacent to S3; Both have X=1 X 1 1 0 0 PARENT S2 is adjacent to S4; Both have X=0 1 S1 S3 S4 S2 1 0 0 1 XY=11 S0 XY=00 D Y S1 XY=10 S4 X A 1D A Correctly grouped C1 state assignment XY=01 S2 S3 D Y B 1D B C1 1D C1 C=1 independent of the branch

If X and Y both change on the clock edge, what is the worst “error”?

p.13 Making Asynchronous Signals Acceptable In A One Input Controlling Branches From Different

One Input Controlling Branches From Different Starting States FIG. 2-13 One asynchronous input X controlling branches at different times. The changes in X may be sent to different ﬂip-ﬂops.

S6 X=0 S0 X=1 X=0 S7 X=1 S1 S2 S8 S9 ∆=1 ∆=1 0 00 01 11 10 D A 1D A 0 S9 S8 C1 1 S1 S2 D X B 1D B state assignment C1 Correctly grouped 1D C1 C = 1 before the branch from S0 -> S1 or S2 = 0 before the branch from S7 -> S8 or S9

p.14 Making Asynchronous Signals Acceptable In A Self Loops

Self Loops

Self loops can make a state its own child. The children must still differ by only on bit. The parent and the other child must differ by only one bit.

FIG. 2-14 This state assignment is safe if X only changes one ﬂip-ﬂop. The states affected by X must differ by only one state variable. This is states S0 and S1 must be adjacent on a Karnaugh map.

00 01 11 10 0 S0 is adjacent to S1 X=0 S0 X=1 1 S0 S1 S1 Correctly grouped ∆=1 state assignment

p.15 Making Asynchronous Signals Acceptable In A Summary So Far

Summary So Far

Each asynchronous input change must be captured by only one D ﬂip-ﬂop when entering a synchronous circuit.

If a parent state branches on an asynchronous input the two child states reached by the branch must differ by exactly one bit.

BUT THIS MAY NOT BE ENOUGH!

p.16 Making Asynchronous Signals Acceptable In A Examples

Examples PROB 2.1 A Single Asychronous Input to A Synchronous Circuit This is for the Olympics. The timing results are read by the computer. The computer separates start, stop and lap times, and other great things. The counter counts in binary. All the flip-flops run from the microcomputer clock. Appropriate flip-flop reset circuitry exists, and is correct, but is not shown. Would you consider this circuit reliable all the time? If not how would you fix it?. Circuitry for a binary counter REGISTER OF 4 C1 MICROCOMPUTER 1D D FLIP-FLOPS WITH CLOCK EN A COMMON CLOCK C1 1D MICRO 1D 1D COMPUTER EN 1D CONNECTION TO C1 PARALLEL PORT. 1D 1D THIS IS OK EN C1

Combinational Logic Circuitry EN +5 Sports Minded C1 Mad Button Pusher

p.17 Making Asynchronous Signals Acceptable In A Examples

SOLN 2.1 Interfacing to Synchronous Circuitry Yes, the button needs debouncing, but you can do better. The EN signal is asynchronous. If the button is pushed on the clock edge, some flip-flops may count and others may not. An EN signal must be captured by only one flip-flop. FIG. 2-15 A better Olympic Timer. Circuitry for a binary counter C1 MICROCOMPUTER 1D CLOCK EN 1D C1 MICRO 1D COMPUTER 1D EN 1D C1 1D 1D EN C1

Combinational Logic Circuitry EN +5 Sports Minded C1 Mad Button Pusher 1D C1

p.18 Making Asynchronous Signals Acceptable In A Examples

PROB 2.2 Asynchronous Input Problem A ﬁnite state machine has the partial state table shown. Every morning the machine is reset. It then waits for X to be pushed. On Friday the 13th it always seems to come up in bad state. It does not wait for X to be pushed like it should. FIG. 2-16 What is wrong with this design? Finite-State Machine CLK RESET 1D Q1 X=0 +5 S0=0000 C1 X R S1=1110 Q2 X=1 1D C1 S2=1100 R +5 Q3 S3=1000 Y=1 Y 1D Y=0 C1 S4=1101 S5=1001 R

Combinational Logic Circuitry 1D Q4 C1 RESET R +5

p.19 Making Asynchronous Signals Acceptable In A Examples

SOLN 2.2 Asynchronous Input Problem RESET The X and Y inputs are not a problem. CLK X switches between S1=1110 and S2=1100 which differ by one bit as required (∆=1). 0 1 0 1 Y switches between S4=1101 and S5=1001 which differ by one bit as required 0 1 0 1 The RESET signal is asynchronous. 0 1 0 1 Coming out of RESET on the clock edge, 0 0 0 0 may send one to state 1110, 1100, 1000, 1010, 0100, 0010, or 0110. One cure is to synchronize RESET. FIG. 2-17 A better reset for the ﬁnite-state machine

Finite-State Machine CLEAR=1 RESET X=0 Note: S0=0000 ∆=3 1D Q1 +5 SO is its C1 own child S1=1110 X R X=1 Q2 1D S2=1100 ∆=1 C1 R +5 S3=1000 Q3 Y=0 Y=1 Y 1D C1 S4=1101 S5=1001 R ∆=1

1D Q4

Combinational Logic Circuitry C1 R RESET CLK +5 CLEAR 1D C1

p.20 Making Asynchronous Signals Acceptable In A Synchronizing Reset

Synchronizing Reset Clocked Reset Watch out for synchronous reset (Rsyn) built into ﬂip-ﬂops. Rsyn must not be fed an asynchronous signal. FIG. 2-18 The circuit must not come out of reset on a clock edge. Finite-State Machine Combinational Logic

1D 1D 1D RESET CLK +5 C1 C1 C1 1Rsyn 1Rsyn 1Rsyn CLEAR

ONE CAN STILL COME OUT OF RESET ON THE CLOCK EDGE ONE CAN STILL START UP IN A BAD STATE

The RESET signal should be synchronized on release. It is not necessary to synchronize the start of RESET There is no false state one can enter when reset is pushed.

p.21 Making Asynchronous Signals Acceptable In A Synchronizing Reset

Do not synchronize going into reset . Resetting clock dividers and resynchronizers can keep the clock from reaching cer- tain flip-flops. Thus those flip-flops cannot be reset. FIG. 2-19 Resetting the clock divider stops the clock and keeps the other flip-flops from resetting. Finite-State Machine Clock Divider Combinational Logic

1D 1D 1D RESET CLK +5 C1 C1 C1 1D 1Rsyn 1Rsyn 1Rsyn C1 CLEAR

FIG. 2-20 The preferred reset signal. Asynchronous apply. Synchronous remove. Fast CLEAR application 1D 1D Clocked CLEAR removal RESET CLK C1 C1 +5 RESET R R 1D C1 CLEAR CLEAR Reset push at clock edge is applied immediately Reset let up, is delayed till safely after clock edge.

p.22 Making Asynchronous Signals Acceptable In A Synchronizing Reset

SOLN 2.2a Asynchronous Input Problem. Another Solution

Releasing RESET on the clock edge, may send one to 1110, 1100, 1000, 1010, 0100, 0010, or 0110. State S0 has children S0 and S1; note ∆ =3. Before we synchronized RESET with a ﬂip-ﬂop. Alternately make state S1 only 1 bit different from S0. Coming out of RESET can then go only to 0000 or 0100.

FIG. 2-21 Fix machine state assignment Finite-State Machine ∆ RESET =1 X=0 Q1 +5 1D S0=0000 ∆ C1 Note: =3 X R SO is its Q2 own child S1=1110 1D X=1 C1 S2=1100 R S1=0100 +5 ∆=1 Q3 Y 1D C1 S3=1000 R Y=0 Y=1 1D Q4 S4=1101 S5=1001 Combinational Logic Circuitry C1 R ∆=1 CLK Make all RESET +5 children differ by one bit Not 1D Needed Forget the parents C1

p.23 Making Asynchronous Signals Acceptable In A The Problem With Encoded Signals

Asynchronous Inputs of Logically Related or Encoded Variables

The Problem With Encoded Signals When signals on several wires have a collective meaning, be careful about how they enter a synchronous circuit. What will happen if some of the bits are received and others are not. Examples of signals with a collective meaning are: binary numbers, ASCII characters, and bus addresses in microcomputers.

An Example Using Logically Related Signals Consider a digital-temperature sensor which sends out a 4-bit reading. Readings from 0000 to 1110 are interpreted as a temperatures. They are used to control heating and air-conditioning.

A reading of 1111 is too high for normal use and it turns on the ﬁre sprinklers.

p.24 Making Asynchronous Signals Acceptable In A The Problem With Encoded Signals

FIG. 2-22 The four digital wires are each synchronized by four D-flip-flops. The synchronous circuit controls the furnace and the fire sprinkler

CLK DIGITAL THERMOMETER C1 4-BIT OUTPUT SYNCHRONOUS W 1D CIRCUIT X 1D To Y 1D Z furnace FABRIQUE AU CANADA 1D

Suppose several thermometer bits change at once, for example 0111 (7û) to 1000 (8û). When this happens on a clock edge, some bits may be captured and some not. In the worst scenario 1111 is captured and the sprinklers are turned on. FIG. 2-23 If Z is captured a little early and W, X and Y a little late. The synchronous circuit would read 1111 and turn on the sprinklers.

CLK W 1 0 A slight difference in timing X 1 0 makes a large difference in the number latched. Y 1 0 Z 01

p.25 Making Asynchronous Signals Acceptable In A Nonencoded Signals Cause No Problems

Nonencoded Signals Cause No Problems FIG. 2-24 If instead of being encoded, suppose: W turned on a heater in the wash room, X turned on a heater in the bedroom, Y turned on a heater in the kitchen, and Z turned on a heater in the greenhouse If W, X and Y were slow in being captured, it only delays turning them on for one clock cycle.

CLK A slight difference in Washroom W 1 0 timing in the ﬂipﬂops 1 Bedroom X 0 only causes a one clock- Kitchen Y 1 0 cycle delay in turning on Greenhouse Z 01 corresponding heaters.

Logically related or encoded inputs must have at most a single bit change, during the time they are being captured by a synchronous circuit.

p.26 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

How to Synchronize Encoded Signals We will give three methods of treating encoded (logically related) signals: 1) One variable changing at a time. 2) Handshaking 3) Debouncing

Asynchronous Inputs Which Change Only One Variable at a Time Gray Codes Gray codes are binary encodings of numbers. They change only one bit at a time. Their are many of them. Gray codes can be read off a Karnaugh map.

FIG. 2-25 Follow a trace through the Karnaugh map. Writing down the squares in the order you pass through them. The common reﬂected Gray code is shown. AB ≈ ≈ 00 01 11 10 0û 0000 8û 1100 CD 1û ≈ 0001 9û ≈ 1101 00 ∆=1 2û ≈ 0011 10û ≈ 1111 01 3û ≈ 0010 11û ≈ 1110 4û ≈ 0110 12û ≈ 1010 11 5û ≈ 0111 13û ≈ 1011 ≈ ≈ 10 6û 0101 14û 1001 7û ≈ 0100 15û ≈ 1000

p.27 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

FIG. 2-26 Another Gray code which starts at 0000 and ends at 1111. Follow the map trace and equate these binary codes with temperatures. The resulting temperatures change only one bit at a time. If they change on a clock edge, the error is never more than 1û. One can never get to the FIRE state unless the temperature is already at 14û. AB ≈ ≈ 00 01 11 10 0û 0100 8û 1101 CD 1û ≈ 0000 9û ≈ 1100 00 4û 2û ≈ 0001 10û ≈ 1000 01 3û ≈ 0011 11û ≈ 1001 cold 4û ≈ 0010 12û ≈ 1011 11 5û ≈ 0110 13û ≈ 1010 FIRE ≈ ≈ 10 6û 0111 14û 1110 10û 7û ≈ 0101 FIRE ≈ 1111

FIG. 2-27 False-bath resistant controller for the furnace and sprinkler system

CLK DIGITAL THERMOMETER C1 4-BIT GREY CODE OUTPUT SYNCHRONOUS 1D W CIRCUIT 1D X 1D Y 1D Z GREY CODE

p.28 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Johnson Counters Johnson or Mobius counters change only one output bit at a time. The counter is very fast because there are no gates between the flipflops. FIG. 2-28 A Johnson counter. The clock line is shown running behind the flipflops.

1D 1D 1D 1D 1D Main C1 C1 C1 C1 C1 Circuit 1 Ghz Different SIGNAL Clock Not the same clock V W X YZ 00000 10000 11000 11100 11110 11111 01111 00111 00011 00001 Use a fast Johnson counter to measure square-wave frequencies. Use the square-wave to clock the counter, and read VWXYZ with a slower circuit. The pattern tells exactly how many cycles had occurred between readings, provided it is less than ten. The Johnson counter is asynchronous to the main circuit. But the VWXYZ signals can be latched without races. There is no race if only one of the signal changes at a time.

p.29 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

FIG. 2-29 This Johnson counter is a fast, asynchronous clocked, counter. It is suitable for latching directly into a synchronous circuit. However watch out for metastability.

CLK

C1 JOHNSON COUNTER HIGH- 1D SYNCHRONOUS FREQUENCY W CIRCUIT INPUT 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 1D X 1D Y FABRIQUE AU CANADA 1D Z

p.30 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Thermometer Code The fastest analog-to-digital converter known is called the ﬂash A-to-D. It is also the most expensive if much accuracy is desired. If one needs n bit accuracy, one needs 2n comparators in the circuit.

FIG. 2-30 Schematic of a 4-level ﬂash A-to-D converter. The output is called a thermometer code. The bit pattern rises and falls like the mercury in a thermometer. Note that only one bit changes at a time.

V+ '1” if (V+ - V-) > 0 V- Vout = +5.0 V REFERENCE '0” if (V+ - V-) < 0

ANALOG Vin=0.4 1.1 2.6 3.3 4.7 V Vin +4.0 0 0 0 0 1 R +3.0 0 0 0 1 1 R +2.0 0 0 1 1 1 R +1.0 0 1 1 1 1 R

p.31 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

A Flash Converter Interfaces Directly A ﬂash-A-to-D converter can be directly connected to a synchronous machine input. The worst error is reading the old voltage just before the clock edge. FIG. 2-31 A ﬂash A-to-D is suitable for latching directly into a synchronous circuit. However watch out for metastability.

CLK THE FLASH C1 ANALOG INPUT 1D V4 SYNCHRONOUS CIRCUIT 1D V3 1D V2 1D V1

Code Conversions The thermometer code is too long for most applications. Usually a thermometer-to-Gray-code conversion is done. This maintains the single change at a time. One cannot convert binary to Gray code to get single-change outputs. If the binary changes 0111 -> 1000 (3 to 4), it might have transient outputs. 0111->0011->0001->1001->1000 Each transient output would generate a transient Gray code output.

p.32 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Handshaking Methods One and only one signal is the handshake. It is made true only after all associated lines (D1 through D4 below) are stable. If handshake = false: the associated lines may not be stable. If handshake = true: the associated signals will be stable for some known duration. The known duration may be: one or more clock cycles, until the handshake goes false, some other convention.

FIG. 2-32 All the associated signals, D1 through D4, are stable when the handshake =1. The handshake is captured on the 1st clock edge after it goes high. The latched ENABLE then lets through D1..D4 which will be stable near the clock edge. SYNCHRONOUS CIRCUIT CLK THE GADGET C1 HANDSHAKE ENABLE 1D Q D4 V4 D3 V3 D2 V2 D1 V1

p.33 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

FIG. 2-33 FIG. 2-32 repeated SYNCHRONOUS CIRCUIT CLK THE GADGET C1 HANDSHAKE ENABLE 1D Q D4 V4 D3 V3 D2 V2 D1 V1

FIG. 2-34 Typical waveforms for the circuit of FIG. 2-32 HANDSHAKE Handshake could come at clock edge D4 D3 D2 The Ds may change here, but they must be stable before HANDSHAKE rises D1

CLK

ENABLE ENABLE is synchronous V4 V3 V1, V2, V3 and V4 are synchronous V2 even though D1, D2, D3 and D4 were not V1

p.34 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

The Less Restricted Handshake It is not necessary for the HANDSHAKE signal to rise before the associated signals. One only needs a know delay between the HANDSHAKE rising and the associated signals stabilizing. D1 through D4 below, have almost a clock cycle to stabilize after HANDSHAKE rises.

FIG. 2-35 The HANDSHAKE signal is latched on the ﬁrst clock edge. D1 through D4 are latched on the second clock edge. They need only stabilize a setup time before the second edge.

CLK THE GADGET C1 C1 HANDSHAKE 1D Q ENABLE EN2 D4 1,2D V4 SYNCHRONOUS CIRCUIT D3 1,2D V3 D2 1,2D V2 D1 1,2D V1

The tug-of-war synchronizer works this way

p.35 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

FIG. 2-36 FIG. 2-35 repeated. CLK THE GADGET C1 C1 HANDSHAKE ENABLE 1D Q EN2 D4 1,2D V4 SYNCHRONOUS CIRCUIT D3 1,2D V3 D2 1,2D V2 D1 1,2D V1

FIG. 2-37 The HANDSHAKE signal is latched on the ﬁrst clock edge. The D signals are latched on the next edge. They need not be stable until they are ready to be latched.

HANDSHAKE D4 D3 D2 D1 The Ds may change until a setup time before the 2nd clock edges CLK ENABLE ENABLE is synchronous V4 V3 V2 V1

p.36 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Debouncing Latches the asynchronous data several times. Accepts it when all bits are the same on two consecutive readings. This method is good if you know the inputs, once changed, will stay stable for several clock cycles.

FIG. 2-38 A ﬂow chart of a system to sychronize data by Debouncing.

LATCH DATA record

WAIT 1 CLOCK CYCLE wait

LATCH DATA AGAIN record

NOARE BOTH YES COPIES OF DATA ACCEPT DATA THE SAME? WORK ON IT. compare

p.37 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Debouncing in Hardware

FIG. 2-39 A circuit that reads data, shifts the old data into a new set of ﬂipﬂops, and reads the data again. Then it compares the two reads.

record wait record compare

DIGITAL COMPARE C1 C1 D1 1D 1D V1 D2 1D 1D V2 DATA OK D3 1D 1D V3 INPUT ASYNCHRONOUS XNOR is a two-bit compare

p.38 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

PROB 2.1 The Coconut Counter The following circuits counts coconuts as they fall by the photocell. The original circuit only lit the display. That always functioned correctly. Then a consultant added the computer interface using the register shown. Every once in a while the computer reads a wildly incorrect coconut count. This sometimes gets printed on invoices and leads to embarrassment. Fix the interface design. Appropriate ﬂip-ﬂop reset circuitry exists, and is correct, but is not shown. Note coconuts do not fall at supersonic velocities.

RIPPLE COUNTER MICROCOMPUTER C1 CLOCK 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 P 1D 1D PHOTOCELL CONNECTION TO 1D PARALLEL PORT THIS IS OK 1D 1D COCONUTS REGISTER OF 5 MICRO FALLING BY D FLIP-FLOPS WITH COMPUTER PHOTOCELL A COMMON CLOCK

p.39 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

SOLN 2.1 The Coconut Counter Comments: • The ripple counter clocks on the rising edge. • It may ripple for one or two clock cycles. • The counter output is encoded asynchronous signals. • The register must not capture data while the counter is changing. •

Debouncing Solutions Read the count in two consecutive cycles. If they are the same, the counter was stable.

Software debouncing If you have control of the software, do the debouncing in software!

Hardware debouncing is excessively complex.

p.40 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Hardware debouncing

FIG. 2-40 Circuit to pass only stable data to the computer The circuit compares data captured on two consecutive clock-edges The output register is enabled when the two data-samples are equal.

RIPPLE COUNTER MICRO COMPUTER RCNTR C1 C1 C1 EN Accept if high CLOCK C+ REG1 REG2 REG3 P [1] 1D 1D 1D [2] 1D 1D 1D [4] 1D 1D 1D [8] 1D 1D 1D [16] 1D 1D 1D MICRO COMPUTER Asynchronous record wait record input COMPARE = =

XNOR is a two-bit comparator

p.41 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Handshaking Solutions

FIG. 2-41 Constructing a handshaking signal to enable REG3 The ripple counter only changes after a rising edge of P. H is low before the rising edge and disables REG3. H is delayed by enough ﬂip-ﬂops to be sure the ripple-counter is stable before H rises.

2 cycle delay (because ripple may take 2 cycles) MICRO P C1 COMPUTER RCNTR C1 C1 H CLOCK C+ 1D 1D EN REG3 [1] 1D [2] 1D [4] 1D

RIPPLE [8] 1D MICRO COMPUTER Ripples for one or two COUNTER [16] 1D clock cycles

CLK P coconut goes by ripple counter active

2 cycle delay H REG3 enabled

p.42 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

Handshaking Solutions (cont.) FIG. 2-42 A handshaking signal for a fast ripple counter The new count must ripple-through the counter in under one clock cycle. The D ﬂip-ﬂop synchronizes the P signal. The counter is stable before the next clock edge. MICRO +5 COMPUTER RCNTR C1 CLOCK H EN C1 P C+ REG3 P 1D syn [1] 1D [2] 1D FAST [4] 1D RIPPLE COUNTER 1D [8] MICRO COMPUTER [16] 1D

FIG. 2-43 Add delay if ripple-through takes over a cycle. CLK Psyn H two cycle delay MICRO C1 C1 COMPUTER RCNTR D C1 CLOCK 1D 1D H EN C1 P C+ REG3 P 1D syn [1] 1D [2] 1D [4] MICRO COMPUTER

p.43 Making Asynchronous Signals Acceptable In A Asynchronous Inputs Which Change Only One

FIG. 2-44 Opposite edge (level) solution The counter counts whenPsyn rises. P stays high long enough for the ripple count to complete, even with speedy coconuts H is low when the ripple-through takes place. H enables REG3 long after the ripple. MICRO COMPUTER RCNTR C1 CLOCK H EN C1 P C+ REG3 P 1D syn [1] 1D [2] 1D [4] 1D RIPPLE COUNTER 1D [8] MICRO COMPUTER [16] 1D

CLK P coconut goes by Psyn ripple counter active

H REG3 enabled REG3 enabled Check other edge too (It’s OK here).

p.44 Making Asynchronous Signals Acceptable In A Glitches Will Cause Errors

Hazards in Asynchronous Inputs

Glitches Will Cause Errors If an asynchronous input has a glitch on it, and if that glitch comes in the restricted region, then it may be captured as a valid input. Sending the signal through a D flip-flop will not work here. The flip-flop could also capture the glitch. The cure is to remove glitches from asynchronous inputs. One should be very careful about doing logic with asynchronous signals. When two or more signals feed a logic network it is very hard to avoid multiple variable glitches. Try to synchronize the individual variables and then do the logic in the synchronous part of the circuit.

1D C1

p.45 Making Asynchronous Signals Acceptable In A Glitches Will Cause Errors

Example From Educational Literature

PROB 2.1 Motor speed control. The binary counter counts sensor pulses for 1 second. The count is compared with the setpoint register. A FAST or a SLOW, or neither is sent to the controller. There is a slack of ±3 to avoid hunting. Suggest some problems and some cures. FIG. 2-45 A potential hazard

Write

Binary Set point Counter R Register 10 ω s 10 Digital Compare Synchronous Controller ω>s-3 ω

SLOW Next clock cycle clk reset binary counter

p.46 Making Asynchronous Signals Acceptable In A Glitches Will Cause Errors

SOLN 2.1 Hazardous Motor Speed Control A binary counter is full of glitches. A glitch may be caught by the FAST, the SLOW, or both lines. Assume a Gray code counter. The ±3 keeps saves the design. If FAST and SLOW were 1 count apart, SLOW there could be a double transition from SLOW to FAST FAST on the last motor pulse. Is the reset clean? Yes, because it synchronous.

Do glitches matter on a motor control? No, a good low-pass ﬁlter is a great glitch minimizer.

p.47 Making Asynchronous Signals Acceptable In A Methods of Dealing With Multiple Changes

Concurrent Input Changes

Methods of Dealing With Multiple Changes Multiple variable changes were “not allowed” in asynchronous analysis The method could not deal with them. State table analysis may still give a solution:

“Go ahead and sue me” method Calculate all the states reachable from the potential double change. This may be all states! Calculate the cost of such a transition and the probability that it will happen. If it will poison the city water supply, more work is needed. If it will make your talking doll say a bad word, your design may be good enough.

Interlock the input Asynchronous arbiters can be designed. An example follows.

p.48 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter

The Tug-of-War Arbiter FIG. 2-46 The tug -of-war game.

Contents: Player 1 LEDs Player 2 -2 -1 0 1 2 3 push-buttons, BL BR 5 light-emitting diodes (LEDs) 1 ﬁeld-programmable gate array RESET CLOCK

Playing the Game Push reset.

After a random time the centre LED comes on. Then each player will try to push his button ﬁrst. The position of the lit LED will move toward the fastest button pusher. If player 2 is fastest, the light shifts LED 0 -> LED 1. End of round one.

After a second the LEDs will all go out. After a random time LED 1 will come on. Again each player will try to push his button ﬁrst. Again the light will shift toward the fastest button pusher.

The game is won when the position of the lit LED move off the end of the display.

p.49 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter

Speciﬁcations of the Push-Button Latch

FIG. 2-47 The synchronous and asynchronous parts. RESET BL LEDs Asynchronous 1D -2 -1 0 1 2 CLOCK BR Push-Button C1 Circuit Synchronizer Clocked Logic

The push button circuit shall be as fair as modern technology can make it. i) It must tell who pushed ﬁrst within the propagation delay of two inverters. ii) It shall have no theoretical bias toward one player. iii) If your circuit goes into a tie state, it shall either: - have equal probability of exiting toward either player. - leave the light stationary for that round. iv) It should not depend on which player releases their button ﬁrst. In a tie, this lets the winner be determined by the bounce properties of the push buttons. The Synchronizer: i) Shall not transfer the wrong information to the clocked logic because of glitches or pushes near the clock edge. ii) A tie shall not be transferred as a win. iii) A win shall not be transferred as a tie. iv) The wrong winner shall not be transferred.

p.50 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter

FIG. 2-48 The State Diagram for the Latch. The Push Button Latch State A...... No button pushed since Clear. BL,BR=0,0 State B...... Button 2 (right) was pushed ﬁrst. P,R/L=0,0 State C...... Button 1 (left) was pushed ﬁrst. BL=1 Input BL...... Left Button input. BR=1 Input BR...... Right Button input. C A Input Clear...CLEAR BL,BR=x,x Clear=1 B Output P...... PUSH; some button pushed. P,R/L=1,0 Clear=1 Output R/L....R(H)/L(L), High if BR was pushed BL,BR=x,x before BL; low if BL preceded BR P,R/L=1,1

FIG. 2-49 State Table for the State Diagram

Pres Next State Output A race free state assignments for the latch. State Inputs= BL, BR, Clear 000 010 110 100 - -1 P, R/L BL AAB - CA0- C=10 BR BBB - BA11 A=00 CCC - CA10 Clear B=01 D------Clear Circled states are stable. - = don’t care

p.51 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter

Handling the double input change Take all the don’t care states and ﬁll them in with. State A initially looks reasonable. It causes no bias on a tie. FIG. 2-50 State table with all default states made “A.”

A State graph with all defaults A. Pres Next State Output State Inputs= BL, BR, Clear D=11 000 010 110 100 - -1 P, R/L BR,BL=0,0; 1,1 AABACA0- BL=1 BBBABA11 C=10 BR=1 CCCACA10 A=00 DAAAAA - Clear B=01 Clear

If both buttons are pushed at once: • A tie does not have a bias toward either side. • Pushing two buttons together is a different kind of race. It is true that the state change A=00 ->D=11, may instead go 00 -> 10 or 00 -> 01, This is just one side or the other winning. It is normal circuit operation for the faster side to win. For this problem, we have solved the “no double input change” rule

p.52 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter

Side effects of this state table a) When there is a tie, one stays in state A=00, only while BR,BL = 1,1. If a switch breaks contact the person pushing that switch will lose. This “lose on ﬁrst bounce” is an avoidable unfairness. FIG. 2-51 Push-button latch state tables that almost made it.

a)Pres Next State Output b) Pres Next State Output State Inputs= BL, BR, Clear State Inputs= BL, BR, Clear 000 010 110 100 - -1 P, R/L 000 010 110 100 - -1 P, R/L AABACA0- AABDCA0- BBBABA11 BBBABA11 CCCACA10 CCCACA10 DAAAAA - DAAAAA -

Lose on first bounce Cycle on tie

Questionable modiﬁcation to the state table b) Replace the “A” in the middle of a) by “D.” This cures the lose on ﬁrst bounce, but makes a tie a cycle. An oscillatory input to the synchronous circuit is not desirable.

p.53 Making Asynchronous Signals Acceptable In A The Tug-of-War Arbiter