Making Asynchronous Signals Acceptable In A Making Asynchronous Signals Acceptable In A Synchronous Society + a A “Any sufficiently advanced technology is indistinguishable from magic.” Clarke © John Knight Electronics Department, Carleton University 9/19/02 p.1 Making Asynchronous Signals Acceptable In A Normal D flip-flop operation. Timing Properties of Flip-Flops Normal D flip-flop operation. FIG. 2-1 The normal operation of the rising-edge edge-triggered D flip-flop. The input is sampled just before and during the active clock edge. The stored data output appears a short time after the clock edge. Time from input sample to clock edge INPUT 1D Q INPUT CLOCK C1 CLOCK Rising edge Q Time from clock edge to output is active FIG. 2-2 If the D input changes just before or during the rising clock edge: the flip-flop may store the old input, the new input, or even half-way in between. To avoid ambiguity disallow input changes in a time region around the clock edge. Region where data must hold still INPUT 1D Q INPUT CLOCK C1 CLOCK Q © John Knight Electronics Department, Carleton University 9/19/02 p.2 Making Asynchronous Signals Acceptable In A Normal D flip-flop operation. Setup, Propagation and Hold Times There are three time intervals associated with the active clock edge in D flip-flops: • The setup time, the interval before the clock where the data must be held stable. • The hold time, the interval after the clock where the data must be held stable. Most modern flip-flops have a zero or a negative hold time. A negative hold time allows the data to change slightly before the clock edge. • the clock to output propagation delay. tCHQV (time from Clock High to Q Valid). FIG. 2-3 The setup and hold times for a flip-flop. The hold time may be negative. Region where data must hold still Setup time INPUT INPUT 1D Q Setup time Hold time CLOCK C1 Hold time negative CLOCK Q tCHQV Clock High to Q Valid © John Knight Electronics Department, Carleton University 9/19/02 p.3 Making Asynchronous Signals Acceptable In A Normal D flip-flop operation. Example: Setup, Hold and tCHQV FIG. 2-4 Setup time, hold time, and propagation delay. For a 74AC74 CMOS flip-flop. The D INPUT signal shows several possible legal transitions. Region where data should not change 74AC74 D INPUT Setup Hold Prop time time Delay 3 ns Setup time tCHQV 0 ns Hold time 3 ns 0 ns 1 ns min CLOCK 6.5 max 1.5 ns -1.5ns typ Q 1 ns tCHQV, Prop Delay In the table, the minimum/maximum delays are the ones one uses in most designs. The manufacturer will guarantee those. The typical delay is not very rigorously defined. © John Knight Electronics Department, Carleton University 9/19/02 p.4 Making Asynchronous Signals Acceptable In A Summary of the Restricted Region Summary of the Restricted Region The setup and hold times define a restricted time region around the active clock-edge. The flip-flop’s input signal must not change in that region or the flip-flop’s output may: 1) follow the change in D. 2) not follow D. 3) follow it halfway (go metastable). D INPUT Setup time Hold time CLOCK Q Q followed D Q Q did not follow D Q went Q metastable Metastability Metastability is when a flip-flop balances at “1/2” trying to make up its mind whether to go to a 1 or 0. The flip-flop will eventually go to either a 1 or a 0. Usually this will happen in less than a clock cyle. Normally metastability is a problem only for flip-flops running near their maximum speed. © John Knight Electronics Department, Carleton University 9/19/02 p.5 Making Asynchronous Signals Acceptable In A Synchronous and Asynchronous Signals Synchronous and Asynchronous Signals A synchronous signal is one which cannot change in the restricted region around the clock edge. An asynchronous signal can and will change anywhere. FIG. 2-5 Three different D inputs. The upper two are synchronous; they do not change in the restricted region. The lower one is asynchronous; it has a transition inside the restricted region. Restricted Region Assume D in they don’t 1D Q D in; Synchronous become CLOCK C1 D in; Synchronous asynchronous off stage. D in; Asynchronous CLOCK © John Knight Electronics Department, Carleton University 9/19/02 p.6 Making Asynchronous Signals Acceptable In A Making an Asynchronous Signal Synchronous Any signal which passes through a flip-flop is synchronous. The clock-to-output propagation delay, tCHQV, will give enough delay to move the Q edges out of the restricted region. The Q signal in FIG. 2-6 is synchronous and results from sending the upper signal through a D flip-flop. FIG. 2-6 The Q output of a flip-flop is synchronous. The exceptions are unlikely and mentioned below. Restricted Region D 1D Q D; Asynchronous CLOCK C1 Q; Synchronous CLOCK tCHQV Making an Asynchronous Signal Synchronous Conditions to assure synchronous output Sending an asynchronous signal through a D flip-flop will sychronize it provided: a) t CHQV)Min >tHOLD This should not happen in any flip-flop designed since ‘75 b) Metastability is not a problem. It is a problem for flip-flops running close to maximum clock speed. © John Knight Electronics Department, Carleton University 9/19/02 p.7 Making Asynchronous Signals Acceptable In A Making an Asynchronous Signal Synchronous When is an Input In the Restricted Region Captured? Don’t consider inputs with pulses shorter than a clock cycle, Fast pulse one must use an asynchronous pulse-catching circuit. Clk Consider inputs over 2 clock cycles long. Then an asynchronous input change in the restricted region, • will be captured on this clock edge • or the next clock edge. FIG. 2-7 Synchronizing an asynchronous input. The change in the restricted region will either be caught on the 1st, or on the 2nd edge. SYNCHRONOUS Nonhousebroken CIRCUIT asynchronous D; Asynchronous caught on 1st edge input Q; Synchronous tCHQV, caught on 2nd edge Q D 1D C1 clean CLOCK Hold time CLOCK synchronized output An asynchronous input may be synchronized by sending it through a D flip-flop before allowing it into a synchronous circuit. © John Knight Electronics Department, Carleton University 9/19/02 p.8 Making Asynchronous Signals Acceptable In A Input Races Into Synchronous Circuits Input Races Into Synchronous Circuits A race between an input and the clock The state machine shown has the x input going into two different flipflops. This is satisfactorily until x rises in the restricted region around the clock edge. Then, whether x is captured or not, depends on the individual flip-flops timing. Since there are two flipflops, A might capture x while B did not. This would send the machine to state A,B = 1,1 which is not what was desired. FIG. 2-8 This illustrates how feeding an asynchronous input into two flipflops may cause an error. 11 State Next State DA Asynch 1D A A B X=0 X=1 X C1 00 00 01 10 X=0 X=1 01 01 00 01 10 D B 10 00 10 B 1D Asynchronous 11 00 00 CLK C1 X A+ = A X B+ = B X DA This might give A = 0 or 1 If it gave AB = 11 as the next state, this would be completely wrong as would DB This might give B = 0 or 1 be AB = 00 Restricted Region © John Knight Electronics Department, Carleton University 9/19/02 p.9 Making Asynchronous Signals Acceptable In A Input Races Into Synchronous Circuits Feeding X to a single synchronizing flip-flop, removes the problem. FIG. 2-9 The problem is cured by synchronizing the signal X. Then both flipflops react to the same X. The only states that can be reached from 00 are 01 and 10. 11 D (Sanitary X) A 1D A -11 00 XSAN C1 X=0 X=1 XSAN=0 X =1 SAN 000 100 X 1D 01 X =0 10 C1 SAN XSAN=1 D 001 B 1D B 110 Using XSAN as input FF-X instead of X. C1 FF-X is not included A+ = A X B+ = B X State graph in these states. SAN SAN including FF-X CLK X XSAN XSANITARY IS A GOOD SYNCHRONOUS SIGNAL DA DA AND DB ARE NOW SYNCHRONOUS DB Restricted Region © John Knight Electronics Department, Carleton University 9/19/02 p.10 Making Asynchronous Signals Acceptable In A Synchronization Without Extra Flipflops. Synchronization Without Extra Flipflops. An extra synchronizing flip-flop may not be necessary. The two child states 01 and 10 in FIG. 2-9. differ by two variables. Thus the X input affects two flip-flops. In FIG. 2-10 the two children differ in only one state variable. The X input affects only one flip-flop (one state variable). This flip-flop (state variable) is the one X is connected to. The parent and the child can differ in many state variables. The children must have adjacent states on the Karnaugh map (one variable different). FIG. 2-10 This state table has a branch where the asynchronous input is sensed. The two child states of the branch differ in only one variable. This makes the input directly affect only one flip-flop. There will be no race if X changes near the clock edge. 10 State Next State D A 1D A A B X=0 X=1 PARENT C1 00 STATE 00 01 11 X=0 X=1 X 01 00 00 01 11 D 10 00 00 B 1D B CHILD STATES C1 11 00 00 A+ = A B X B+ = A B © John Knight Electronics Department, Carleton University 9/19/02 p.11 Making Asynchronous Signals Acceptable In A Synchronization Without Extra Flipflops.