Appendix A: Transistor-Transistor Logic

Transistor-transistor logic, TTL, became the dominant logic family in the mid­ 1960s as the first steps towards integrating circuits became possible. Although metal-oxide-silicon, MOS, logic has since become at least as important, and integration is several orders of magnitude greater, many of the performance criteria of logic families in general are still specified in terms of TTL circuits. The industry standard TTL is the 74 series, in which the allocated number defines the logic operation and pin layout, regardless of manufacturer. The basic TTL circuit, as, for example, in the 7400 two-input NAND gate of figure A.la, uses a multi-emitter transistor, Tl, at the input, and a push-pull circuit, T3 and T4, at the output. This is also known as a totem-pole circuit. Transistor T2 acts as a phase-splitter to provide the output stage with the necessary antiphase signals. When either input A or B, or both, is taken to a voltage, V1L , lower than about half a volt (but not negative), the corresponding emitter conducts and transistor T2 cuts off. The emitter current, IlL, has a maximum value of 1.6 milliamps. If both input emitters are taken to a voltage between 2 and 5 volts, VIH , neither emitter conducts and T2 switches on. The control of the gate can best be seen in terms of the current in the 4k resistor: the current is diverted away from T2 through the emitter if the input voltage is low, and flows to T2 if neither input is low. In the latter case, the current at the base of T2 switches it on, so that T4 is also switched on and T3 is switched off. The output voltage then falls to VOL at about 0.2 volts, and the circuit draws in, or sinks, up to 16 milliamps of current. When the current is diverted away from T2, it switches off, also switching off T4 and switching on T3. The output voltage now rises to VOH ' and the circuit can provide, or source, up to 400 microamps. The 130 n resistor is included to protect the output transistors, by limiting the current during switching, but also has the effect of reducing the value of VOH • The additional voltage drops across the diode D3, included to ensure correct switching levels, and across T3, mean that the typical value of VOH is only 3.4 volts. The action of the circuit is such that any low voltage, VIL , on an input, sets the gate output high, VOH ' and the gate output only goes low, VOL, if there are no low voltages at the inputs. If we think of the high-level voltage as representing logic'1" the circuit acts as a NAND gate. By including inverters at inputs and output, as appropriate, other forms of gate such as AND, OR and NOR can be generated. The same form of circuit is also used in building flipflops, and more complex systems.

102 i • • +5 V

130 5

::t:.. :g 3.:~fV'~>-VOH 3';.~VIHs D3 3 A o. '. ~ ~ ~AB 3 2.4 D- ::t:.. B e>-+----4 2 .. 2~~I ~ D1 s 1 '0.8 ~. ~ o TYP 0.2 ~L O~J;~"'n-~ ~ ------VOL r Input voltage Output voltage a range range ~ ~ t;. (a) (b) ~ .... ~

~. Figure A.l Standard TTL gate. (a) Circuit. (b) Voltage levels ~

...... ~ 104 Interfacing the BBC Microcomputer

V1H and V1L are the voltage levels at the gate inputs needed to cause the gate to operate correctly, so generating the output levels, VOH and VOL, which are dependent on the logic conditions. The standard TTL levels have quite a wide tolerance, as shown in figure A.1b, and are specified as follows:

Vrn = 1.0 V minimum VOH =2.4 V minimum (typically 3.4 V) V1L =0.8 V maximum VOL =0.4 V maximum (typically 0.2 V) The corresponding current levels are

I ill = 40 JJA maximum IOH = -400 JJA maximum IlL =-1.6 rnA maximum IOL = 16 rnA maximum The negative sign indicates that current is flowing out of the gate terminal. Since each gate can sink 16 milliamps at its output, and each emitter input that it drives requires a current of 1.6 milliamps, when its input voltage is low, the one gate can drive up to ten similar gates. It is said to have a fanout of 10. When the driven emitters are taken to the high level, each takes 40 microamps and the driving gate can provide 400 microamps, so again the fanout is 10. Improvements in fabrication techniques over the years have led to extensive developments in TTL circuitry, and modern TTL is usually the low-power Schottky version, 74LS, or, increasingly, the advanced low-power Schottky, 74ALS (some­ times designated 74F). The majority of LS TTL circuits do not now use the multi­ emitter input transistor, but make use of Schottky diodes, since these give a shorter switching delay. Schottky diodes do not suffer the charge-storage problems of conventional diodes (and transistors) and so switch between states much faster. They are also used as clamping diodes on the transistors to prevent charge-storage. With the help of the Schottky diodes, and by increasing the circuit resistance values somewhat, 74LS circuitry can operate at about twice the speed of standard TTL, but at only one-fifth of the power dissipation. Some of the input and output levels are slightly modified when compared with standard TTL:

IIH =20 JJA maximum VOH =2.7 V minimum (typically 2.4 V) IlL =-0.36 rnA maximum VOL = 0.5 V maximum (typically 0.35 V)

The newer 74ALS versions make use of die shrinking techniques recently developed, which, together with modified isolation methods, gives another doubling of the speed and a further halving of the power dissipation. In many cases the input loading requirements and the output driving capa­ bilities of different versions are quoted in terms ofunit loads (UL) normalised to the standard TTL figures. Thus, in the high state, one unit load, UL, is 40 microamps, and in the low state, one unit load is 1.6 milliamps. The input load factor for 74LS TTL is then 0.36 mA/1.6 rnA = 0.225 UL (normally rounded to 0.25 UL) in the low state, and 20 JJA/40 JJA = 0.5 UL in the high state. The output current I OL is 8 milliamps, so the low-level drive factor is 8.0 mA/1.6 rnA =5 UL, and the high-level drive factor is 400 JJA/40 JJA = 10 UL. Appendix A: Transistor-transistor Logic 105

Special drive circuits such as the 74LS245 are designed to operate at much higher current levels:

1m =30 J.lA maximum I OH = -15 rnA maximum IlL =-0.2 rnA maximum I OL = 24 rnA maximum giving load factors of 20 J.lA/40 J.lA =0.5 UL (high state) and 0.2 mA/l.6 rnA = 0.125 UL (low state), and drive factors of 15 mA/40 J.lA = 375 UL (high state) and 24 mA/l.6 rnA = 15 UL (low state). Many large-scale integrated circuits use NMOS technology, which is a voltage­ controlled form of logic, rather than the current control used in TTL. However, in most cases, the outputs are again standardised in terms of TTL levels. The port B connections of the VIA on the user port, for example, are quoted as having current levels of

IIH =100 JJ,A maximum I OH =-1 rnA maximum IlL =--1.6 rnA maximum I OL = 1.6 rnA maximum In terms of unit loads, therefore, the input load factors are 100 JlA/40 JlA = 2.5 UL in the high state and 1.6 mAl 1.6 rnA = 1 UL in the low state. The output drive factors are 1 mA/40 J.lA = 25 UL in the high state and 1.6 mAl1.6 rnA = 1 UL in the low state. Thus, as long as the factors are correctly matched, NMOS and TTL can be directly connected together. The same applies with CMOS and TTL, except that when driving CMOS from TTL the CMOS, operating at 5 volts, requires a Vm value of 4.3 volts minimum, whereas LS TTL output voltage, VOH ' is typically 3.4 volts and can be as low as 2.7 volts. The solution is to include a 10kn pull-up resistor to +5 volts at the output of the TTL gate. Standard CMOS can drive two 74LS inputs directly. Under certain circumstances it is desirable to connect the outputs of two or more gates together, but a little thought will show that the TTL totem-pole circuit of figure A.la would not last long if connected to a similar circuit. Very soon, one circuit would be set with its upper transistor, T3, on, while the other would be set with its lower transistor, T4, on, and one of the transistors (normally the upper) would act as a fuse, as a large current flowed from +5 volts to ground! One occasion for outputs to be connected together is in wired-OR logic, when the common point is to be taken low if gate A, or gate B, or any other gate out­ put goes low. In such circumstances we must use open-collector versions of the TTL gates. These are identical to normal gates except that T3, 03 and the 130 n resistor are omitted. It is then necessary to provide an external resistor at the commoned outputs to act as the collector load. The resistor value depends on the number ofgates involved and suitable values are given for different conditions in the manufacturer's literature. A second requirement for commoned outputs arises in bus-organised systems, such as our microcomputer. Anyone of many registers may be required to feed data onto the bus, but only one register is selected at any time. Here we make use of three-state circuits which have additional enabling circuitry built in. 106 Interfacing the BBCMicrocomputer

When the gate is enabled it acts as a conventional TTL circuit with totem-pole output. But when it is disabled, both transistors in the totem-pole circuit are switched off, so that the circuit presents a high impedance to the bus, and is effectively disconnected from it. The use of these logic circuits, and the design of logic systems in general, is a fascinating area of study. Anyone wishing to develop the ideas that we have briefly outlined here should consult more specialised books such as Fundamentals ofModern Digital Systems by B. R. Bannister and D. G. Whitehead, published by Macmillan, 1983. Appendix B: Machine Code Programming

Whenever the computer is running it is working methodically through a sequence of instructions which is known as the program. The range of operations from which the instructions can be selected is limited and each operation is very simple, but the processing circuitry can deal with about half a million instructions each second, which makes it very powerful. The instructions are coded in binary, which is the only form that the circuitry can accept, and it is this form that is called machine code. Users, however, find it difficult and very time-eonsuming to work in binary, and the need to concentrate on getting the coding right tends to restrict the range of programming ideas that we can employ. The obvious thing to do is to construct programs in a form that is more meaningful to the user, and pass the tedious work of conversion into machine code back to the computer. The more meaningful version of machine code is called assembler language, and the program that the computer uses to translate the assembler code to the form it requires is the assembler. Thus when the computer is running the assembler, it is using the user's assembler language program as data to be translated to another form of data. The user's program in assembler language is the source code which is translated to object code in binary, and the object code can then be run as a program in its own right. Since the assembler relates closely to the machine code of the particular microprocessor, it is also processor-specific, and it is often preferable to work in a higher-level language which, with minor modifications, could run on different computers if a suitable translating program is provided. Many high-level languages have been designed, but by far the most popular for personal computers is BASIC which is an acronym for Beginners' All-purpose Symbolic Instruction Code. Programs written in BASIC, or any other high-level language, use pseudo-English statements which are much more understandable to the user, but are meaningless strings of characters to the circuitry that will actually carry out the operations defined. Again, each BASIC statement has to be translated, and a special program is provided which operates on the user's program and converts it to a form similar to assembler. It is then further converted to machine code form which is acceptable to the computer circuitry. Most high-level languages employing this method of translation make use of a type of program known as a compiler; the complete user program is translated to machine code form, so that, once the compilation is com­ pleted, the program can be run and rerun as often as required, without further translation. BASIC, however, is normally dealt with in a different way. Each

107 108 Interfacing the BBeMicrocomputer

BASIC statement is interpreted into machine code form, and is immediately carried out. No copy is kept of the machine code form and the interpreter program must re-interpret each statement if it returns to it. This makes BASIC much slower than compiled languages, especially where repetitive loops are concerned. The operation of the different levels of program can conveniently be thought of as a series of software shells, built around the processing circuitry of the computer. The hardware forms the kernel, and the assembler language makes the innermost shell. BASIC, or some other high-level language, forms another shell, and so on. By designing different additional shells, we can effectively change the characteristics of the computer, as far as a user is concerned, without having to change any of the hardware. Applications packages, such as word-processing programs, for example, can be added as extra shells, and users need no knowledge of how the computer is operating internally. However, there are advantages in working in assembler language, especially when we are interfacing other equipment to the computer; programs are shorter and operate much faster and they also make much more efficient use of memory. Furthermore, knowing in more detail how the processor actually works allows us to exploit some of its special features, which are not fully used by the high-level languages. There are, of course, times when it is easier to use BASIC, and a very important feature of the BASIC interpreter held in the ROMs in the BBC microcomputer is the ability to mix machine code sections with BASIC statements, to get the best of both worlds. In effect, we can operate in two shells at the same time. The processor used in the BBC computer is the 6502, which is one ofthe processors in the 6500 series. The microprocessor operates on data in eight-bit bytes, and in common with all microprocessors it has a range of registers which are used in carrying out specific operations. Many of the registers are only for internal use - what we call housekeeping operations - and, as far as the program­ mer is concerned, the 6502 has three general registers, the accumulator and index registers X and Y. In addition, three of the special registers are important: the program counter, PC, the stack pointer, SP, and the processor status register. The program counter indicates the location in program memory where the next instruction is to be found. It is a 16-bit counter since any part of the 65 536 location memory space may be used for program purposes. At the beginning of each instruction cycle the instruction must be fetched from memory. The complete information necessary to specify an instruction may require one, two or three bytes, but in all cases the first byte fetched is the op-code byte. This byte is decoded to indicate the type of operation involved, and it also indicates how many more bytes, if any, are needed to complete the instruction. Each op­ code byte is associated with a mnemonic from the instruction set listing, such as LDA for load accumulator, STX for store content ofX register, and so on. The complete set of mnemonics is given in appendix D, section 1 together with the total number of bytes needed in each case. The additional bytes are necessary to specify the operands that are to be used in carrying out the instruction. LDA, for example, means load accumulator with a data byte, and we need to specify the Appendix B: Machine Code Programming 109

location in memory, or elsewhere, that is to be used to provide the data. There are several different ways in which the operands can be specified, and these addressing modes are explained in appendix D, section 1. In building-up the instruction, each time a byte is taken from memory the program counter is incremented, so that, when all the necessary bytes have been fetched, the program counter points to the start of the next instruction, ready for the next fetch sequence to begin. The fetch sequence is complete when various housekeeping operations have been carried out, and the execution phase follows immediately. During this phase the operations indicated by the instruction are carried out, and, where appropriate, the condition flags are set. The condition flags are individual flipflops which indicate the status of the processor after each operation, and together they form the condition code which is held in the processor status register. The flags are carry, C set to '1' if a carry occurred at the most-significant bit of the accumulator zero, Z set to '1' if accumulator value became zero overflow, V set to '1' if the number range of the accumulator was exceeded negative, N set to '1' if the msb of the accumulator became '1', so indicating a negative value decimal mode, D set to '1' if arithmetic operations are to be in binary­ coded decimal interrupt disable, I set to '1' if external interrupts are disabled break command, B set to '1 ' if the instruction was BRK. The number of mnemonics in the instruction set is 56, though, when we take all the addressing variations into account, the number of instruction types available is almost three times that. The instructions can be split into four main groups: • Those involved with transfers of data between registers and to and from memory. • Arithmetic and logic operations, such as add, AND, compare, decrement, exclusive-OR, increment, rotate, etc. • Flag operations, such as set or clear the carry flag, set or clear the decimal flag, etc. The majority of the instructions in these first three groups affect the settings of at least some of the flags in the processor status register, to reflect the new conditions. • Branch instructions. This group includes jump, IMP, jump to subroutine, ISR, return from subroutine, RTS, and several conditional jumps, such as branch if carry flag set, BCS, branch if minus, BMI (that is, branch if negative flag set), and so on. The branch instructions react to the flag settings but do not modify them. 110 Interfacing the BBCMicrocomputer

The effect of all jump instructions is to change the program counter value, so that the next instruction is taken not from the next sequential location but from the indicated new location. Most jumps and branches are non-return, and subsequent instructions are taken sequentially from the new position. Jump to subroutine, JSR, however, retains the original value of the program counter, so that when a return instruction, RTS, is encountered, the original value of the program counter can be restored. The value is stored until required in a section of memory known as the stack, which is exactly the same as all the other read/write random access memory, except that it is addressed via a counter known as the stack pointer, SP, which is automatically incremented or decremented when used. Special instructions allow us to write to and read from the stack, and these are known as push and pull respectively. The stack, in the BBC computer, is located in page 1 of memory and runs from &0100 to &01FF . . The assembler provided in the computer is a conventional two-pass assembler, which allows the use of labels to indicate locations. A small section of program, for example, could be .START LOA &FE60 : STA &70 CMP #0 : BEQ START LOA #0: STA ACR During assembly, the label .START is allocated the value of the address at which the op-code LOA is stored, and, whenever the label is encountered later on, the address is substituted. Individual instructions are terminated either by the return at the end of a line, or by the colon. This small section of machine code loads the accumulator from location &FE60, stores that value at location &70, then com­ pares the value with zero and, if equal to zero, jumps back to the location labelled START. Otherwise it continues to the next instruction following, and loads the accumulator with zero; it finally stores the zero in the register location labelled ACR. This has of necessity been only a brief introduction to assembly language pro­ gramming. Section 43 of the User Guide contains a full account of the methods used to link the assembler sections, such as we have discussed, into a BASIC program. A much more thorough coverage of the whole field of machine code programming will be found in Assembly Language Programming for the BBC Microcomputer (second edition) by Ian Birnbaum, published by Macmillan, 1984. Appendix C:lnput-Output Memory Map

&FFFF &FEFF TUBE OPERATING SYSTEM /~ &FEEO ROM i &FEC3 ADC ~K , &FECO J.lPD7002 &FFOO / &FEA3 ADLC, ECONET 68B54 &FEFF &FEAO &FE84 INPUT-0UTPUT FDC 8271 ~K &FE80 &FCOO &FE6F &FBFF VIA B 6522 &FE60 , &FE40 VIAA 6522 OPERATING SYSTEM SHEILA PAGED ROM SELECT ROM &FE30 74LS163 \ &FE21 VIDEO ULA &FE20 &FE18 ECONET INTERRUPT CONTROL &COOO 15K \ &BFFF &FE10 SERIAL ULA \ &FE09 ACIA 6850 &FE08 &FE01 CRTC 6845 \ &FEOO PAGED &FDFF ROMs \ LOW EIGHT BITS 1 OF EXTENDED JIM ADDRESS USED WITH \ PAGING REGISTER &8000 16K &FDOO J &7FFF \ JIM PAGE REGISTER &FCFF &FCFE USER APPLICATIONS \ &FCCO &FCBF ACORN RESERVED \ &FC90 &FC8F TEST HARDWARE &FC80 1 MHz &FC7F \ ACORN RESERVED BUS &FC48 \ &FC47 WINCHESTER DISC &FC40 FRED &FC3F CAMBRIDGE RING \ &FC30 &FC2F ACORN RESERVED &FC28 RAM \ &FC27 IEEE-488 INTERFACE &FC20 \ &FC1F PRESTEL &FC14 &FC13 TELETEXT \ &FC10 &FCOF TEST HARDWARE \ &FCOO

32K &0000

111 Appendix D: Data Sheets

1. SY6500 8-bit Microprocessor Family Reproduced by courtesy of Synertek Inc., Honeywell House, Charles Square, Bracknell, Berkshire, UK 2. SY6522 Versatile Interface Adapter, VIA Reproduced by courtesy of Synertek Inc., Honeywell House, Charles Square, Bracknell, Berkshire, UK 3. ~PD7002 12-bit Binary AID Converter Reproduced by courtesy of NEC Electronics (UK) Ltd, Devonshire House, Bank Street, Lutterworth, Leicestershire, UK 4. SN74LS244 Octal Buffers and Line Drivers with 3-state Outputs Reproduced by courtesy of Texas Instruments Ltd, Manton Lane, Bedford, UK 5. SN74LS245 Octal Bus Transceivers with 3-state Outputs Reproduced by courtesy of Texas Instruments Ltd, Manton Lane, Bedford, UK

The manufacturers reserve the right to make changes at any time in order to improve design and to supply the best product possible. Therefore, they cannot assume any responsibility for the information given or represent that it is free from patent infringement.

112 Appendix D: Data Sheets 113

~ertek SY6500 8-Bit Microprocessor Family

Features • Single 5 V ±5% power supply •Instruction decoding and control • N channel, silicon gate, depletion load technology • Addressable memory range of up to 65 K bytes • Eight bit parallel processing • "Ready" input • 56 Instructions • Direct memory accesscapability • Decimal and binary arithmetic • Bus compatible with MC6800 • Thirteen addressing modes • Choice of external or on-board clocks • True indexing capability • 1 MHz, 2 MHz, 3 MHz and 4 MHz operation • Programmable stack pointer • On-chip clock options • Variable length stack * External single clock input • Interrupt capability * Crystal time base input • Non-maskable interrupt • 40 and 28 pin package versions • Use with any type or speed memory • Pipeline architecture • Bi-directional Data Bus

Description

The SY6500 Series Microprocessors represent the first totally software compatible microprocessor family. This family of products includes a range of software compatible microprocessors which provide a selection of addressable memory range, interrupt input options and on-chip clock oscillators and drivers. All of the microprocessors in the SY6500 family are software compatible within the group and are bus compatible with the MC6800 product offering. The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs or crystals provide the time base. The external clock versions are geared for the multi-processor system applications where maximum timing control is mandatory. All versions of the microprocessors are available in 1 MHz, 2 MHz, 3 MHz and 4 MHz maximum operating frequencies.

Members of the Family Ordering Information

PART SY P6502A NUMBERS CLOCKS PINS IRQ NMI RYD ADDRESSING ~ -~ -~ SY6502 On-Chip 40 ~ J J 64 K SYNERTEK 1SPEED SY6503 28 J 4K No Suffix = 1 MHz SY6504 28 J 8K NO PREFIX A = 2 MHz SY6505 28 J J 4K OOC to 70°C B = 3 MHz SY6506 28 J 4K C = 4 MHz SY6507 28 J 8K PACKAGE TYPE SY6512 External 40 J J J 64 K P = Plastic SY6513 28 J J 4K 0= CERDIP SY6514 28 J 8K C = Ceramic I.-SPECIFICTYPE SY6515 28 J J 4K 02-07 65XX FAMILY 12-15

Only 6502 and 6512 are availablein 3 and 4 MHz 114 Interfacing the BBeMicrocomputer

Synertek. SY6500

PI n Functions

Non·Maskable Interrupt (NMI) Clocks H'" "2) The SY651 X requires a two phase non-overlapping clock A negative going transition on this input requests that a that runs at the Vcc voltage level. non-mask able interrupt sequence be generated within the microprocessor. The SY650X clocks are supplied with an internal clock generator. The frequency of these clocks is externally con­ NMI is an unconditional interrupt. Following completion of trolled. Clock generator circuits are shown elsewhere in this the current instruction, the sequence of operations defined data sheet. for IRQ will be performed, regardless of the state interrupt mask flag. The vestor address loaded into the program counter, low and high, are locations FFFA and FFFB Address Bus (A o-A,5) (See sections on each micro for respective address lines on those devices.) respectively, thereby transferring program control to the memory vector located at these addresses. The instructions These outputs are TTL compatible, capable of driving one loaded at these locations cause the microprocessor to standard TTL load and 130 pF. branch to a non-maskable interrupt routine in memory.

NM I also requires an external 3Kn resistor to V for Data Bus (DB ) cc o·DB 7 proper wire-OR operations. Eight pins are used for the data bus. This is a bi-directional bus, transferring data to and from the device and peripherals. Inputs IRQ and NMI are hardware interrupts lines that are The outputs are three-state buffers, capable of driving one sampled during 0-.2 (phase 2) and will begin the appropriate standard TTL load and 130 pF. interrupt routine on the 0, (phase 1) following the comple­ tion of the current instruction. Data Bus Enable (DBE) Set Overflow Flag (S.O.) This TTL compatible input allows external control of the three-state data output buffers and will enable the micro­ A NEGATIVE going edge on this input sets the overflow processor bus driver when in the high state. In normal bit in the Status Code Register. This signal is sampled on operation DBE would be driven by the phase two (0 ) clock, the trailing edge of 0, . 2 thus allowing data output from microprocessor only during 0~. During the read cycle, the data bus drivers are internally SYNC disabled, becoming essentially an open circuit. To disable This output line is provided to identify those cycles in data bus drivers externally, DBE should be held low. This which the microprocessor i~ doing an OP CODE fetch. The signal is available on the SY6512, only. SYNC line goes high during 0, of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line Ready (ROY) is pulled low during the 0, clock pulse in which SYNC went This input signal allows the user to halt the microprocessor high, the processor will stop in its current state and will on all cycles except write cycles. A negative transition to remain in the state until the RDY line goes high. In this the low state during or coincident with phase one (0, ) will manner, the SYNC signal can be used to control ROY to halt the microprocessor with the output address lines cause single instruction execution. reflecting the current address being fetched. This condition will remain through a subsequent phase two (0-.2) in which Reset (RES) the Ready signal is low. This feature allows microprocessor This input is used to reset or start the microprocessor from interfacing with low speed PROMS as well as fast (max. 2 a power down condition. During the time that this line is cycle) Direct Memory Access (DMA). If ready is low during held low, writing to or from the microprocessor is inhibited. a write cycle, it is ignored until the following read opera­ When a positive edge is detected on the input, the micro­ tion. Ready transitions must not be permitted during 0-.2 processor will immediately begin the reset sequence. time. After a system initialization time of six clock cycles, the Interrupt Request (IRQ) mask interrupt flag will be set and the microprocessor will load the program counter from the memory vector locations This TTL level input requests that an interrupt sequence FFFC and FFFD. This is the start location for program begin within the microprocessor. The microprocessor will control. complete the current instruction being executed before recognizing the request. At that time, the interrupt mask After Vee reaches 4.75 volts in a power up routine, reset bit in the Status Code Register will be examined. If the must be held low for at least two clock cycles. At this time interrupt mask flag is not set, the microprocessor will begin the R/W and SYNC signal will become valid. an interrupt sequence. The Program Counter and Processor When the reset signal goes high following these two clock Status Register are stored in the stack. The microprocessor cycles, the microprocessor will proceed with the normal will then set the interrupt mask flag high so that no further reset procedure detailed above. interrupts may occur. At the end of this cycle, the program counter low will be loaded from address FFFE,and program ReadlWrite (R!W) counter high from location FFFF, therefore transferring program control to the memory vector located at these This output signal is used to control the direction of data addresses. The RDY signal must be in the high state for any transfers between the processor and other circuits on the interrupt to be recognized. A 3Kn external resistor should data bus. A high level on R/W signifies data into the pro­ be used for proper wire-OR operation. cessor; a low is for data transfer out of the processor. Appendix D: Data Sheets 115

Synertek. SY6500

Programming Characteristics

INSTRUCTION SET - ALPHABETIC SEQUENCE ADC Add Memory to Accumulator with Carry LOA Load Accumulator with Memory AND "AND" Memory with Accumulator LOX Load Index X with Memory ASL Shift left One Bit (Memory or Accumulator) LOY Load Index Y with Memory LSR Shift One Bit Right (Memory or Accumulator) BCC Branch on Carry Clear BCS Branch on Carry Set NOP No Operation BEQ Branch on Result Zero ORA "OR" Memory with Accumulator BIT Test Bits in Memory with Accumulator BMI Branch on Result Minus PHA Push Accumulator on Stack BNE Branch on Result not Zero PHP Push Processor Status on Stack BPL Branch on Result Plus PLA Pull Accumulator from Stack BRK Force Break PLP Pull Processor Status from Stack BVC Branch on Overflow Clear ROL Rotate One Bit Left (Memory or Accumulator) BVS Branch on Overflow Set ROR Rotate One Bit Right (Memory or Accumulator) CLC Clear Carry Flag RTI Return from Interrupt CLD Clear Decimal Mode RTS Return from Subroutine CLI Clear Interrupt Disable Bit SBC Subtract Memory from Accumulator CLV Clear Overflow Flag with Borrow CMP Compare Memory and Accumulator SEC Set Carry Flag CPX Compare Memory and Index X CPY Compare Memory and Index Y SED Set Decimal Mode DEC Decrement Memory by One SEI Set Interrupt Disable Status DEX Decrement Index X by One STA Store Accumulator in Memory DEY Decrement Index Y by One STX Store Index X in Memory STY Store Index Y in Memory EOR "Exclusive-or" Memory with Accumulator TAX Transfer Accumulator to Index X INC Increment Memory by One TAY Transfer Accumulator to Index Y INX Increment Index X by One TSX Transfer Stack Pointer to Index X INY Increment Index Y by One TXA Transfer Index X to Accumulator JMP Jump to New Location TXS Transfer Index X to Stack Pointer JSR Jump to New Location Saving Return Address TYA Transfer Index Y to Accumulator

ADDRESSING MODES

Accumulator Addressing This form of addressing is represented with a one byte Page, Y." The effective address is calculated by adding the instruction, implying an operation on the accumulator. second byte to the contents of the index register. Since this Immediate Addressing is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally In immediate addressing, the operand is contained in the due to the "Zero Page" addressing nature of this mode, no second byte of the instruction, with no further memory carry is added to the high order 8 bits of memory and addressing required. crossing of page boundaries does not occur. Absolute Addressing Indexed Absolute Addressing - (X. Y indexing) In absolute addressing, the second byte of the instruction specifies the eight low order bits of the effective address This form of addressing is.used in conjunction with X and Y while the third byte specifies the eight high order bits. index register and is referred to as "Absolute, X," and Thus, the absolute addressing mode allows access to the "Absolute, Y." The effective address is formed by adding entire 65K bytes of addressable memory. the contents of X or Y to the address contained in the second and third bytes of the instruction. This mode allows Zero page Addressing the index register to contain the index or count value and The zero page instructions allow for shorter code and the instruction to contain the base address. This type of execution times by only fetching the second byte of the indexing allows any location referencing and the index to instruction and assuming a zero high address byte. Careful modify multiple fields resulting in reduced coding and use of the zero page can result in significant increase in execution time. code efficiency. Implied Addressing Indexed Zero Page Addressing - (X. Y indexing) In the implied addressing mode, the address containing the This form of addressing is used in conjunction with the operand is implicitly stated in the operation code of the index register and is referred to as "Zero Page, X" or "Zero instruction. 116 Interfacing the BBeMicrocomputer

Synertek. SY6500

ReI.tive Addressing Indirect Indexed Addressing Relative addressing is used only with branch instructions In indirect indexed addressing (referred to as (Indir­ and establishes a destination for the conditional branch. ectl.Y), the second byte of the instruction points to .a memory location in page zero. The contents of this The second byte of the instruction becomes the operand which is an "Offset" added to the contents of the lower memory location is added to the contents of the Y index register, the result being the low order eight bits of the eight bits of the program counter when the counter ~s effective address. The carry from this addition is added set at the next instruction. The range of the offset IS to the contents of the next page zero memory location, -128 to +127 bytes from the next instruction. the result being the high order eight bits of the effective Indexed Indirect Addressing address. In indexed indirect addressing (referred to as (Indir­ Absolute Indirect instructio~ a~ded ect,X)), the second byte of the is to The second byte of the instruction contains the low the contents of the X index register, discarding the order eight bits of a memory location. The high order carry. The result of this addition points to a memory eight bits of that memory location is contained in the location on page zero whose contents is the low order third byte of the instruction. The contents of the fully ~emo.ry eight bits of the effective address. The next specified memory location is the low order byte of the location in page zero contains the high order eight bits effective address. The next memory location contains of the effective address. Both memory locations specify­ the high order byte of the effective address which is ing the high and low order bytes of the effective address loaded into the sixteen bits of the program counter. must be in page zero.

Programming Characteristics

PROGRAMMINGMODEL

7 , I A I ACCUMULATOR A 7 y • INOEX REGISTER y I I ~ IRO OISABlE 1 =OlSABlE 7 • ~ DECIMAL MODE 1 ~ TRUE I x I INOEX REGISTER X ~---- BRK COMMAND 1 ~ BRK 15 7 J I PCH I PCl I PROGRAM COUNTER "PC" 7 ., ~------OVERFLOW 1 ~ TRUE S STACK POINTER "S" I I ~------NEGATIVE 1 ~ NEG. Appendix D: Data Sheets 117

-Svnertek. SY6500 INSTRUCTION SET - OP CODES, EXECUTION TIME, MEMORY REQUIREMENTS

_ ...an , , a•• a.. , ••UllVI .....ltl ,.a", eM',lI •• e.... "'.ltC'_ &111\ lin ,.•••a" ace.. _," .... ,..." ,.a"...... '"u".. 0" N 0" N .OP N• OP N • OP N OP N • OP N oplN • OP N ·OP N• OP N • OP N • OP N • N Z C I o V A DC A+M+C-A (41111 260 43 65 3 2 I 71[S 2 JJ J I ~12 7~ 1412 AND A I\M -A (11 292 2:20 4 3 25 3 21 6 2 3152 35 4 2 3D 4 3 39 4 3 '1 I - - 6' 61' I ASL C~~~. 'E 6 3 t6 S 1 I IE 7 1.1 I 'TI' I ~.i,:, i i 'TI' I I ICC IRANCHQNC.. 121 :.+ I 13 I i ICS BRANCH ON c-i 121 i ! I I B' 2 i:2 - - BEO IRANCH ON Z-1 121 F.1212 ! -- ! M, I IIT AI\M i 2C 413 243 2 M. ! i II BM I BRANCH ON N' 1 121 ! 'tf 31 21 2 i ! BRANCH 0111 Z'I 121 I i I :I Of 212 - -- - BillE I I I II I BPL BRAIIICH 0111111=' 121 i I I " 2 2 I >-- ---=----=---=- BRK ISMF'gll - ..!7l, j t 'I - -.I - I I I BRAIIICH 0111 V-I 121 L ! I 51 2 2 -- - BVC I II I' BVS BRANCH ON V-I 121 ; II i: 71 2 2 CLC I-C I I I! i -I- I lr I~ ~8 2~ I 'I -I CLo .- 0 - 1 1-~ 5& 2i, I 1 CLI I-I "t' I I I ' i eLV I-V 88,2 1 1 ++ I I CMP A-M "I 2 col4 3 C5312 10 Is 2 i 1 I CPX X-M E' 2 2 EC 4 3 E432 :I osl'!' ex'!'I' o'!,I' II I e'l+ ~~ 2 CC 4 3 C4 3 2 I I II I ~~-_ ~2 I ~ .. _- i -- DEC M-I -M CE 6 3 C6 5 2 i-+- 06 6 I I i:- I I oEi713 i DE X X-I -X CAI2 I I 1 i 2 J I- I I I I II I J oEV V-I -V Ii 88! 2 i I ! I EOR A..,M-A 111 49 2 :2 40 4 34S 3 2 4162 5152 551412 :~:~ ~ 59'413 11 I I I 1111 C M" -M EE6 3 E6 5 2 II -=-- 1111 X X. I-X EB21 Fr~ I J 1111 Y V. I-V +1 C8 2 1 I / I I JMP JUMP TO IIIEW LOC 4C 3 3 6C 5 3 JS R ISM F,g 21 JUMP SUB 2. 6 3 LOA M-A (II A9 '] 2 AD 4 3 A5 312 II Al 6 2 " .1, 8s14 2 BD 43 B9 4 3 11 I I - -

_ 0" N _ 0" N _oP N• oPN _oPN _oPN .oPN LOX M-X (11 A:2:2 :2 AE 4 3 A6 3 2 BE 4 3 86 4 2 JJ L 0 V M - Y (11 A' 2 2 AC 4 3 A4 3 2 B4 4 2 BC 4

LSR .....~C 4E6 3 46 5 2 4A 2 1 566 2SE 7 •" J NO P NO oPERATION EA 2 1 ORA AVM-A t9 2 2.0 4 1 15 3 2 " 6 2 11 S 2 IS 4 2 10 4 3 19 4 3 "H AA- Mt S-1 - S 41 3 1 PH P P - Mt 5-1 - S 1831 PLA S+1-5 Mt-A 68 4 1 PLP 5 + 1 -·5 MI-P 28 4 1 ROL ~ Ii~.-J 2E 6 3 26 5 2 2A 2 36 6 2 3E- 7 3 76 6 2 7E 7 3 ROR t+~~ 6E 6 3 66 S 2 6A 2 RT I (Set F.g. 11 RTRN tNT 4' 6 1 RESTOREDI RTS (Set F.g 2) RTRN SUI 61 6 1 SBC A-M-C-A 10 E9 2 2 ED 4 3 ES3 2 El 6 2 FI S 2 F54 2 r o 4 3 F9 4 3 JJ (31- J SEC l-C 38 2 1 SED 1-0 FI21 SE I 1-1 STA A-M 804 3 15 3 2 8162911629542905 399,S 3 ST)( X-M BE4 3 86 3 2 STY Y-M IC 4 3 14 3 2 l TAX A- X TAY ,,- V AI 2 1 TS XS-X IA 2 1 TXA X-A IA 2 1 T)( S X-S 9A 2 1 TVA V-A 98 2 1

111 ADD 1 TO "N" IF PAGE BOUNoARV IS CROSSED X IIII0EX X ADO 1II0T MODIFIED (21 ADD 1 TO "N" IF IRANCH OCCURS TO SAME PAGE 'Y IIII0EX Y -- SUBTRACT M, MEMORY BIT 7 ADD 2 TO "N" IF IRANCH OCCURS TO DIFFEREIIIT PAGE A ACCUMULA TOR 1\ AND M. MEMORY 81T 6 131 CARRY NOT - IROW M MEMORY PER EFFECTIVE ADDRESS V OR III 1110 CYCLES 141 IF IN DECIMAL MODE Z FLAG IS INVALID M, MEMORV PER STACK POIIIITER .., EXCLUSIVE OR • NO BYTES ACCUMULA TOR MUST If CHECKED FOR ZERO RESUL T J MODIFIED 118 Interfacing the BBeMicrocomputer

~rtek. SY6522/SY6522A Versatile Interface Adapter (VIA)

Features • Two a-Bit Bidirectional I/O Ports • Expanded "Handshake" Capability Allows Positive • Two l6-Bit Programmable Timer/Counters Control of Data Transfers Between Processor and • Serial Data Port Peripheral Devices • Single +5V Power Supply • Latched Output and Input Registers • TTL Compatible • 1 MHz and 2 MHz Operation • CMOS Compatible Peripheral Port A lines

Description The SY6522 Versatile Interface Adapter (VIA) is a be programmed aseither an input or an output. Several very flexible I/O control device. In addition, this de­ peripheral I/O lines can be controlled directly from vice contains a' pair of very powerful l6-bit interval the interval timers for generating programmable fre­ timers, a serial-to-parallel/parallel-to-serial shift re­ quency square waves or for counting externally gen­ gister and input data latching on the peripheral ports. erated pulses. To facilitate control of the many power­ Expanded handshaking capability allows control of ful features of this chip, an interrupt flag register, an bi-directional data transfers between VIA's in multiple interrupt enable register and a pair of function con­ processor systems. trol registers are provided. Control of peripheral devices is handled primarily through two 8-bit bi-directional ports. Each line can

INTERRUPT ,...------ilfC CONTROL

FLAGS (IFR)

ENABLE PORTA (IER)

DATA BUS

1_------CAl 1_------CA2

RES .....---+-..----- CBl Rm ....--.....----_ CB2 lb2 CSl CHIP C§ ACCESS RSO CONTROL RSl RS2 PORT B RS3

Figure 1. SY6522 Block Diagram Appendix D: Data Sheets 119

Svnertek.-- SY6522/SY6522A Absolute Maximum Ratings· Comment· This device contains circuitry to protect the inputs Rating Symbol Value Unit against damage due to high static voltages. However, Supply Voltage Vee -0.3 to +7.0 V it is advised that normal precautions be taken to Input Voltage VIN -0.3 to +7.0 V avoid application of any voltage higher than maxi­ Operating Temperature mum rated voltages. Range TA o to +70 °C Storage Temperature Range Tstg -55 to +150 °C

Electrical Characteristics (Vee = 5.0V ± 5%, TA = Q-70°C unless otherwise noted) Symbol Character istic Min. Max. Unit

VIH Input High Voltage (all except <1>2) 2.4 Vee V VeH Clock High Voltage 2.4 Vee V VIL Input Low Voltage -0.3 0.4 V liN Input Leakage Current - VIN = 0 to 5 Vdc - ±2.5 Jl.A RIW, ~, RSO, RS1, RS2, RS3, CS1, CS2, CAl, <1>2

ITSI Off-state Input Current - VIN = .4 to 2.4V - ±10 Jl.A Vee = Max, DOto 07 IIH Input High Current - VIH = 2.4V -100 - Jl.A PAO-PA7, CA2, PBQ-PB7, CB1, CB2 IlL Input Low Current - VIL = 0.4 Vdc - -1.6 mA PAO-PA7,CA2,PBO-PB7,CB1,CB2

VOH Output High Voltage 2.4 - V Vee = min, lload = -100 Jl.Adc PAQ-PA7, CA2, PBQ-PB7, CB1, CB2

VOL Output Low Voltage - 0.4 V Vee = min, lload = 1.6 mAde IOH Output High Current (Sourcing) VOH = 2.4V -100 - Jl.A VOH = 1.5V (PBQ-PB7) -1.0 - mA IOL Output Low Current (Sinking) 1.6 - mA VOL = 0.4 Vdc

IOFF Output Leakage Current (Off state) - 10 Jl.A IRQ CIN Input Capacitance - TA = 25°C, f = 1 MHz (RIW, R'£S, RSO,RS1, RS2, RS3, CS1, ~, - 7.0 pF 00-07, PAQ-PA7, CAl, CA2, PBo-PB7) (CB1, CB2) - 10 pF (<1>2 Input) - 20 pF COUT Output Capacitance - TA = 25°C, f = 1 MHz - 10 pF Po Power Dissipation (Vee = 5.25V) - 700 mW 120 Interfacing the BBeMicrocomputer

Synertek. SY6522/SY6522A

TestLoad OPEN COLLECTOR 5V OUTPUT TEST LOAD

5V

3Kn

PIN ----...----+-~I( ...----t----- PIN

C • 130 pF MAX. FOR DBG-DB7 C • 30 pF MAX, FOR ALL OTHER OUTPUTS -= Figure 2. Test Load (for all Dynamic Parameters)

cl>z CLOCK

CHIP SELECTS. REGISTER SELECTS, RtW

PERIPHERAL DATA

DATA BUS ------...... 1-<

Fig~re 3. Read Timing Characteristics

Read Timing Characteristics (Figure 3) SV6522 SV6522A Symbol Parameter Min. Max. Min. Max. Unit Tcy Cycle Time 1 50 0.5 50 IJS TACR Address Set-Up Time 180 - 90 - ns TCAR Address Hold Time ( 0 - 0 - ns TpCR Peripheral Data Set-Up Time 300 - 300 - ns TCDR Data Bus Delay Time - 340 - 200 ns THR Data Bus Hold Time 10 - 10 - ns

NOTE: tr, tf· 10 to 30ns. Appendix D: Data Sheets 121

~ynertek. SY6522/SY6522A

.------TCy-----~

<1>2 CLOCK

CHIP SELECTS. REGISTER SELECTS

RM

DATA BUS

PERIPHERAL DATA

Figure 4. Write Timing Characteristics

Write Timing Characteristics (Figure 4)

SV6522 SV6522A Symbol Parameter Min. Max. Min. Max. Unit TCY Cycle Time 1 50 0.50 50 JJ.s TC f/>2 Pulse Width 0.44 25 0.22 25 JJ.s TACW Address Set-Up Time 180 - 90 - ns TCAW Address Hold Time 0 - 0 - ns Twcw RIW Set-Up Time 180 - 90 - ns Tcww RIW Hold Time 0 - 0 - ns Tocw Data Bus Set-Up Time 300 - 150 - ns THW Data Bus Hold Time 10 - 10 - ns TCpw Peripheral Data Delay Time - 1.0 - 1.0 JJ.s TCMOS Peripheral Data Delay Time to CMOS Levels - 2.0 - 2.0 JJ.s

NOTE: tr, tf = 10 to 30n5. 122 Interfacing the BBeMicrocomputer

Synertek. SY6522/SY6522A

Peripheral Interface Characteristics

Symbol Characteri8tic Min. Max. Typ. Unit Figure tr,tf Rise and Fall Time for CA1, CB1, CA2, and CB2 - 1.0 ,.,.s - Input Signals TeAl Delay Time, Clock Negative Transition to CA2 - 1.0 ,.,.s 5a,5b Negative Transition (read handshake or pulse mode) TRS Delay Time, Clock Negative Transition to CA2 Positive - 1.0 ,.,.s 5a Transition (pulse mode)

TRS2 Delay Time, CA1 Active Transition to CA2 Positive - 2.0 ,.,.s 5b Transition (handshake mode) TwHS Delay Time, Clock Positive Transition to CA2 or CB2 0.05 1.0 ,.,.s 5c,5d Negative Transition (write handshake)

Tos Delay Time, Peripheral Data Valid to CB2 Negative 0.20 1.5 us 5c,5d Transition TRS3 Delay Time, Clock Transition to CA2 or CB2 - 1.0 ,.,.s 5c Positive Transition (pulse mode)

TRS4 Delay Time, CAlor CB1 Active Transition to CA2 or - 2.0 ,.,.s 5d CB2 Positive Transition (handshake mode)

T21 Delay Time Required from CA2 Output to CA1 400 - ns 5d Active Transition (handshake mode) Til Set-up Time, Peripheral Data Valid to CA1 or CB1 300 - ns 5e Active Transition (input latching)

TSR1 Shift-Out Delay Time - Time from cf>2 Falling Edge - 300 ns 5f to CB2 Data Out TSR2 Shift-In Setup Time - Time from CB2 Data in to 300 - ns 5g 4>2 Rising Edge

TSR3 External Shift Clock (CB1) Setup Time Relative to 100 Tcy ns 59 4>2 Trailing Edge

TIPW Pulse Width - PB6 Input Pulse 2 xTcy - 5i TICW Pulse Width - CB1 Input Clock 2 x TCY - 5h TIPS Pulse Spacing - PB6 Input Pulse 2 xTcy - 5i TICS Pulse Spacing - CB1 Input Pulse 2 xTCY - 5h TAL CA1, CB1 Set Up Prior to Transition to Arm Latch Tc +50 - ns 5e TpOH Peripheral Data Hold After CA1, CBl Transition 150 - ns 5e

TPWI Set Up Required on CA1, CB1, CA2 or CB2 Prior to TC + 50 - ns 5j Triggering Edge Shift Register Clock - Delay from 4>2 TOPR to CB1 Rising Edge 200 ns 5k TOPl to CB1 Falling Edge 125 ns 5k Appendix D: Data Sheets 123

~ynertek. SY6522/SY6522A

READ IRA OPERATION

CA2 "DATA TAKEN"

Figure Sa. CA2 Timing for Read Handshake, Pulse Mode

READ IRA OPERATION ,(

CAl "DATA TAKEN" ,(

TCA2

CAl >fT."f "DATA READY" ;':: LACTIVE TRANSITION Figure 5b. CA2 Timing for Read Handshake, Handshake Mode

WRITE ORA. ORB OPERATION

CA2.CB2 "DATA READY"

Figure 5c. CA2, CB2 Timing for Write Handshake, Pulse Mode 124 Interfacing the BBeMicrocomputer

Synertek. SY6522/SY6522A

WRITE ORA, ORB OPERATION

CA2, CB2 "DATA READY"

t-----TOS----.-I

PA,PB PERIPHERAL DATA

TRS4

CA1,CBl "DATA TAKEN" _____--r _ t5t_ ACTIVE ~ TRANSITION

Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode

PERIPHERAL ~ PA,PBINPUTDATA J< -ljL--l-POH'I ----

CA1,CBl INPUT LATCHING CONTROL

ACTIVE TRANSITION

Figure 5e. Peripheral Data Input Latching Timing

CB2 SHIFT DATA (OUTPUT) --

CBl SHIFT CLOCK (INPUT OR OUTPUT) ~, DELAVTIMEMEASURED FROMTHE FIRST -LFALLING EDGEMill CBl FALLING EDGE.

Figure 5f. Timing for Shift Out with Internal or External Shift Clocking Appendix D: Data Sheets 125

Synertek. SY6522/SY6522A

CB2 SHIFT DATA (INPUT)

CBl SHIFT CLOCK (INPUT OR OUTPUTI

SETUP TIME MEASUREDTO THE FIRST <1>2 RISING EDGE AFTER CBl RISING EDGE.

Figure 5g. Timing for Shift In with Internal or External Shift Clocking

CBl SHIFT CLOCK INPUT

Figure 5h. External Shift Clock Timing

PB6 PULSE COUNT INPUT

Figure 5i. PulseCount Input Timing

02 CB,I- 1 fC l}:---

Figure 5j. Setup Time to Triggering Edge Figure 5k. Shift-in/out with Internal Clock Delay C02 to CB1 Edge 126 Interfacing the BBeMicrocomputer

Svnertek.-- SY6522/SY6522A Pin Descriptions DBa-DB7 (Data Bus) m (Reset) The eight bi-directional data bus lines are used to The reset input clears all internal registers to logic 0 transfer data between the SY6522 and the system (except T1 and T2 latches and counters and the Shift processor. During read cycles, the contents of the sel­ Register). This places all peripheral interface lines in ected SY6522 register are placed on the data bus lines the input state, disables the timers, shift register, etc. and transferred into the processor. During write and disables interrupting from the chip. cycles, these lines are high-impedance inputs and data p2 (Input Clock) is transferred from the processor into the selected re­ gister. When the SY6522 is unselected, the data bus The input clock is the system <1>2 clock and is used to lines are high-impedance. trigger all data transfers between the system processor and the SY6522. CS1, ~ (Chip Selects)

Rfii(Read/Write) The two chip select inputs are normally connected to processor address lines either directly or through de­ The direction of the data transfers between the coding. The selected SY6522 register will be accessed SY6522.and the system processor is controlled by the ooen CS1 is high and CS2 is low. RiW line. If RM is low, data will be transferred out of the processor into the selected SY6522 register RSa- RS3 (Register Selects) (write operation). If RIW is high and the chip is select­ The four Register Select inputs permit the system pro­ ed, data will be transferred out of the SY6522 (read cessor to select one of the 16 internal registers of the operation). SY6522, as shown in Figure 6.

Register RS Coding Register Description Number RS3 RS2 RS1 RSO Desig. Write Read 0 0 0 0 0 ORB/IRB Output Register "B" Input Register "B" 1 0 0 0 1 ORA/IRA Output Register"A" Input Register "A" 2 0 0 1 0 DDRB Data Direction Register "B" 3 0 0 1 1 DORA Data Direction Register "A" 4 0 1 0 0 T1C-L Tl Low-Order Latches Tl Low-Order Counter 5 0 1 0 1 T1C-H T1 High-Order Counter 6 0 1 1 0 T1L-L T1 Low-Order Latches 7 0 1 1 1 T1L-H Tl High-Order Latches 8 1 0 0 0 T2C-L T2 Low-Order Latches T2 Low-Order Counter 9 1 0 0 1 T2C-H T2 High-Order Counter 10 1 0 1 0 SR Shift Register 11 1 0 1 1 ACR Auxil iary Control Register 12 1 1 0 0 PCR Peripheral Control Register 13 1 1 0 1 IFA Interrupt Flag Register 14 1 1 1 0 IER Interrupt Enable Register 15 1 1 1 1 ORA/IRA Same as Reg 1 Except No "Handshake"

Figure 6. SV6522 Internal Register Summary Appendix D: Data Sheets 127

..Svnertek. SY6522/SY6522A

fRO (I nterrupt Request) PA port. In addition, the PB7 output signal can be The Interrupt Request output goes low whenever an controlled by one of the interval timers while the internal interrupt flag is set and the corresponding in­ second timer can be programmed to count pulses terrupt enable bit is a logic 1. This output is "open­ on the PB6 pin. Peripheral B lines represent one drain" to allow the interrupt request signal to be standard TTL load in the input mode and will drive "wire-or'ed" with other equivalent signals in the one standard TTL load in the output mode. In addi­ system. tion, they are capable of sourcing 1.0mA at 1.5VDC in the output mode to allow the outputs to directly PAo-PA7 (Peripheral A Port) drive Darlington transistor circuits. Figure 8 is the The Peripheral A port consists of 8 lines which can circuit schematic. be individually programmed to act as inputs or out­ puts under control of a Data Direction Register. The CB1, CB2 (Peripheral B Control Lines) polarity of output pins is controlled by an Output The Peripheral B control lines act as interrupt inputs Register and input data may be latched into an in­ or as handshake outputs. As with CA1 and CA2, each ternal register under control of the CA1 line. All of line controls an interrupt fJag with a corresponding in­ these modes of operation are controlled by the sys­ terrupt enable bit. In addition, these lines act as a tem processor through the internal control registers. serial port under control of the Shift Register. These These lines represent one standard TTL load in the lines represent one standard TTL load in the input input mode and will drive one standard TTL load in mode and will drive one standard TTL load in the the output mode. Figure 7 illustrates the output output mode. Unlike PBQ-PB7, CB1 and CB2 £!!!!!Q! circuit. drive Darlington transistor circuits. CA1, CA2 (Peripheral A Control Lines) The two Peripheral A control lines act as interrupt in­ puts or as handshake outputs. Each line controls an internal interrupt flag with a corresponding interrupt enable bit. In addition, CA1 controls the latching of

data on Peripheral A port input lines. CA1 is a high­ INPUTI OUTPUT ---...... ----\ impedance input only; while CA2 represents one stan­ CONTROL dard TTL load in the input mode. CA2 will drive one

standard TTL load in the output mode. PBO-PB7. CB1.CB2

Figure 8. Peripheral B Port Output Circuit

PAO-PA7. CA2 FUNCTIONAL DESCRIPTION I I/O CONTROL D--1 Port A and Port B Operation OUTPUT DATA I I Each 8-bit peripheral port has a Data Direction Reg­ ister (DORA, DDRB) for specifying whether the peri­ pheral pins are to act as inputs or outputs. A 0 in a INPUT DATA ....------~ bit of the Data Direction Register causes the corres­ ponding peripheral pin to act as an input. A 1 causes Figure 7. Peripheral A Port Output Circuit the pin to act as an output. When programmed as an output each peripheral pin is also controlled by a correspond ing bit in the Out­ PBo-PB7 (Peripheral B Port) put Register (ORA, ORB). A 1 in the Output Regis­ The Peripheral B port consists of eight bi-directional ter causes the output to go high, and a "0" causes the lines wh ich are controlled by an output register and a output to go low. Data may be written into Output data direction register in much the same manner as the Register bits corresponding to pins which are pro- 128 Interfacing the BBeMicrocomputer

Svnertek.-- SY6522/SY6522A

grammed as inputs. In this case, however, the output REG 1 - ORA/IRA signal is unaffected. Reading a peripheral port causes the contents of the PAO Input Register (I RA, IRB) to be transferred onto the Data Bus. With input latching disabled, IRA will always PA2 reflect the levels on the PA pins. With input latching OUTPUT REGISTER "A" (ORAl enabled and the selected active transition on CA1 OR having occurred, IRA will contain the data present INPUT REGISTER "A" (lRAI on the PA lines at the time of the transition. Once ~------PA6 IRA is read, however, it will appear transparent, re­ flecting the current state of the PA lines until the Pin next "Iatching" transition. Ott. Direction WRITE READ S.lection The IRB register operates similar to the IRA register. DORA· "'" (OUTPUT I MPU writes Output Level MPUrttdll.velonPApin. (lnutlttchtnadisebltdl (ORAl. However, for pins programmed as outputs there is a DORA· "'" (OUTPUT I MPU r••h IRA bit which il (lnputlttchingentbltd) the 1...1of thtPA pin.t tht difference. When reading IRA, the level on the pin tirneofthtltItCA1.etiY. tr.nlition. determines whether a 0 or a 1 is sensed. When reading DORA· "0" (INPUT) MPU writes into ORA. but MPU,etdl'evelonPApin. (lnputl.tchinid'lIbltdl no tffect on pin lev.I,untll IRB, however, the bit stored in the output register, DDRAchtngtd. DORA· "0" (INPUT) MPU retdl I RA bit whIch is ORB, is the bit sensed. Thus, for outputs which have (Inputl.tching.nebledl thelev.lofth.PApinttth. tim.ofthel.ItCA1.ctive large loading effects and which pull an output "1" trtnlltlOn. down or which pull an output "0" up, reading IRA may result in reading a "0" when a "1" was actually Figure 10. Output Register A (ORA), programmed, and reading a "1" when a "0" was pro­ Input Register A (IRA) grammed. Reading IRB, on the other hand, will read the "1" or "0" level actually programmed, no matter REG 2 (DDRB) AND REG 3 (DORA) what the loading on the pin. Figures 9, 10, and 11 illusttate the formats of the port registers. In addition, the input latching modes are selected by the Auxiliary Control Register (Figure 16.) DATA DIRECTION REGISTER Handshake Control of Data Transfers "B" OR "A" (DDRB/DDRAI

The SY6522 allows positive control of data transfers L..- PB6/PA6

between the system processor and peripheral devices L..- PB7/PA7

ASSOCIATED PB/PA PIN IS AN INPUT REG 0 - ORB/IRB (HIGH·IMPEDANCE) ASSOCIATED PB/PA PIN IS AN OUTPUT, WHOSE LEVEL IS DETERMINED BY ORB/ORA REGISTER BIT

Figure 11. Data Direction Registers (DDRB, DORA)

PB2 throug, the operation of "handshake" lines. Port A OUTPUT REGISTER "B" (ORBI L..----PB3 lines (CA1, CA2) handshake data on both a read and OR L..-----PB4 a write operation while the Port B lines (CB1, CB2) INPUT REGISTER "B" (ORBI L..------PB5 handshake on a write operation only. L-...------PB6 Read Handshake Positive control of data transfers from peripheral de­ Pin vices into the system processor can be accomplished D.t.Direction WRITE READ S.lection very effectively using Read Handshaking. In this case, DDRB· "'" (OUTPUT) MPU writes Output L.vel M~Ur.tdloutPutrll9ilttrbit (ORB I inORB. Pin 1.".1 h.lno.ffect. the peripheral device must generate the equivalent of DDRB· "0" (INPUT) MPU writ .. into ORB, but MPU r.tdl input In.1 on PB (lnputl.tchingdiubltdl no tff.et on pin I.vel,until pin. a "Data Ready" signal to the processor signifying that DDRBcht"9td. DDRB· "0" (lNPUTI MPU r.tdslRB bit, which il valid data is present on the peripheral port. This signal (lnputl.tchingtn.bl.dl th.lev.lofth.PBpin.tth. tim.ofth.ltltCB,.etiY. normally interrupts the processor, which then reads tr.nlltion. the data, causing generation of a "Data Taken" signal. The peripheral device responds by making new data Figure 9. Output Register B (ORB), available. This process continues until the data trans­ Input Register B (lRB) fer is complete. Appendix D: Data Sheets 129

Synertek. SY6522/SY6522A

"DATA TAKEN" HANDSHAKE MODE ICA21

Figure 12. Read Handshake Timing (Port A, Only)

'1'2~~~

WRITE ORA, ORB II II OPERATION "DATA READY" ~------~1 HANDSHAKE MODE R= ICA.~~::: READY" -----ir I PULSE MODE ICA2,CB21 ~

;g:l~~;~KEN ------...... 1' 1'ZZZZZZZZZZZZ741 I 'iROOUTPUT I r- Figure 13. Write Handshake Timing

In the SY6522, automatic "Read" Handshaking is Timer Operation possible on the Peripheral A port only. The CAl in­ Interval Timer Tl consists of two a-bit latches and a terrupt input pin accepts the "Data Ready" signal 16-bit counter. The latches are used to store data and CA2 generates the "Data Taken" signal. The which is to be loaded into the counter. After loading, "Data Ready" signal will set an internal flag which the counter decrements at l/>2 clock rate. Upon reach­ may interrupt the processor or which may be polled ing zero, an interrupt flag will be set, and IRO will go under program control. The "Data Taken" signal can low if the interrupt is enabled. The timer will then either be a pulse or a level which is set low by the sys­ disable any further interrupts, or (when programmed tem processor and is cleared by the "Data Ready" to) will automatically transfer the contents of the signal. These options are shown in Figure 12 which latches into the counter and begin to decrement illustrates the normal Read Handshaking sequence. again. In addition, the timer may be programmed to invert the output signal on a peripheral pin each time Write Handshake it "times-out". Each of these modes is discussed sep­ arately below. The sequence of operations which allows handshaking data from the system processor to a peripheral device The Tl counter is depicted in Figure 15 and the is very similar to that described for Read Handshaking. latches in Figure 16. However, for Write Handshaking, the SY6522 gener­ ates the "Data Ready" signal and the peripheral de­ REG 12 - PERIPHERAL CONTROL REGISTER vice must respond with the "Data Taken" signal. This 1716151 41312101 can be accomplished on both the PA port and the C82CONTROL~ PB port on the SY6522. CA2 or CB2 act as a "Data CAl lNTERRUPT CONTROL O· NEGATIVE ACTIVE EDGE Ready" output in either the handshake mode or pulse o 0 0 INPUT·NEGATIVEACTIVE EDGE 1 • POSITIVE ACTIVE EDGE o 0 1 INDEPENDENT INTERRUPT mode and CAlor CBl accept the "Data Taken" sig­ INPUT·NEG EDGE D CA2CONTROL o 1 0 INPUT·POSITIVE ACTIVE EDGE nal from the peripheral device, setting the interrupt o 1 1 INDEPENDENT INTERRUPT o 0 0 INPUT·NEGATIVE ACTIVE EDGE INPUT.f'OS EDGE o 0 1 INDEPENDENT INTERRUPT flag and cleaning the "Data Ready" output. This INPUT·NEG EDGE sequence is shown in Figure 13. o 1 0 INPUT-POSITIVE ACTIVE EDGE o 1 1 INDEPENDENT INTERRUPT INPUT·POS EDGE Selection of operating modes for CAl, CA2, CB1, C811NTERRUPTCONTROL -

and CB2 is accompl ished by the Peripheral Control ~ : :~;~~~~EA~~~~~EE~El Register (Figure 14). 'SEE NOTE ACCOMPANYINGFIGURE 25 Figure 14. CA1, CA2, CB1, CB2 Control 130 Interfacing the BBeMicrocomputer

Svnertek... SY6522/SY6522A

Two bits are provided in the Auxiliary Control Reg­ ating modes. The four possible modes are depicted ister (bits 6 and 7) to allow selection of the Tl oper- in Figure 17.

REG 4 - TIMER 1 LOW-oRDER COUNTER REG 5 - TIMER 1 HIGH-ORDER COUNTER

COUNT COUNT VALUE VALUE ""'------16 '------4096 '------32 L...------8192 ------64 ""'------16384 ------128 '------32768

WRITE - 8 BITS LOADED INTO Tl LOW·ORDER WRITE - 8 BITS LOADED INTO Tl HIGH-ORDER LATCHES. LATCH CONTENTS ARE LATCHES. ALSO. AT THIS TIME BOTH TRANSFERRED INTO LOW-ORDER HIGH AND LOW-ORDER LATCHES COUNTER AT THE TIME THE HIGH· TRANSFERRED INTO T1 COUNTER. ORDER COUNTER IS LOADED (REG 51. AND INITIATES COUNTDOWN. T1 READ - 8 BITS FROM Tl LOW-ORDER COUNTER INTERRUPT FLAG ALSO IS RESET. TRANSFERRED TO MPU.IN ADDITION, READ - 8 BITS FROM Tl HIGH-ORDER COUNTER Tl INTERRUPT FLAG IS RESET (BIT 6 TRANSFERRED TO MPU. IN INTERRUPT FLAG REGISTER). Figure 15. Tl Counter Registers

REG 6 - TIMER 1 LOW-oRDER LATCHES REG 7 - TIMER 1 HIGH.QRDER LATCHES EEEEHill I~I~: L== 4096: COUNT COUNT VALUE '------16 ~ VALUE ""'------32 8192 '------64 ""'------16384 '------128 '------32768

WRITE -8 BITS LOADED INTO TlLOW-ORDER WRITE - 8 BITS LOADED INTO T1 HIGH·ORDER LATCHES. THIS OPERATION IS NO LATCHES. UNLIKE REG 4 OPERATION DIFFERENT THAT A WRITE INTO NO LATCH·To-COUNTER TRANSFERS REG4. TAKE PLACE. READ - 8 BITS FROM T1 LOW-ORDER LATCHES READ - 8 BITS FROM T1 HIGH·ORDER LATCHES TRANSFERRED TO MPU. UNLIKE REG 4 TRANSFERRED TO MPU. OPERATION, THIS DOES NOT CAUSE RESET OF T1 INTERRUPT FLAG. Figure 16. Tl Latch Registers

REG 11 - AUXILIARY CONTROL REGISTER

T1 TIMER CONTROL 76 oPERATION PB7 o 0 TIMED INTERRUPT EACH TIME T1 IS LOADED DISABLED 01 CONTINUOUS INTERRUPTS 1 0 TIMED INTERRUPT ONE·SHOT EACH TIME T1 IS OUTPUT LOADED 1 1 CONTINUOUS SOUARE INTERRUPTS WAVE OUTPUT

Figure 17. Auxiliary Control Register

Note: The processor does not write directly into the low order counter (T1C-L). Instead, this half of the counter is loaded auto­ matically from the low order latch when the processor writes into the high order counter. In fact, it may not be necessary to write to the low order counter in some applications since the timing operation is triggered by writing to the high order counter. Appendix D: Data Sheets 131

Synertek. SY6522/SY6522A

<1'2

WRITE TlC·H W oPERATION -----' I~ -----~r)------+------If'

,j' iliOOUTPUT I Pe7 OUTPUT IT1,ONlY) ,','

T1 COUNT N-2 N-J FFFF N-1 N-2

T2 COUNT N-1 N-2 N-3 FFFF FFFE FFFD FFFC .1

Figure 18. Timer 1 and Timer 2 One-Shot Mode Timing

Timer lOne-Shot Mode In the free-running mode, the interrupt flag is set and the signal on PB7 is inverted each time the counter The interval timer one-shot mode allows generation reaches zero. However, instead of continuing to decre­ of a single interrupt for each Timer load operation. ment from zero after a time-out, the timer automati­ In addition, Timer 1 can be programmed to produce cally transfers the contents of the latch into the a single negative pulse on PB7. counter (16 bits) and continues to decrement from To generate a single interrupt ACR bits 6 and 7 must there. It is not necessary to rewrite the timer to en­ be 0 then either TI L-L or TIC-L must be written with able setting the interrupt flag on the next time-out. the low-order count value. (A write to TIC-L is effec­ The interrupt flag can be cleared by reading TIC-L, tively a Write to TI L-L). Next the high-order count by writing directly into the flag as described later, value is written to TIC-H, (the value is simultan­ or if a new count value is desired by a write to TICH. eously written into TI L-H), and TI L-L is transferred to TIC-L. Countdown begins on the 4>2 following the All interval timers in the SY6522 are "re-triggerable". write TIC-H and decrements at the 4>2 rate. Tl inter­ Rewriting the counter will always re-initialize the rupt occurs when the counters reach O. Generation time-out period. In fact, the time-out can be prevent­ of a negative pulse on PB7 is done in the same manner ed completely if the processor continues to rewrite except ACR bit 7 must be a one. PB7 will go low the timer before it reaches zero. Timer 1 will operate after a Write TIC-H and go high again when the in this manner if the processor writes into the high counters reach O. order counter (T1C-H). However, by loading the latches only, the processor can access the timer dur­ The Tl interrupt flag is reset by either writing TIC-H ing each down-counting operation without affecting (starting a new count) or by reading TIC-L. the time-out in process. Instead, the data loaded into Timing for the one-shot mode is illustrated in the latches will determine the length of the next time­ Figure 18. out period. This capability is particularly valuable in the free-running mode with the output enabled. In Timer 1 Free-Run Mode this mode, the signal on PB7 is inverted and the in­ The most important advantage associated with the terrupt flag is set with each time-out. By responding latches in Tl is the ability to produce a continuous to the interrupts with new data for the latches, the series of evenly spaced interrupts and the ability to processor can determine the period of the next half produce a square wave on PB7 whose frequency is cycle during each half cycle of the output signal on not affected by variations in the processor interrupt PB7. In this manner, very complex waveforms can be response time. This is accomplished in the "free­ generated. Timing for the free-running mode is shown running" mode. in Figure 19. 132 Interfacing the BBC Microcomputer

Synertek. SY6522/SY6522A

11'2 JL...fl.-JL..y ~

WA'TET'CH --r-L-... I I :A:~::T ~:: I II'.. _

P87 OUTPUT -----,'------f,~' _ ,','

I------N + 1.5 CYCLES--_.1·.....----N+ 2 CYCLES-----.-4.1

Note: A. precaution to take in the UI8 of PB7 II the timer output concernl the Dlte Direction Register contentl for PB7. Both DDRB bit 7 and ACR bit 7 must be 1 for PB7 to function II the timer output. If either ill 0, then PB7 functionl III normal output pin, controlled by ORB bit 7.

Figure 19. Timer 1 Free-Run Mode Timing

Timer 2 Operation Timer 2 One-Shot Mode Timer 2 operates as an interval timer (in the "one­ As an interval timer, T2 operates in the "one-shot" slot" mode only), or as a counter for counting neg. mode similar to Timer 1. In this mode, T2 provides a tive pulses on the PB6 peripheral pin. A single con­ single interrupt for each "write T2C-H" operation. trol bit is provided in the Auxiliary Control Register After timing out, (reading 0) the counters "roll-over" to select between these two modes. This timer is com­ to all l's (FFFF16) and continue decrementing, al­ prised of a "write-only" low-order latch (T2 L-L), a lowing the user to read them and determine how long "read-only" low-order counter and a read/write high T2 interrupt has been set. However, setting of the order counter. The counter registers act as a l6-bit interrupt flag will be disabled after initial time-out counter which decrements at ~2 rate. Figure 20 illus­ so that it will not be set by the counter continuing to trates the T2 Counter Registers. decrement through zero. The processor must rewrite T2C-H to enable setting of the interrupt fill. The interrupt flag is cleared by reading T2CL or by writing T2CH. Timing for this operation is shown in Figure 18.

REG 8 - TIMER 2 LOW-QRDER COUNTER REG 9 - TIMER 2 HIGH-QRDER COUNTER

2M

512

1024

COUNT 2041 COUNT VALUE VALUE '------1. 40H ...... -----32 .182 ------84 11314 ------121 327.

WRITE - 8 BITS LOADED INTO T2 LOW-oRDER WRITE - • IITS LOADED INTO T2 HIGH-oRDER LATCHES. COUNTER. ALSO. LOW-oRDEA LATCHES 8 BITS FROM T2 LOW-oRDER COUNTER TRANSFERRED TO LOW-oRDER TRANSFERRED TO MPU. T2 INTERRUPT COUNTER. IN ADDITION. 12 INTERRUPT FLAG IS RESET. FLAG II RESET. READ - • IITS fROM 12 HIGH·ORDER COUNTER TRANSfEARED TO MPU.

Figure 20. T2 Counter Registers Appendix D: Data Sheets 133

-Svnertek. SY6522/SY6522A Timer 2 Pulse Counting Mode Interrupt Operation In the pulse counting mode, T2 serves primarily to Controlling interrupts within the SY6522 involves count a precietermined number of negative-going three principal operations. These are flagging the in­ pulses on PBG. This is accomplished by first loading terrupts, enabling interrupts and signaling to the pro­ a number into T2. Writing into T2C-H clears the in­ cessor that an active interrupt exists within the chip. terrupt flag and allows the counter to decrement each Interrupt flags are set by interrupting conditions time a pulse is applied to PBG. The interrupt flag will which exist within the chip or on inputs to the chip. be set when T2 reaches zero. At this time the counter These flags normally remain set until the interrupt will continue to decrement with each pulse on PBG. has been serviced. To determine the source of an in­ However, it is necessary to rewrite T2C-H to allow terrupt, the microprocessor must examine these flags the interrupt flag to set on subsequent down-counting in order from highest to lowest priority. This is ac­ operations. Timing for this mode is shown in Figure complished by reading the flag register into the pro­ 21. The pulse must be low on the leading edge of <1>2. cessor accumulator, shifting this register either right or left and then using conditional branch instructions to detect an active interrupt. Shift Register Operation Associated with each interrupt flag is an interrupt The Shift Register (SR) performs serial data transfers enable bit. This can be set or cleared by the proces­ into and out of the CB2 pin under control of an in­ sor to enable interrupting the processor from the cor­ ternal rnodulo-B counter. Shift pulses can be applied responding interrupt flag. If an interrupt flag is set to to the CB1 pin from an external source or, with the a logic 1 by an interrupting condition, and the corres­ proper mode selection, shift pulses generated inter­ ponding interrupt enable bit is set to a 1, the Inter­ nally will appear on the CB1 pin for controlling ex­ rupt Request Output (IRQ) will go low. IRQ is an ternal devices. "open-collector" output which can be " wire-or'ed" The control bits which select the various shift register with other devices in the system to interrupt the operating modes are located in the Auxiliary Control processor. Register. Figure 22 illustrates the configuration of the In the SY6522, all the interrupt flags are contained SR data bits and the SR control bits of the ACR. in one register. In addition, bit 7 of this register will Figures 23 and 24 illustrate the operation of the vari­ be read as a logic 1 when an interrupt exists within ous shift register modes. the chip. This allows very convenient polling of sev­ eral devices within a system to locate the source of an interrupt.

~:~~~i,~: ---fI _ '~

iRa OUTPUT I I II Figure 21. Timer 2 Pulse Counting Mode

REG 10 - SHIFT REGISTER REG 11 - AUXILIARY CONTROL REGISTER ~ ~

SHIFT SHIFTREGISTER REGISTER L MODE CONTROL BITS

OPERATION DISABLED SHIFT IN UNDER CONTROL OF T2 SHIFT IN UNDER CONTROL OF -I' SHIFT IN UNDER CONTROL OF EXT CLK NOTES: 1. WHEN SHIFTII\IG OUT. BIT 7 IS THE FIRST BIT SHIFT OUT FREE·RUNNING AT T2 RATE OUT AND SIMUL T'ANEOUSLY IS ROTATED BACK SHIFT OUT UNDER CONTROL OF 12 INTO BITO. SHIFT OUT UNDER CONTROL OF '1'2 2. WHEN SHI FTING IN. BITS INITIALLY ENTER BIT 0 AND ARE SHTFTED TOWARDS BIT 7. SHIFT OUT UNDER CONTROL OF EXT CLK

Figure 22. SR and ACR Control Bits 134 Interfacing the BBeMicrocomputer

..Svnertek. SY6522/SY6522A

SR Disabled (000) The 000 mode is used to disable the Shift Register. In this mode the microprocessor can write or read the SR, but the shifting operation is disabled and operation of CB1 and CB2 is controlled by the appropriate bits in the Peripheral Control Register (PCR). In this mode the SR Interrupt Flag is disabled (held to a logic 0).

Shift in Under Control of T2 (001) In the 001 mode the shifting rate is controlled by the low order 8 bits of T2. Shift pulses are generated on the CBl pin to control shifting in external devices. The time between transitions of this output clock is a function of the system clock period and the contents of the low order T2 latch (N). The shifting operation is triggered by writing or reading the shift register. Data is shifted first into the low order bit of SR and is then shifted into the next higher order bit of the shift register on the negative-going edge of each clock pulse. The input data should change before the positive-going edge of the CBl clock pulse. This data is shifted into the shift register during the f/>2 clock cycle following the positive-going edge of the CBl clock pulse. After 8 CBl clock pulses, the shift register interrupt flag will be set and IRQ will go low.

-1>2

WRITE OR READ SHIFT REG. ct ~~~LES ------N+2 CYCLES...... / SHIFT CLOCK 8 g~~ ~NPUT 1I$ffff//l!ff(ff(ff(ffff((fffffff(A I

Shift in Under Control of f/>2 (010) In mode 010 the shift rate is a direct function of the system clock frequency. CBl becomes an output which generates shift pulses for controlling external devices. Timer 2 operates as an independent interval timer and has no effect on SA. The shifting operation is triggered by reading or writing the Shift Register. Data is shifted first into bit 0 and is then shifted into the next higher order bit of the shift register on the trailing edge of each f/>2 clock pulse. After 8 clock pulses, the shift register interrupt flag will be set, and the output clock pulses on CBl will stop.

-1'2

g~~~NPUT W//ffffff$ff//ffff/ff$/ff/ffff@ff& iRii 1... _

Shift in Under Control of External CB1 Clock (011) In mode 011 CBl becomes an input. This allows an external device to load the shift register at its own pace. The shift register counter will interrupt the processor each time 8 bits have been shifted in. However, the shift register counter does not stop the shifting operation; it acts simply as a pulse counter. Reading or writing the Shift Register resets the Interrupt flag and initializes the SR counter to count another 8 pulses. Note that the data is shifted during the first system clock cycle following the positive-going edge of the CB1 shift pulse. For this reason, data must be held stable during the first full cycle following CBl going high.

Figure 23. Shift Register Input Modes Appendix D: Data Sheets 135

Svnertek... SY6522/SY6522A

Shift Out Free-Running at T2 Rate (100) Mode 100 is very similar to mode 101 in which the shifting rate is set by T2. However, in mode 100 the SR Counter does not stop the shifting operation. Since the Shift Register bit 7 (SR7) is recirculated back into bit 0, the 8 bits loaded into the shift register will be clocked onto CR2 repetitively. In this mode the shift register counter is disabled, and IRQ is never set. '1'2 .nnnruUUlfUlJUUU1IlJnnnnnIUUUUlMJlfUllIUUlJUUlflIlfUUUUUl WRITESR~1 I OPERATION - .....--+----+-...... -----I-~~----- N'2 CYCLES N'2 CYCLES

CB10UTPUT 2 SHIFT CLOCK

CB20UTPUT DATA

Shift Out Under Control of T2 (101) In mode 101 the shift rate is controlled by T2 (as in the previous mode). However, with each read or write of the shift register the SR Counter is reset and 8 bits are shifted onto CB2. At the same time, 8 shift pulses are generated on CBl to control shifting in external devices. After the 8 shift pulses, the shifting is disabled, the SR Interrupt Flag is set and CB2 remains at the last data level.

·1- 2 CLOCK

WRITE SR OPERATION

CB10UTPUT SHIFT CLOCK

g~~~UTPUT_ x'- x ~

Shift Out Under Control of <1>2 (110) In mode 110, the shift rate is controlled by the <1>2 system clock.

-/-2 CLOCK

WRITE SR OPERATION

CB10UTPUT SHIfT CLOCK

CB2 OUTPUT DATA

Shift Out Under Control of External CB1 Clock (111) In mode 111 shifting is controlled by pulses applied to the CBl pin by an external device. The SR counter sets the SR Interrupt flag each time it counts 8 pulses but it does not disable the shifting function. Each time the microprocessor writes or reads the shift register, the SR Interrupt flag is reset and the SR counter is initialized to baqin counting the next 8 shift pulses on pin CB1. After 8 shift pulses, the interrupt flag is set. The microprocessor can then load the shift register with the next byte of data.

-1'2

WRITE SR OPERATION

CBllNPUT I 1 I 'H"'CLOCK _~ g~~~UTPUT ~.... '- -/

Figure 24. Shift Register Output Modes 136 Interfacing the BBeMicrocomputer

Svnertek... SY6522/SY6522A

The Interrupt Flag Register (IFR) and Interrupt En­ by writing to address 1110 (IER address). If bit 7 of able Register (IER) are depicted in Figures 25 and the data placed on the system data bus during this 26, respectively. write operation is a 0, each 1 in bits 6 through 0 The IFR may be read directly by the processor. In ad­ clears the corresponding bit in the Interrupt Enable dition, individual flag bits may be cleared by writing Register. For each zero in bits 6 through 0, the cor­ a "1" into the appropriate bit of the IFR. When the responding bit is unaffected. proper chip select and register signals are applied to Setting selected bits in the Interrupt Enable Register the chip, the contents of this register are placed on is accomplished by writing to the same address with the data bus. Bit 7 indicates the status of the IRQ out­ bit 7 in the data word set to a logic 1. In this case, put. This bit corresponds to the logic function: IRQ = each 1 in bits 6 through 0 will set the corresponding IFR6xIER6+IFR5x IER5+IFR4x IER4+ IFR3x bit. For each zero, the corresponding bit will be un­ IER3 +.IFR2 x IER2 + IFRl x IER1 + IFRO x IERO. affected. This individual control of the setting and Note: X = logic AND, + = Logic OR. clearing operations allows very convenient control of the interrupts during system operation. The IF R bit 7 is not a flag. Therefore. th is bit is not directly cleared by writing a logic 1 into it. It can In addition to setting and clearing IE R bits, the pro­ only be cleared by clearing all the flags in the register cessor can read the contents of this register by placing or by disabling all the active interrupts as discussed the proper address on the register select and chip in the next section. select inputs with the R/W line high. Bit 7 will be read as a logic 1. REG 13 - INTERRUPT FLAG REGISTER REG 14 - INTERRUPT ENABLE REGISTER

SET BY CLEARED BY CAl ACTIVE EDGE READ OR WRITE REG 1 (ORA'· CA' ACTIVE EDGE READ OR WRITE REG 1 ORA COMPLETE 8 SHIFTS READ OR WRITE SHIFT REG CB2 CB2 ACTIVE EDGE READ OR WRITE ORB· CB1 1 V 0"' INTERRUPT DISABLED TIMER 2 TIME·OUT OF T2 READ T2 LOW OR WRITE T2 HIGH L...------CB' 1" INTERRUPT ENABLED TIME·OUT OF T1 READ T1 LOW OR TIMER 1 WRITE T1 HIGH L..------TIMER2 IRQ ANY ENABLED CLEAR ALL INTERRUPT INTERRUPTS

~------SET/CLEAR • IF THE CA2/CB2 CONTROL IN THE PCR IS SELECTED AS "INDEPENDENT" INTERRUPT INPUT, THEN READING OR NOTES: WRITING THE OUTPUT REGISTER ORA/ORB WILL NOT 1. IF BIT 7 IS A "0", THEN EACH "1" IN BITS 0 - 6 DISABLES THE CLEAR THE FLAG BIT. INSTEAD, THE BIT MUST BE CORRESPONDING INTERRUPT. CLEARED BY WRITING INTO THE IFR, AS DESCRIBED 2. IF BIT 7 IS A "1", THEN EACH "1" IN BITS 0 - 6 ENABLES THE PREVIOUSL Y. CORRESPONDING INTERRUPT. 3, IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE "'" AND Figure 25. Interrupt Flag Register (I FR) ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.

Figure 26. Interrupt Enable Register (lER) For each interrupt flag in !FR, there is a corres­ ponding bit in the Interrupt Enable Register. The system processor can set or clear selected bits in this register to facilitate controlling individual inter­ rupts without affecting others. This is accomplished Appendix D: Data Sheets 137

..Svnertek. SY6522/SY6522A

Pin Configuration

CA2 RSO

RSl

RS2

RES

CSl C52 RM

Package Availability 40 Pin Plastic 40 Pin Ceramic

Ordering Information

Order Package Frequency Number Type Option Syp 6522 Plastic 1 MHz SYP 6522A Plastic 2 MHz SYC 6522 Ceramic 1 MHz SYC 6522A Ceramic 2 MHz 138 Interfacing the BBeMicrocomputer ttiEC NEe Microcomputers, Inc. It'- PD7002

12-BIT BINARY AID CONVERTER

DESCRIPTION The ~PD7002 is a high performance, low power, monolithic CMOS AID converter designed for microprocessor applications. The analog input voltage is applied to one of the four analog inputs. By loading the input register with the multiplexer channel and the desired resolution (8 or 10 bits) the integrating AID conversion sequence is started. At the end of conversion EOC signal goes low and if connected to the inter­ rupt line of microprocessor it will cause an interrupt. At this point the digital data can be read in two bytes from the output registers. The ~PD7002 also features a status register that can be read at any time.

FEATURES • Single Chip CMOS LSI • Resolution: 8 or 10 Bits • 4 Channel Analog Multiplexer • Auto-Zeroscale and Auto-Fullscale Corrections without any External Components • High Input Impedance: l000Mn • Readout of Internal Status Register Through Data Bus • Single +5V Power Supply • Interfaces to Most 8-Bit Microprocessors • Conversion Speed: 5 ms • Power Consumption: 20 mW • Available in a 28 Pin Plastic Package

PIN CONFIGURATION Xo EOC PIN NAMES

XI A1 XO,XI External Clock Input Vss AO VSS TTL Ground CI Ri5 CI Integrating Capacitor GO WR GO Guard CI cs VREF Reference Voltage Input GNO Analog Ground GO DO CH3 Analog Channel 3 VREF 01 CH2 Analog Channel 2 GNO 02 CH1 Analog Channel 1 CH3 03 CHO Analog Channel 0 CH2 04 TTL Voltage (+SV) CH1 05 VOO 07 Data Bus CHO 06 00- CS Chip Select VOO 07 WR,RD Control Bus

AO,A1 Address Bus EOC End of Conversion Interrupt Appendix D: Data Sheets 139

I£PD7002 BLOCK DIAGRAM H 2 3

AID ANALOG SECTION INTEGRATING CAPACITOR

ANALOG GNO

AID DIGITAL SECTION

'.ISS

I r

Ta = 25! 2"C VOO = ..-5 ! 025V VREF = +2.50V 'CK = 1 MHz DC CHARACTERISTICS

LIMITS TEST PARAMETER SYMBOL UNIT MIN TYP MAX CONDITIONS Resolution 12 Bits VOO = 5V. VREF .. 2.5 ! 0.25V Non Linearity 0.05 0.08 %FSR VOO" 5V. VREF .. 2.5 ! 0.25V Fullscale Error 0.05 0.08 %FSR VOO ~ 5V. VREF =2.5' 0.25V Zeroscale Error 0.05 0.08 %FSR VOO = 5V. VREF = 2.5 ! 0.25V Fullscale Temperature Coeff icrent 10 PPMfc VOO = 5V Zeroscale Temperature Coefficient 10 PPMtC VOO = 5V Analog Input Voltage Range VIA 0 VREF V Analog Input Resistance RIA 1000 Mn VIA = VSS to VOO Total Unadjusted Error 1 T.U.E.1 0.05 0.08 %FSR VREF = 2.25 to 2.75V. VOO =5V Total UnadJusted Error 2 T.U.E.2 0.05 0.08 %FSR VREF - 2.5V. VOO =4.75 to 5.25V Clock Input Current IXI 5 50 IJA Clock Input High Level VXIH VOO-1.4 V Clock Input Low Level VXIL VSS+1.4 V High Level Input Voltage V,H 2.2 VTa=-20 Cto+70 C Low Level Input Voltage -. 0.8 V T -20°C to +70°C VIL a = High Level Output Voltage VOH 3.5 V 10 =-1.6mA Ta = -20°C to +70°C Low Level Output Voltage VOL 0.4 V 10 = +16mA Ta =-20°C to +70°C Digital Input Leakage Current II 1 10 IJA VI" VSS to VOO High-Z Output Leakage Current I Leak 1 10 IJA vo" VSS to VOO Power Dissipation Pd 15 25 mW fCK'" 1 MHz 140 Interfacing the BBeMicrocomputer

,.,.PD7002 ABSOLUTE MAXIMUM Operating Temperature -20°C to +70°C RATINGS* Storage Temperature -65°C to +125°C All Input Voltages -0.3 to VDO + 0.3 Volts Power Supply - 0.3 to +7 Volts Power Dissipation 300 mW Analog GNO Voltage...... VSS ± 0.3 Volts COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. *Ta = 2SoC

AC CHARACTERISTICS Ta " 25° :t 2°C; VDD = +5 :t 0.25V; VREF =2.5V; fCK ::: 1 MHz; CINT::: 0.033 IlF

LIMITS TEST PARAMETER SYMBOL UNIT MIN TYP MAX CONDITIONS

Conversion Speed (12 bit) tCONV 8.5 10 15 ms fCK = 1 MHz Conversion Speed (8 bit) tCONV 2.4 4 5 ms fCK =1 MHz Clock Frequency Range fCK 0.1 1 3 MHz Integrating Capacitor Value CINT* 0.029 IlF VREF =2.50V. fCK = 1 MHz Address Setup Time tAW 50 ns CSt AO, A1, to WR Address Setup Time tAR 50 ns CS, AO, A1, to R15 Address Hold Time WR to tWA 50 ns CS, AO, A1 Address Hold Time RD to tRA 50 ns CS, AO, A1 Low Level WR Pulse Width tww 400 ns Low Level R 0 Pulse Width tRR 400 ns Data Setup Time Input tow 300 ns Data to WA Data Hold Time WR to two 50 ns Input Data Output Delay Time RD to tRD 300 ns 1TTL + 100 pF Output Data Delay Time to High Z tDF 150 ns Output ADto Floating Output

TIMING WAVEFORMS cs AO.A1

tV(N WR

tow

07- 0 0

CS AO.A1 tRR RO

07- 0 0 Appendix D: Data Sheets 141

IJ-PD7002

CONTROL TERMINALS CONTROL TERMINAL INTERNAL DATA INPUT·OUTPUT CS RD WR A1 Ao MODE FUNCTION TERMINALS FUNCTIONS H x x x x Not selected High impedance L HH x x Not selected - L H L LL Write mode Data latch Input status. 01. DO· MPX addrlSl AID start 03· 8 bit/12 bit conversion designation.

Not ..: CD Designation of number of conversion bits: 8 bit • L; 12 bit· H @ Test Mode: Used for inspecting the device. The data inputo()utput terminals assumean input state and are connected to the AID counter. Therefore. the AID conversion cMta read out after this is meaningless.

PACKAGE OUTLINE p.PD7002C

(PLASTIC) ITEM MILLIMETERS INCHES A 38.0 MAX. 1.496 MAX. 8 2.49 0.098 C 2.54 0.10 o 0.5 ~ 0.1 0.02 ~ 0.0()4 E 33.02 1.3 F i.s 0.059 G 2.54 MIN. 0.10MIN. H O.SMIN. 0.02 MIN. I 5.22 MAX. 0.205 MAX. J S.72 MAX. 0.22SMAX. K lS.24 0.6 L 13.2 0.52

M 0.25 ~ ~:~ 0.01 ~~:: 142 Interfacing the BBeMicrocomputer

TYPES SN54LS240,SN54LS241,SN54LS244,SN54S240,SN54S241, SN74LS240,SN74LS241,SN74LS244,SN74S240,SN74S241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

Typical Typecal Typical Pr~tion Typic81 Typical PCWNr IOl IOH Oea.y Times EMbieI Dissipetion (Sink (Sourn Disable (Erwbled) Current) CurrentJ 'nwwting Nonimerting Timea Irwertine Noninwertine SN54LS' 12mA -12mA 10.5n5 12 ns 18 ns 130 mW 135 mW SN74LS' 24mA -15mA 10.5 ns 12 ns 18 ns 130 mW 135 mW SN54S' 48mA -12mA 4.5 ns 6 ns 9 ns 450 mW 538 mW SN74S' 64mA -15mA ~.5 ns 6ns 9 ns 450 mW 538 mW SN54LS240, SN54S240 ••• J • 3-8tate Outputs Drive Bus Lines SN74lS240, SN74S240 .•• J OR N or Buffer Memory Address Registen (TOPVIEWJ • P-N-P Inputs Reduce DeC Loading • Hysteresis at Inputs Improves Noise Margins description These octal buffers and line drivers are designed specifically to improve both the performance and deniity of three-state memory address drivers, clock drivers. and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and non inverting outputs, symmetrical C (active-Jow output control) inputs, and comple­ mentary G and G inputs. These devices featu:-e high SN54LS241. SNS4S241 ••• J fan-out, improved fan-in. and 400-mV noise-margin. SN74LS241, SN74S241 •.• J OR N (TOP VIEW) The SN74lS' and SN74S' can be used to drive terminated tines down to 133 ohms. schematics of inputs and outputs 'LS240, 'lS241, 'L$24.4 EQUIVALENT OF TYPICAL OF All EACH INPUT OUTPUTS

VCC----

INPUT

SNS4LS244 .•• J SN74lS24.4 •.. J OR N (TOP VIEW)

EQUIVALENT OF EACH INPUT

VCC --- h INPUTW-- 'LS240, 'LS241, ·LS244; R -500 NOM '5240. '5241: R -250 NOM Appendix D: Data Sheets 143

TYPES SN64LS240.SN54LS241,SN64LS244, SN74LS240,SN74LS241,SN74LS244 BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

recommended operating conditionl

SNMLS· 1N74LI· 'ARAMETtR UN.T MIN NOM MAX MIN NOM MAX S",p~ly YOlltee. Vee (1M NOli 11 4.6 6 6.6 4.76 6 6.25 V Hlyh·l.vel output curr.nt, 'OH -12 -16 rnA L~·lh.1 output CUH.nt. 'Ol 12 24 rnA Qp.'.lIng fr••·." tlmp.,atu. I. T A -66 126 0 70 ·C

NOTt. 1: "oil. valu" a" with ,.,,'1'1 10 n.two,'" lI'O'.Ind tetmlnal. elttetrical charact.riitici over recornmended operating fr...ir tIImperatur. range (unll.. oth.rwi. noUld) SNWLS' SN74LS· PARAMETER TUT COHDITlON&t UNIT MIN TYP~ MAX MIN TYP* MAX VIH Hlgh·h,vel Inpyt \tollage 2 2 V V'L low·l.vel Input vollage 0.7 0.8 V v« Input cl~mp voltag.t vee> MIN, 'I· -18mA -1.5 -1.6 V HyU.r.III tVT .. - VT-) 1Vee· MIN 0.2 0.4 0.2 0.4 V Vec - MIN, VH- 2 V, 2.4 3.4 2.4. 3.4 VIL • Vil max. 'OH - -3 rnA VOH Hlgh-j.vel output volLage V Vec· MIN, V'H· 2V, 2 2 Vil - 0.5 V. 'OH - MAX Vec - MIN, 'OL - 12 mA 0.4 0.4 VOL lo.ltll-j.veloutput vol t.~ VIH-2V, V 0,6 V'l • VllIN. IOL - 24 mA Off·It.1I output current, Va· 2.1 V 20 'OlH hlgh·level voltage Ipplled Vee - MAX, 20 Off·nl" output current. V'H - 2 V, IAA lOll 10w·I."., "oltagtl Ipplu,d Val - VILmiX vo -0.4 V -20 -20 'nput current ,t mexlmum II MAX, Input VOlt.... vee- V,· 7 V 0.1 0.1 mA 'IH High-iewl Input currlnt, any Input Vee - MAX, V, - 2.7 V 20 20 ~A III lOW·lltvl' Input currlnt Vee - MAX. Vll • 0.4 V -0.2 -0.2 mA lOS ShOll-Clrcult outpul currenl. Vee - MAX 40 -225 -40 -226 mA OUlPUIl hll.lh All 17 27 17 21 Vec· MAX 'lS240 26 44 26 44 OutpUll low mA tec Supply curr.nt 'LS241 'LS244 27 46 27 46 OutPUll open All oulputl 'LS240 29 50 29 60 d, ••ul.d 'lS241. 'LS244 32 64 32 604 t For cOndlliOftllftown • MIN or MAX. UN "'. epp'oP,la'. valw. IPKlf.ed u~ recommended oP.,.llne condition.. uC. tAli tYPICal v..... " .... at Vee • I V, T A • 20 'Nol mo,. "'In on. oulI»"I Ihould be eho"ed .' • lime. end dur.t.Oft of "'. lhor1-clreuI1Iho"ld not poNd Oftl MCond, Iwitching charactariitici. Vee • 6 V, TA • 26~ C

'LS240 'LS241 'LS2" PARAMETER TEST CONDITIONS UNIT MIN TVP MAX MIN TVP MAX P'~tlon del.y 1I11l4t. 9 14 12 18 IPlH low-to·hlgh·level output .. P,op.tlon del.y tim". CL - 45 pF. RL - 661 n, It'HL 12 18 12 18 hlgtHO·low·I.~1 Output .. IPZL OutPut .nlbl. time to low 'evel 20 JO 20 30 ,. IPZH Output .n.bt, tim. to hlyh I~vcl 16 23 15 23 nl tPtZ OUIPut d" ..bht tam. from low h'vttl Cl-5pF, Rl- 667 n, 16 25 15 25 m IPHl OutPut dtiilbl. t,me from hl\fh I.~I 10 18 10 18 nl 144 Interfacing the BBeMicrocomputer TYPES SNi4S24a. 51&45241, 11741241, 11741241 BUffERS/LINE DRIVERS/LINE RECEIVERS WITH 3·Sl'ATE OUTPUTS fWCOmmended operlting conditions SN64&- IN1.- PARAMETER UNIT MIN NOM MAX MIN NOM MAX Supply vol&age, Vee (Me Not. 1) 4.6 & 6.5 4.7& 6 6.25 V H,gh·,ev.' Oulpul cu".nt. IOH -12 -16 m~ Low-Iewl output currlnt. 'OL 48 b4 m~ 1)pel.t,ng f,••·." IlmPer.tur.,'A (a. No.. 3) -66 125 0 70 -'c NOli'. 1. Voflege v"u.. .,. whh 'elPKt 10 n.twork jlound lerm'n". 3. An SNr.482.U op"ellnt •• " ....,r temp.r.l"r. aI»Ove 1,.·C '"'1""' he.' ••"k .". prow•••• m"",_ .....Iance from c.... " ....t" "'CA, of n~t more then .OUCIW. electrical characteriltics over recommended oper.ting free-air wnperatur. range (una..o1herwi.. noIM)

-'240 ..241 'ARAMETER TUT CONDITIOHIt UNIT MIN Ty,l MAX MIN n,1 MAX V,H H.gh·'eve' input volt. 2 2 V V,L low-'.wl input vol~ 0.8 0.8 V Vue: Input clemp volt. vee> MIN, It - -18mA -1.2 -1.2 V Hyst~,esl' IVT-t - VT-~ Vee· MIN 0.2 0." 0.2 0." V MIN, SN14S' vee- V,H· 2 V, 2.7 2.7 V'l- 0.8 V, '0'-' --1 mA

SN54S' tmd vee- MIN, V,H - 2 V, 2.4 3." 2.4 3.4 V SN74S' V,L· 0.8 V, 'OH· -3mA VOH Hlgh-I."el OUlput volr..ge .nd SN54S' vee> MIN, V,H· 2 V, 2 2 SN74S' V,L" 0.6V, 'OH· MAX "cc· MIN, V,H· 2V, 2.4 3.4 2.4 3.4 V,L· 0.8 V, 'Oti· -3mA \ICC· MIN, VIH· 2 V,· V 2 2 VIL • 0,6 V, 10H· MAX Vec·MIN, VIH-2V, VOL low·'.wl o"tput vote.. O.N 0.66 V VIL • 0.8 V, IOl - MAX Off-'I.t. Oulput curr.nt, MAX, 'OZH hiuh-'.~' woltage app'ied vee> vo - 2.4 V 60 60 V,H· 2 V, ~ Off'IIIC' OUlp". cur,.nl, IOZl low-4'v.1 volt..,. Ipplled V,l· 0.8 V vc -0.6 V -60 -60 Input cUII.nt I' maximum '1 IOput volt... Vee· MAX, V,-I.IV 1 1 mA I'H Hlgh·I.~1 IOPUI currlnt, Inv input Vee· MAX, V,· 2.7 V so 60 ..A -400 -400 ..A IlL Low-I.wl ,nput cu".nt I :~~ ~ vee- MAX, VI- 0.6 V -2 -2 mA los Short-c.rcult output currant. Vee· MAX -60 -225 -60 -225 mA SN64S' 123 147 OutPUll high 80 96 SN74S' 80 136 96 160 vee- MAX, SNMS' 10C 146 120 170 ICC Supply curr.nl Oueputalow mA Outputl oPtn SN74S' 100 1&0 120 180 Outpuel SN64S' 100 145 120 170 de••bled SN14S' 100 160 120 180 t fo, con4itlon• .nown _ MIN or MAX, UN th. approp,"" v."'. IPIClfltd und.r recommended op.reu", con~'''on.. *AIIIYPic.. v.."...... Vce -• V. TA· 21·C. tNor mOl. "'en on. OUtPul ",..lei ... _onN II • '''"', and ""r..... of "'- lIhon~Itc"•• Ihou'~ ...... c.... one etC"'" Iwitching ch.recteristiCi, vee> 6 V, TA • 21)C "SZAG -S241 'ARAMETER TUT CONDITIONS UNIT MIN TV' MAX MIN TV' MAX P'opIIgItlOfl delav time, 4.& 7 lPlH IOW·IO·tllgh·l.ve' OUIDut I I III Plopeeauon dlIIV elme, Cl- 60 pF, RL -goo. 4.& 7 tPHl h'gh ·lo·low ...",1 output • 8 '" tpll OUlput .nabl. time '0 low ,.",1 10 16 10 1& n. tpZH -Output .nabl. tIme to highl.v.r 8.& 10 8 12 n, tPLZ -OUIPut dlilbl. lime from low I.~I el- &pF, RL - eon_ 10 16 10 16 ". 'PHZ ·O"lput d,"blt time1,om high ,."" e 8 I 8 n. Appendix D: Data Sheets 145 TYPES SN&4LS240,SN54lSZ41, SN54LS244,SN&4SZ40,SN54SZ41,SN74lSZ40. SN74LS241,SN74LS244,SN74S240,SN74S241 OCTAL BUFfERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

DRIVE" t LONG- HE ~ .RECEIVER ''''LS241'''S241 REPEATE" ~~ATER REPEATER I'I1.S2A1, '$241 ~~~~·'·~~~~'·~t B>ou~ ~~~~~ ~ . ~~::::;;;\-~-:-n---~-:M~-n----~---::-n--. .--;:::,.=-:::-n=~=-:-n-= 12V·W-_~--;~-=t-'-L--":J~-=\:-r~- ~:J~-=\:-~-~-::J~-=~-'--:J~-=C U v -.NPuT _. OUTPUT - tWuT - OUiNT - iNM- OUTPUT - iNP\iT- 5UTiUf iNPUT - OUTPUT 'LS241. '5241 USED AS REPEATER/LEVEL RESTORER

OUTPUT { CONTROL

v SYSTEMAND/OR MEMORY·ADDRESSBUS 'lS241, '~ USED AS SYSTEM AND/OR MEMORY BUS DRIVER~"IT ORGAHIZATION CAN 8E APPLIED TO HANDLE BINARY OR BCD

~ BUS RECEIVERS IUS CONTROL INPUT OUTPUT CONTROL -8- ..----H -,,- L L H L 8 8 H L L L 8 H H L H " L H H L NONE" NONE" L H

PARTY·LINE BUS SYSTEM WITH MULT.,LE INPUTS, OUTPUTS, AND RECEIVERS extern.' re.iltlW\ce betw..n 111\., inpYt of me '52~ CN '5241 Ind wound or Vee mUlt not exceed 40 kG.

INDEPENDENT 4·BIT BUS DRIVERs/RECEIVERS IN A SINGLE PACKAGE 146 Interfacing the BBeMicrocomputer

TYPES SNS4lS24S, SN74lS24S OCTAL BUS TRANSCEIVERS WITH 3··STATE OUTPUTS BULLETIN NO. OL-S 7612471, OCTOBER 1976

• Bi~irectional Bus Transceiver in a SN54LS245 ... J PACKAGE High-Density 20-Pin Package SN74LS245.•.• J OR N PACKAGE (TOP VIEW) • 3-5tate Outputs Drive Bus Lines Directty • P-N-P Inputs Reduce D-C Loading on Bus Lines • Hysteresis at Bus Inputs Improve Noise Margins • Typical Propagation Delay Times, Port-to-Port ... 12 ns • Typical Enable/Disable Times ... 17 ns

lot. IOH TYPE (SINK (SOURCE CURRENT» CURRENT) SNS4LS245 12mA -12mA SN74LS245 24mA -15mA

positi".lo9ic: see function table description

These OCtal bus transceivers are designed for asynchronous toNo-way communication between data buses. The control function .molementatioo minimizes external timing requirements.

The device allows data transmission from ttle A bus to the B bus or from the B bus to th'! A bus depending upon the logic level at the direction control (01 R) input. The enable input ((3) can be used to disable the device so that the buses are effectively isolated.

o The SN54LS24S is characterized for ooeration over the full military temperature range of -ss'c to 12S e. The SN74LS245 is characterized for operation from o'c to 70°C.

schematics of inputs and outputs FUNCTION TABLE

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS DIRECTION ENABLE ------~vcc CONTROL OPERATION G VCC~---- 50 n NOM t DIR f 9 kn NOM L L B data to A bus ~------t;=< L H A data to B bus INPUT~ '" t ~ ~OUTPUT H X Isolation t>--.~ --~~y cr :- • f ~l H• hiQf' level, L ,. tow level, X• Irrelevant i ; -* t ; ! ~ : I ~ ~~ ~

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ...... 7 V Input voftage ...... 7 V o Operating free-air temcersrure range: SN54LS24S -ss'c to 12S e SN74lS245 o'c to 70~C Storage temperature range -65°C to iso'c Appendix D: Data Sheets 147

TYPES SN54lS245, SN74lS245 OCT Al BUS TRANSCEIVERS WITH 3-ST ATE OUTPUTS

recommended operating conditions

SNSCLS245 SN74LS245 PARAMETER UNIT MIN NOM MAX MIN NOM MAX Supply vol tage. Vee 4.5 5 5.5 4.75 5 5.25 V High-level output current, 10H -12 -15 mA Low-level outPUt current, 10L 12 24 mA Operating free-air ~emperature, TA -55 125 0 70 DC

!Iectrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SNS4lS245 SN74LS245 PARAMETER TEST CONDITIONS' UNIT MIN TVP:;: MAX MIN TYP~ MAX VIH High~evel input voltage 2 2 V VIL Low·level input voltage 0.7 0.8 V VIK Input clamp voltage Vee" MIN, II a -18mA -1.5 -1.5 V Hysteresis (VT+ - VT_)A Of B input Vee" MIN 0.2 0.4 0.2 0.4 V

Vee" MIN, 10H" -3 mA 2.4 3.4 2.4 3.4 VOH High·lwe' output voltage VIH a2V, V VIL .. VIL max 10H" MAX 2 2

Vee" MIN, 10L" 12 mA 0.4 0.4 VOL Low-4evel OUtPut voltage VIH" 2 V, V VIL" VIL max 10L" 24 mA 0.5 Off·state outPut current. 10ZH VO" 2.7 V '20 20 high~itVel voltage applied Vee" MAX, ~A Off·state OUtPut Current, Oat 2 V 10Zl VO"0.4V -'20 -'20 low-level voltage applied Input current at maximum II Vee" MAX, VI-7V 0.1 0.1 mA input voltage IIH High-lwel input current Vee" MAX, VIH=2.7V '20 20 ~A IlL Low-level input current Vee" MAX, VIL" 0.4 V -0.2 -0.2 inA lOS Short-circuit OUtPUt current~ Vee" MAX -40 -225 -40 -225 mA I Total. outputs high 2S 46 25 46 ICC Supply current f Total, outPUts low Vee" MAX, Outputs open 58 100 58 100 mA IOutputs at Hi-Z 64 105 64 105 t For conditions shown _ MIN or MAX. U~ m. MJC)roPriate v••J. wecifi.d under recommended QC:l.,.tin9 conditions. tAli tyPtc:" values ar. at Vee = 5 v , T A- 2S=e. 49 Not more ttl.n one outPut mould b. shorted at a time, and duration of ttl. short-cIrcuit should not exceed on. second.

switching characteristics, Vee =5 V, TA =25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, tplH 12 18 ns low-tc>-high-leveloutput Propagation delay time, tpHL el ~ 45 pF, RL" 667 n 12 18 ns hitl'·t~ow-Ievel output tpZL Output enable time to low I"'" 20 30 ns tpZH OutPUt enable time to hIgh 14N" lS 25 ns tpLZ Output disable time from low level 15 25 ns el - S pF, RL - 667 n tpHZ Output disable time from hi~ lev" 10 18 ns Appendix E:Summary of Connections

SKI UHF out SK2 Video out SK3 RGB 1. Red 4. Sync. 5 2. Green 5.0V 3. Blue 6. +5V

4 2

3

SK4 RS423 A. Data in D. Clear to send, CTS B. Data out E. Ready to send, RTS E A C.OV

o B c·

SK5 Cassette port 1. Output 5. N.C. 2.0V 6. Motor control 7 3. Input 7. Motor control 4. Output 3

2

SK6 Analogue in 1. +5 V 9. Light pen strobe, LPSTB 2.0V 10. 101 (PB1) 8 3.0V 11. VREF 0 0 0 0 0 0 0 0) 4. Channel 3 12. Channel 2 \ _0000000. 5. Analogue ground 13. 100 (PBO) 15 9 6.0V 14. VREF 7. Channell 15. Channel 0 8. Analogue ground

148 Appendix E: Summary ofConnections 149

SK7 Econet 1. Data 4. Data 2.0V 5. Clock 3. Clock 3

2

Disc power extension socket A. 0 V D. -5 V, 75 p.A B. +5 V, 1.25 A E. +12 V, 1.25 A A F C. N.C. F.OV B E C o

PL8 Disc interface 2. Side select 20. Seek step 4. Index 22. Write data 2 34 6. N.C. 24. Write enable 00000000000000000 8. Index 26. Track 0 00000000000000000 10. Drive select 0 28. Write protect 33 12. Drive select 1 30. Read data 14. N.C. 32. Side select 16. Load head 34. N.C. 18. Direction All odd numbered pins are connected to 0 V

PL9 Printer connector 1. STB 15. DATA 6 3. DATA 0 17. DATA 7 2 26 0000000000000 5. DATA 1 19. CAl

0000000000000 7. DATA 2 21. N.C. 25 9. DATA 3 23. N.C. 11. DATA 4 25. N.C. 13. DATA 5 26. N.C. All even numbered pins (except 26) are connected to OV

PLIO User port 1. +5 V 10. PB2 2. CBl 12. PB3 2 20 0000000000 3. +5 V 14. PB4

0000000000 4. CB2 16. PBS 19 6. PBO 18. PB6 8. PBl 20. PB7 All odd numbered pins (except 1 and 3) are connected to OV 150 Interfacing the BBeMicrocomputer

PLl1 1 MHz expansion bus 2. R/NW(R/W) 23.05 4. IMHZE 24.06 2 34 6. NNMI(NMI) 25.07 00000000000000000 8. NIRQ (IRQ) 26.0V 00000000000000000 33 10. NPGFC (FREO) 27. AO 12. NPGFO (JIM) 28. Al 14. NRST (RST) 29. A2 16. ANALOGUE IN 30. A3 18. DO 31. A4 19. 01 32. AS 20.02 33. A6 21. 03 34. A7 22. D4 All odd numbered pins 1 to 17 are connected to 0 V PL12 The tube 2. R/NW (R/W) 22. 05 4. 2MHZE 24. 06 r---2 4__O 6. NIRQ(IRQ) 26.07 o 000 00 0 0 0 0 0 0 000 0 0 0 0 0 8. NTUBE (TUBE) 28. AO 00000000000000000000 10. NRST (RST) 30. Al 39 12. DO 32. A2 14. 01 34. A3 16. 02 36. A4 18. 03 38. AS 20. D4 40. A6 Odd numbered pins 1 to 29 are connected to 0 V; 31 to 39 are connected to +5 V Index

Accumulator 2 Compiler 107 Address bus 1 Condition flags 109 ADVAL command 14,48 Contact bounce 29 Advanced Data Link Control, ADLC Control bus 1 15 Conversion rate, of ADC 46 Advanced low-power Schottky TTL Conversion time, of ADC 46 104 CRT controller 8 ANALOG IN 17 Analogue-digital converter, ADC Darlington transistor 22 12,43 Data bus 1 conversion rate 46 Data Direction Register, DDR 21, 69 conversion time 46 Debouncing, of switch 29 resolution 46 Digital-analogue converter, DAC 12, successive approximation 51 method 98 Digitizer Analogue inputs 12, 43~56 radius arm 91 ANSI/IEEE Std 488-1975 65 two sliders 91 Assembler 2,5,7,107 DIM statement 6 Asynchronous Communications Interface Adapter, ACIA 10 Econet 14 Auxiliary Control Register, of VIA End of conversion signal 46 39 Ethernet 14 Events 37 Background task 35 Expansion box 17, 57 Bang-bang control 76 Extended page number 17, 61 Baud rate 10 External paging register 17 Block numbers 62 BRK instruction 36 Bus Fanout 104 address Field, of instruction 2 control Fire buttons 14, 49 data 1 Floppy Disc Controller, FDC 16 1 MHz 3,16,57-75 FOR statement 7 BYTEV 5 Foreground task 35 Frame 10 Capacitor, charge/discharge display FRED 3,57 99 FX calls 5 Cassette port 8, 11 Clean page selection signals 59 Games paddles 14 Clear Interrupt Disable, CLI 38 General Purpose Interface Bus, Clock stretching circuitry 59 GP-IB 64 Closed loop control 80 Gray code 31

151 152 Index

Handshake transfers 67 Object code 107 Highway 1 Op-eode byte 108 Housekeeping operations 35, 108 Op-eode set 2 HP-IB 64 Open-eollector TTL 105 Operational amplifier 94 IEC~25-1 bus standard 65 OPT command 7 IEEE-488 bus 64 Optical shaft encoder 31 Image, of page register 64 Opto-switch 53 Index registers 2 OSBYTE calls 5,49,57 Initialisation of PIA 73 Oscilloscope 95 Input port 3 Output port 3 Instruction 2 Output Register, OR 21 Instruction set 2 Oven controller 81 Instruction types 109 Insulation Displacement Connectors, Page 16 IDC 15 Page register 17, 6 1 Interpreter 108 Pedestrian control of traffic lights Interrupt 32 39 vectors 36 Peripheral Control Register, of VIA Interrupt Enable Register, of VIA 39 39 Interrupt Flag Register, of VIA 38 Peripheral Interface Adapter, PIA Interrupt Request, IRQ 17,35,37 69 Pixel 7 JIM 3,57,61 Pop, from stack 35, 110 Joystick controller 14 Port 3 Potentiometer 12 Keyboard scanning 27 Printer interface 16 Program counter, PC 2 Last in, first out memory, LIFO 35 Programmable unijunction transistor Light emitting diode, LED 22 53 Light pen strobe, LPSTB 14 Pull, from stack 35, 110 Light-dependent resistor 53 Pull-up resistor 28 Listener, on IEEE-488 bus 65 Pulse width modulation 81 Local area network, LAN 14 Push, to stack 35, 110 Look-up table 31 Put-and-take ADC 98 Low-power Schottky TTL 104 RAM, random access memory Machine code programming 107-10 Read only memory 2 Mark-to-space ratio 76 Read/write memory 2 Masking, of interrupts 38 Reed relay 25 Memory Relaxation oscillator 53 LIFO 35 Relay 25 RAM 1 solid-state, SSR 26 ROM 2 Reset button 14 stack 35 Reset vector 35 Memory-mapped I/O 3, 57, 111 Resolution, of ADC 46 Mode 7 7 Return from Interrupt, RTI 35 Multiplexing, of displays 25, 83 Return from Subroutine, RTS 7,38 Multiplying digital-analogue converter, Reversing scan method 32 MDAC 52 Ring counter 84 ROM, read only memory 2 Non-maskable Interrupt, NMI 17, RS232-e standard 8 35 RS423 standard 8 Index 153

Sample and hold circuit 46 Universal Asynchronous Receiver/ Sampling theorem 50 Transmitter, UART 10 Sawtooth waveform 44 User port 16, 19-42 Schottky diode 104 Second processor 17 Selection register, of ADC 46 V24 interface 8 Set Interrupt Disable, SEI 38 Valid memory address, VMA 59 Seven-segment display 22 Vector 35 SHEILA 3 break, BRKV 36 Signal conditioning 94 byte, BYTEV 5 Simple harmonic motion 89 event, EVNTV 37 Sinewave, generation of 86 IRQIV 37 Solid-state relay, SSR 26 IRQ2V 37 Source code 107 VELA 74 Stack 35 Versatile Interface Adapter, VIA 14, Stack pointer, SP 2, 35, 110 19, 118-37 Staircase generator 87 Auxiliary Control Register, Staircase waveform 43 ACR 39 Start bit 10 Interrupt Enable Register, IER Status 19 39 Status register Interrupt Flag Register, IFR of ADC 46 38 of processor 2 Peripheral Control Register, Stepper motor 78 PCR 39 Stop bit 10 Video signals 7 Successive approximation method 98 Voltage to frequency converter, VFC 44 Talker, on IEEE-488 bus 65 Task 35 Teletext mode 7 Watchdog timer 67 Three-state TTL 105 Wiper, of potentiometer 12 Totem-pole circuit 102 Wired-QR 17,57,66,105 Traffic light sequence 26,39 Transistor-transistor logic, TTL 102-6 Zero page 17 Tube 17

UART 10 *FX calls 5 Unijunction transistor, UJT 53 1MHz bus 3, 16, 57-75 Unit load, of TTL 104 ~PD7002 converter 12, 138-41