UG1046 Ultrafast Embedded Design Methodology Guide

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UG1046 Ultrafast Embedded Design Methodology Guide

UltraFast Embedded Design Methodology Guide UG1046 (v2.3) April 20, 2018 Revision History The following table shows the revision history for this document. Date Version Revision 04/20/2018 2.3 • Added a note in the Overview section of Chapter 5. • Replaced BFM terminology with VIP across the user guide. 07/27/2017 2.2 • Vivado IDE updates and minor editorial changes. 04/22/2015 2.1 • Added Embedded Design Methodology Checklist. • Added Accessing Documentation and Training. 03/26/2015 2.0 • Added SDSoC Environment. • Added Related Design Hubs. 10/20/2014 1.1 • Removed outdated information. •In System Level Considerations, added information to the following sections: ° Performance ° Clocking and Reset 10/08/2014 1.0 Initial Release of document. UltraFast Embedded Design Methodology Guide Send Feedback 2 UG1046 (v2.3) April 20, 2018 www.xilinx.com Table of Contents Chapter 1: Introduction Embedded Design Methodology Checklist. 9 Accessing Documentation and Training . 10 Chapter 2: System Level Considerations Performance. 13 Power Consumption . 18 Clocking and Reset. 36 Interrupts . 41 Embedded Device Security . 45 Profiling and Partitioning . 51 Chapter 3: Hardware Design Considerations Configuration and Boot Devices . 63 Memory Interfaces . 69 Peripherals . 76 Designing IP Blocks . 94 Hardware Performance Considerations . 102 Dataflow . 108 PL Clocking Methodology . 112 ACP and Cache Coherency. 116 PL High-Performance Port Access. 120 System Management Hardware Assistance. 124 Managing Hardware Reconfiguration . 127 GPs and Direct PL Access from APU . 133 Chapter 4: Software Design Considerations Processor Configuration . 137 OS and RTOS Choices . 142 Libraries and Middleware . 152 Boot Loaders . 156 Software Development Tools . 162 UltraFast Embedded Design Methodology GuideSend Feedback 3 UG1046 (v2.3) April 20, 2018 www.xilinx.com Chapter 5: Hardware Design Flow Overview . 171 Using the Vivado IDE to Build IP Subsystems. 171 Rule-Based Connection . 173 Creating Hierarchical IP Subsystems. 173 Board Window . 173 Generating Block Designs . 174 Creating and Packaging IP for Reuse . 174 Creating Custom Interfaces . 176 Managing Custom IP . 176 Vivado High-Level Synthesis (HLS) . 177 Summary. 178 Chapter 6: Software Design Flow Board Bring-Up Development. 181 Driver Development . 184 Application Developer . 192 Xilinx SDK Tools and Packages . 197 Xilinx Software Development Tools . 201 Chapter 7: Debug Overview . 203 Software-Only Debug . 204 Simulation-Based Debug . 209 Board Debug. 210 Hardware and Software Co-Debug . 211 Virtual Platforms . 212 Chapter 8: SDSoC Environment Introduction . 215 Overall Usage Flow . 216 Profiling . 219 Performance Estimation . 220 Generating and Running a Complete Software-Hardware System . 220 Optimizing Performance Using C-Callable RTL IP Library . 220 Optimizing IP Performance Using HLS . 221 Optimizing System Performance . 221 Debugging the System . 223 Performance Measurement and Analysis . ..

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