Journal of Xi'an University of Architecture & Technology ISSN No : 1006-7930
Design and Development of Soft Core Microprocessor using Open-Source EDA tools
Taha Bilal Iqbal Abdul Wasay Mudasser Dept. of ECE, Lords Institute Dept. of ECE, Lords Institute Dept. of ECE, Lords institute of Engineering & Technology, of Engineering & Technology, of Engineering & Technology, Hyderabad, India, Hyderabad, India Hyderabad, India, e-mail: [email protected] e-mail: [email protected] e-mail: [email protected]
Abstract- This paper discusses about the But the biggest problem that will arise due to designing of a custom soft- core this is that there will no or very less software microprocessor along with various support among different manufacturers. Here architectures that can be considered while come the EDA tools in the picture. Xilinx have designing one. A discussion on the pros and their own set of EDA tools like Xilinx Vivado, cons of using custom architecture is PetaLinux and so on, Similarly, Intel too has its presented. In this paper, a simple 16-bit own software tool called Intel Quartus Prime. MIPS microprocessor has been implemented in VHDL and is simulated Imagine a large number of companies using GHDL and testbench waveforms having their own set of tools for their own verified using GTKWave. The pros and cons FPGAs, issues like inter-compatibility and of using these tools are also discussed. pricing will arise. So, to prevent such problems as well as to promote the open-source tools and Keywords- Microprocessor, ISA, VHDL, FPGA technology in the academic and GHDL, GTKWave, Open-Source research institutes, especially those who have less monetary budget and are under-privileged, INTRODUCTION the promise of open-source software Soft core microprocessor is quite different guarantees equal freedom and opportunity. from a typical microprocessor, referred as a This paper promotes the existing open-source hard-core microprocessor. Instead of physical EDA tools like GHDL (a VHDL simulator) and layout and connections, a soft-core GTKWave (a waveform monitor) by microprocessor is designed using Hardware implementing a simple 16-bit soft core Descriptive Languages or HDLs. Currently the microprocessor and discusses briefly the pros most commonly used HDLs in the industry are and cons of using these tools. SystemVerilog and VHDL. A soft-core microprocessor is designed by simply writing This paper is divided into two parts, Part-I a script in the HDL. They can be implemented discusses about the pros and cons of designing physically by downloading the code in an a custom architecture. Part-II has a brief FPGA. The biggest vendors of FPGAs are introduction about the open-source tools used Xilinx and Intel. Due to the stagnation of followed by simulating a simple 16-bit MIPS Moore’s law the focus of industry has shifted architecture soft core microprocessor. from smaller and faster microprocessor, to application specific and custom architecture. PART I: DESIGNING A SOFT-CORE One can design their own architecture or use MICROPROCESSOR OF CUSTOM ARCHITECTURE one of the open-source architectures like When planning to make a custom core, a RISC-V to implement their custom core. With designer is confronted with the choice of these many changes in the industry the obvious whether to use an available open-source ISA or need that will rise will be the FPGAs. And to create their own from scratch. This section therefore, a large number of manufacturers discusses about the pros and cons of each have and will start to produce their own FPGA.
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choice and later discusses the steps to follow cannot be used with Linux and its distros being when planning to design a custom architecture. an exception. Linux and some of its distros are open-source and their licenses allow anyone to A.OPEN-SOURCE ISA OR CUSTOM ISA? modify and reuse their code. So, you can use There are large number of open-source Linux but you will have to write your own ISAs like the popular RISC-V, OpenRISC, Linux port that supports your design. OpenSPARC, LEON and many others. Each O OMMUNICATION UPPORT one of these have some differences among II. N C S them, however discussing those differences is If the core is completely self-designed and out of scope of this paper. We will consider a it can’t communicate with external devices as general standpoint when comparing it with the it won’t support the various communication Custom ISA. protocols like USB, Ethernet and others.
Open-Source ISA are designed by Some designers do adopt the strategy of researchers and scientists and are maintained mixing their design with others, for example, a by the communities. For instance, the RISC-V designer designs his own core but uses others Foundation maintains the RISC-V ISA. A large specialized core for communication support number of people from around the world and in some cases even operating system contribute and thus try to achieve a complete support. All in all, one can do all these if they support for the newcomers of the community. have enough technical knowledge and These projects have been around for a long obviously enough time. time and thus have reached a stage where they can nearly compete with the existing tech PART II: SIMULATION USING OPEN-SOURCE giants. For instance, RISC-V have been started EDA TOOLS to be compared with the ARM. The purpose of using open-source EDA tools instead of closed-source specialized Custom ISA can be designed by anyone software tools is to promote these tools as well who have the knowledge about the System as to make sure that every vendor of FPGA in Architecture. This is a personal or company the market gets equal opportunity, as this helps level project and getting external support and in the availability of low-cost FPGAs. There help is nearly impossible unless they study and are some vendors that do sell FPGAs that sell understand your design. at a cost lower than the Xilinx, Intel or Lattice. However, only people with high can technical The prime benefit of designing an skills can use them. It must be made sure that architecture is security. Consider a company the students, especially the underprivileged using computer systems using an architecture ones can get access to them as they can learn a that’s completely different and unknown to the lot. This will surely help in the improvement of outside world. Such system is nearly the quality of education. impossible to get hacked and have their data stolen. Such systems are only useful in The tools used in this paper are GHDL and Government organisations or companies that GTKWave both of them open-source and can have very valuable data stored like Intellectual be freely downloaded from their respective Property (IP). Except this, there are a lot of websites. However, these are not the only problems and issues that arise when using one, open-source EDA tools out there, there are a like: lot of others like Verilator (used to simulate -No Operating System Support Verilog script), Yosys and so on. -No Communication Support I. GHDL I. No Operating System Support Since the design is unknown to the world, GHDL is a VHDL Simulator which the mainstream propriety operating systems converts the VHDL script into the machine like the Microsoft Windows and Macintosh code. However, GHDL doesn’t have a GUI for
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now and therefore has to used using the A. EXISTING METHODOLOGY Command Line Interface typically referred to Use of closed source tools like Xilinx ISE as Command Prompt in Windows and or Intel Quartus Prime for Simulation and Syn- Terminal in Ubuntu (a Linux distro based on Debian). For this paper we have used the thesis of Soft Core Microprocessor. The Terminal as shown, softcore microprocessor used is an MIPS mi- croprocessor, MIPS stands for Microprocessor without Interlocked Pipeline Stages. This MIPS microprocessor has an instruction word length of 16bit, along with 8 general purpose registers. These registers are 16bit wide. The ALU implemented here is a simple ALU, it does not support bulky operations like multi- plication and division. Floating point units are not used MIPS-16.
B. INTERNAL ARCHITECTURE AND OPCODES
Figure 1: Terminal showing ghdl version
The only difficulty faced when using this tool is the installation process, which is also a one- time deal and can be done by following the GHDL Documentation [1].
II. GTKWAVE GTKWave is a waveform viewer which can be used to view large number file formats like the .ghw, .vcd and many others. This tool does have a GUI which can be used to browse, set and view the testbench waveforms [2].
Figure 3: Architecture of 16-bit MIPS processor
C. PROPOSED METHODOLOGY Figure 2: A Typical GTKWave Window Use of open source tools for design, simu- lation and RTL for schematic of Soft Core Mi- croprocessor. Innovation by using open source EDA tools that are GHDL and GTKWave.
Where GHDl is VHDL simulator used to con-
vert VHDL script into the machine code.
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GHDL doesn’t have any GUI and therefore needs to use Command Line Interface. The tool GTKWave is a waveform generator which can use file formats like .ghw, .vcd.
D. SIMULATION PROCEDURE For simulation of 16-bit MIPS Microprocessor only the HDL script file is required. For this paper we have used a VHDL script (.vhdl) file along with its testbench waveform file. The process of simulation is quite simple and can be done within 3 steps. First, we use the GHDL Simulator to analyse our VHDL files. Figure 5: Terminal showing the command for storing the testbench waveform in an external file
The output is stored in the .ghw file and viewed using our waveform viewer, GTKWave.
Figure 4: Terminal showing the successful analysis of the input files
Second, we use the GHDL Simulator to run our generated object file and store the output i.e. Figure 6: Terminal showing the launch of the waves in a file called p1.ghw as shown, GTKWave using generated .ghw file
Finally, using the GTKWave tool simulated waveforms of the 16bit MIPS processor is obtained.
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Figure 7: GTKWave showing the testbench waveforms generated by GHDL
E. FLOWCHART
$cd~ Make a $mkdir
ion E n t F.Enter the Check e code syntax r
Enter the code Analysis $ ls -> To check listing $ ghdl -s
Launching GTKwave To create GHW file $ ghdl –r
Outputs obtained Output waveform
Figure 8: Flowcharts showing the general procedure(left) and the commands to be used on each step(right) Volume XII, Issue V, 2020 Page No 2413 Journal of Xi'an University of Architecture & Technology ISSN No : 1006-7930
SYNTHESIS COMPUTER" SIMULATION AND FPGA IMPLEMENTATION OF A SIMPLE The only downfall of using the open- COMPUTER (1998) source tools is that the Synthesis option is still Available at: immature and in experimental stage. However, http://works.bepress.com/philadelphia_university/ if in the near future this is further developed it 90/ will become one of the strengths of the open- source tools, the compatibility with any FPGA [8]- “The RISC-V Instruction Set Manual, Volume whose library is available. I: User-Level ISA, Document Version 2.2”, Editors Andrew Waterman and Krste CONCLUSION Asanović, RISC-V Foundation, May 2017.
In this paper we have discussed about the [9]- Hennessy, John L., and David A. Patterson. pros and cons of using a custom core Computer Architecture: a Quantitative Approach. architecture when designing a microprocessor. Morgan Kaufmann, 2019. Followed by the discussion on some of the open-source tools like GHDL and GTKWave [10]- Patterson, David A., and John L. Hennessy. with a demo by implementing a simple 16-bit Computer Organization and Design: The Hardware MIPS microprocessor. We found out that Software Interface: RISC-V Edition. Morgan although these tools are good for simulating Kaufmann Publishers, 2018. but they couldn’t be synthesised in an FPGA and the option is currently in experimental stage.
REFERENCES [1]- “GHDL” News - GHDL 1.0-Dev Documentation, ghdl.readthedocs.io/en/latest/index.html.
[2]- "GTKWave" -http://gtkwave.sourceforge.net/
[3]- El Khaili, M.. (2014). 4-Bit Processing Unit Design Using VHDL Structural Modeling For Multiprocessor Architecture. Engineering Science and Technology: An International Journal (ESTIJ). 4. 2250-3498.
[4]- Jansen, Dirk & Dusch, Benjamin. (2014). Every student makes his own microprocessor. 10th European Workshop on Microelectronics Education, EWME 2014. 97-101. 10.1109/EWME.2014.6877404.
[5]- Martinez Santa, Fernando & Martínez, Fredy & Ariza, Holman. (2017). Minimalist 4-bit Processor Focused on Processors Theory Teaching. Indian Journal of Science and Technology. 10. 1-6. 10.17485/ijst/2017/v10i14/111328.
[6]- E. Ayeh, K. Agbedanu, Y. Morita, O. Adamo and P. Guturu, "FPGA Implementation of an 8-bit Simple Processor," 2008 IEEE Region 5 Conference, Kansas City, MO, 2008, pp. 1-5.
[7]- Philadelphia University. "SIMULATION AND FPGA IMPLEMENTATION OF A SIMPLE
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