Modeling Junctionless Metal-Oxide-Semiconductor Field- Effect Transistor
THÈSE NO 6811 (2015)
PRÉSENTÉE LE 27 NOVEMBRE 2015 À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR GROUPE DE SCIENTIFIQUES STI PROGRAMME DOCTORAL EN MICROSYSTÈMES ET MICROÉLECTRONIQUE
ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE
POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES
PAR
Farzan JAZAERI
acceptée sur proposition du jury:
Prof. M. A. Ionescu, président du jury Dr J.-M. Sallese, directeur de thèse Prof. G. Baccarani, rapporteur Prof. B. Iniguez, rapporteur Prof. Y. Leblebici, rapporteur
Suisse 2015
Simplicity is the ultimate sophistication. —LeonardodaVinci
To my dear parents who made my education possible, through their sacrifice, devotion, and support.
To my brothers you will always be in my heart no matter how far I go.
Acknowledgements
Scientific research is often a collaborative endeavor, and the work presented in this dissertation is certainly no exception. During the past four years I have had the pleasure of working with a number of bright and enthusiastic people that I would like to mention here.
First of all, it has been my honor and privilege to have had Dr. Jean-Michel Sallese as my research advisor during my graduate career at EPFL and I would like to express my utmost gratitude to him for his generous help and support throughout the course of this work. He taught me not only his unsurpassed technical knowledge, but his exceptional professionalism and his sincere attitude towards scientific research. He impressed me very much by his humility, responsibility and strict attitude in training students. He always provided timely and warm encouragement and support in difficult times. He was never hesitant to get involved with details of my calculations and I am grateful for that.
Jean-Michel gave me not only the supervision of my research but also the guidance on my future life. His great knowledge in semiconductor physics motivated my devotion to the field of semiconductor devices. He was a role model for me; a great friend put things in proper perspective, and contributed to my positive attitude. I would especially like to thank him for giving me freedom to pursue my research interests. Indeed, without his invaluable guidance, and encouragement, this work could not have come to fruition.
It is my pleasure to thank to the professors from my doctoral and exam commission: Prof. Giorgio Baccarani, Prof. Benjamin Iniguez, Prof. Yusef Leblebici, and Prof. Adrian M. Ionescu.
v Acknowledgements
I appreciate the time they have taken to participate in these crucial last steps of my PhD and also their insightful advices.
I must say thanks to Dr. Wladek Grabinski and Dr. Adil Koukab for sharing their invaluable experiences and encouragements. I wish to thank Dr. Didier Bouvet for his friendly and patient support during the cleanroom fabrication processes.
I feel very lucky to have had the opportunity to explore my academic interests for the past four years at EPFL. Indeed, my life in Lausanne would not have been wonderful and fulfilling without many of my friends who I met during the time in Lausanne. I would especially like to thank Dr. Maria-Anna Chalkiadaki and Dr. Lucian Barbut, and who made it possible. I would thank my good friends and colleagues. It was very enjoyable working with nice friends. We stablished friendships in this big family. I really want to send my thanks and best wishes to them: Dr. Antonios Bazigos, Dr. Anurag Mangla, Dr. Mehrad Azizighannad, Dr. Omid Talebi, Dr. Naser Khosropour, Dr. Sarah Rafiee, Mariana Barbut, Dr. José Luis Padilla, Dr. Ehsan Kazemi, Dr. Mani Bastani Parizi, Dr. Georgios Lilis, Lauriane Richer, Ramona Rosu, and Silvia Puche. I would like to thank all of my colleagues for many valuable discussions and helpful suggestions. I am very thankful to have had the camaraderie and support of so many people in so many places. Thanks to Isabelle and Karin, our dear assistances for bureaucratic matters, and to Raymond Sutter, Marc Paster for IT and software support.
The financial support for this work from Swiss National Science Foundation organization (SNF) is greatly appreciated.
I would like to express appreciation to the people that helped me to complete this project. Last, but certainly not least, I am deeply grateful for never-ending love from my parents (Ferdos and Jamal) and my brothers; Dr. Farshid and Dr. Farzad. I owe more than words can describe to my parents. I would like to sincerely thank them for their support, sacrifices, and encouragement in the past 30 years which made all these possible. This work is dedicated to them.
Lausanne,1st October 2015 Farzan Jazaeri
vi
Abstract
Metal-oxide semiconductor (MOS) field-effect transistor (FET) scaling is following the predic- tion of the Moore’s law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap.
In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes.
This dissertation focuses on the physics and modeling of nanoscale junctionless double-gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double-gate configuration as well as junctionless nanowires topologies will be presented.
Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson-Boltzmann equation and on the drift- diffusion transport to derive charges and current in long-channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long-channel concept. This includes modeling short-channel effects
1 Abstract and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off -state currents.
Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge-based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture.
Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design-space tool with explicit links between silicon thickness and doping ensuring safe operation.
Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law.
Based on these developments, the EPFL-JL-model was implemented into Hspice platforms to be used by circuit designers.
Key words: MOSFET, junctionless FET, nanowire FET, compact modeling, short-channel effects, Trans-capacitance, noise, CMOS scaling, mobility, design space, transient analysis, asymmetric double-gate MOSFET.
2 Résumé
La miniaturisation du transistor à effet de champ de type Métal-Oxide-Semiconducteur (MOS) poursuit une miniaturisation prédite par la loi de Moore depuis 45 ans. Cette miniaturisation est une facteur clef qui permet à l’industrie de la microélectronique de satisfaire la demande constante pour des performances toujours plus exigeantes. Cependant, cette miniaturisation devient particulièrement compliquée au delà du nœud de 28 nm à causes des limitations en terme de procédé de fabrication et de performance du composant. Afin de parer à ce possible ralentissement, de nouvelles architectures non standards ont été introduites dans la ’roadmap’.
Dans ce contexte, le transistor à effet de champ sans jonction, communément désigné par ’junction less FET’, représente un nouveau type de composant qui est théoriquement en mesure de satisfaire la miniaturisation de la technologie CMOS car il garantit un contrôle optimal par la grille, un faible courant de fuite, une mobilité accrue des porteurs de charge, tout en présentant des étapes de fabrication simplifiées.
Cette thèse traite essentiellement de la modélisation de ces transistors ‘junctionless’ de type double-grille et nano cylindriques (‘nanowires’) en conservant une approche physique. La première partie discute les avantages et les inconvénients de cette nouvelle technologie tout en présentant les modéles qui ont été développés jusqu’à présent. Par la suite, la modélisation adopté dans ce travail sera exposée dans les différent chapitres.
Le modèle développé est un modèle en charge qui se base sur l’équation de Poisson-Boltzmann et qui utilise le concept de drift and diffusion pour le transport des charges. Un modèle rigoureux du courant dans le canal du transistor est ainsi obtenu. Deux jeux de solutions apparaissent selon que le transistor opère en mode de déplétion ou d’accumulation. Il n’est introduit aucun paramètre d’ajustement, et le modèle prédit avec précision tous les modes opératoires. Au cours de ce travail, la modélisation a été étendue pour prendre en compte la plupart des phénomènes physiques tels que la modélisation des effets canaux courts aux dimension nanométriques et la modélisation du bruit blanc dans le canal avec la corrélation
3 Abstract avec le bruit de la grille. D’autres part, afin de permettre une simulation en mode AC, un modèle complet de la matrice de transcapacités est proposé.
De même, au delà du mode opératoire symétrique, le fonctionnement asymétrique a été modélisé au moyen de composants symétriques virtuels, ce qui permet d’étendre considéra- blement son domaine d’application. De plus, le modèle est capable de simuler des transistors de type nanowire en adoptant le même formalisme.
Etant donné que ce composant doit répondre à des critères très stricts en matière de dimen- sionnement et de dopage, un modèle dédié à ces aspects technologiques visant à s’assurer que le transistor peut être fermé a fait l’objet d’une modélisation théorique toute particulière en proposant des relations entre les paramètres technologiques.
Enfin, un modèle dédié à l’extraction de la mobilité des porteurs dans ces transistors est proposé pour la première fois.
Le modèle "EPFL-JL" a été implémenté dans le simulateur NGSpice et a été utilisé pour simuler des circuits de base utilisant la technologie Junction less FETs.
Mots clefs : MOSFET, junctionless FET, nanowire FET, modèle compact, effets canaux courts, Trans-capacité, bruit, CMOS scaling, mobilité, design space, analyse transitoire, mode asymé- trique.
4 Contents
Acknowledgements v
Abstract (English/French) 1
List of figures 13
List of tables 21
Abbreviations 23
List of symbols 25
1 Introduction 29
1.1 Overview of CMOS Technology ...... 29
1.2 Moore’s law and scaling devices to their limits ...... 30
1.3 Limits of CMOS scaling and alternative MOSFET structures ...... 32
1.4 Junctionless technology beyond CMOS ...... 33
1.4.1 Working principle of junctionless MOSFETs ...... 33
1.4.2 Advantages and limits ...... 36
1.4.3 Non-standard junctionless architectures ...... 38
1.4.3.1 Junctionless double-gate MOSFETs ...... 38
5 Contents
1.4.3.2 Junctionless nanowire FETs ...... 39
1.4.3.3 Junctionless bulk FinFETs ...... 39
1.4.3.4 Junctionless vertical slit FETs ...... 39
1.5Summary...... 41
2 Theory and compact modeling of the junctionless FETs: review and perspectives 43
2.1 DC modeling of symmetric junctionless double-gate MOSFETs ...... 45
2.1.1 Crude depletion approximation ...... 45
2.1.2 Improved depletion approximation for junctionless UTB SOI-FETs . . . 45
2.1.3 Surface potential based approach ...... 46
2.1.4 Simplified current model at pinch-off ...... 47
2.1.5 Semi-charge-based approach ...... 47
2.1.6 An analytical approach based on conventional inversion mode MOSFETs 48
2.1.7 Parabolic approximation and full-range drain current ...... 48
2.1.8 Gaussian distribution of mobile charge density ...... 48
2.1.9 Simple model for performance estimation ...... 49
2.1.10 Explicit drain current model relying on charge-based approach . . . . . 49
2.1.11 Compact modeling of quantum mechanical effects ...... 49
2.1.12 Short-channel effects (SCEs) in junctionless double-gate MOSFET . . . . 50
2.2 Compact DC modeling of junctionless asymmetric double-gate MOSFETs . . . 52
2.3 Trans-capacitance modeling in junctionless double-gate MOSFETs ...... 52
2.4 Compact modeling of junctionless nanowire FETs ...... 53
2.4.1 Subthreshold behavior in junctionless nanowire FETs ...... 54
2.5 Trans-capacitance modeling in junctionless nanowire FETs ...... 55
6 Contents
2.6 Quantum mechanical effects in junctionless nanowire FETs ...... 55
2.7Summary...... 56
3 Recalling the basis of the EPFL charge-based model 57
3.1 Charge-based modelling of junctionless double-gate field-effect transistors . . 57
3.1.1 Electrostatics in junctionless double-gate MOSFET ...... 57
3.1.2 General approach to the mobile charge calculation ...... 61
3.1.3 Approximate expressions for charges ...... 63
3.1.3.1 The junctionless double-gate MOSFET in accumulation . . . . 63
3.1.3.2 The junctionless double-gate MOSFET in depletion ...... 65
3.1.4 Assessment of the mobile charge density ...... 66
3.1.5 Derivation of the current ...... 69
3.1.5.1 The current in accumulation ...... 70
3.1.5.2 The current in depletion ...... 70
3.1.6 General treatment of the current in junctionless double-gate MOSFETs . 71
3.1.6.1 The whole channel in accumulation ...... 71
3.1.6.2 The whole channel in depletion ...... 71
3.1.6.3 The ‘hybrid’ channel ...... 71
3.1.7 Comparison with numerical simulation ...... 72
3.2 A common core model for junctionless nanowires and symmetric double-gate FETs...... 77
3.2.1 Analysis of electrostatics in junctionless nanowire FETs ...... 77
3.2.1.1 The Poisson-Boltzmann equation in junctionless nanowire FETs 77
3.2.1.2 Accounting for the gate capacitance ...... 80
7 Contents
3.2.2 Derivation of the current in junctionless nanowire ...... 82
3.2.3 Simulations ...... 83
3.3ThresholdvoltageinjunctionlessFETs...... 85
3.4Summary...... 85
4 Model driven technological design-space considerations of junctionless FETs 87
4.1 off -state current and hole inversion layer in junctionless FETs ...... 87
4.2 Model derivation in junctionless double-gate MOSFET ...... 88
4.2.1 Electrostatics in junctionless double-gate MOSFET ...... 88
4.2.2 Role of the channel potential in junctionless double-gate MOSFET . . . 93
4.2.3 Estimation of the critical points ...... 94
4.2.4 Assessment of the critical mobile charge density in junctionless double- gateFETs...... 99
4.2.5 On/Off -current ratio in junctionless double-gate MOSFETs ...... 100
4.2.6 Rail-to-rail supply voltage ...... 104
4.3 Design space of twin gate junctionless vertical slit FETs ...... 106
4.3.1 Device structure ...... 107
4.3.2 Electrostatics in junctionless VeSFET and design-space ...... 108
4.3.3 Off -state current and on/off current ratio in junctionless VeSFET . . . . 111
4.3.4 Subthreshold slope in junctionless VeSFET ...... 112
4.3.5 DIBL in junctionless VeSFET ...... 112
4.4Summary...... 114
5 Generalization of the charge-based model of junctionless double-gate MOSFETs in- cluding inversion 115
8 Contents
5.1 off -state current and hole inversion layer in junctionless FETs ...... 115
5.1.1 Electrostatics in junctionless double-gate MOSFET ...... 116
5.1.2 Co-existence of inversion and depletion ...... 119
5.1.3 Asymptotic relations in depletion ...... 120
5.1.4 Inversion layer induced capacitance in junctionless double-gate MOSFET 121
5.1.5 Generalization to junctionless nanowire FETs ...... 123
5.2 Simulations and model assessments ...... 123
5.2.1 Impact of hole layer on drain current ...... 126
5.3Summary...... 127
6 Short channel effects in junctionless symmetric double-gate MOSFETs 129
6.1 Electrostatics in short-channel junctionless double-gate MOSFETS in subthreshold130
6.2 Body center potential and limitations of the parabolic approximation in junc- tionless double-gate MOSFET ...... 133
6.3 Modeling subthreshold slope in junctionless double-gate MOSFET ...... 141
6.4 Limitations of model ...... 145
6.5 Modeling drain induced barrier lowering in junctionless double-gate MOSFET 147
6.6Summary...... 151
7 Trans-capacitance modeling in junctionless symmetric double-gate MOSFETs and gate-all-around nanowire FETs 153
7.1 Model derivation in junctionless symmetric double-gate MOSFET ...... 154
7.1.1 Derivation of the spatial dependence of the mobile charge density along thechannel...... 154
7.1.1.1Generalcase...... 155
7.1.1.2 Channel in depletion/accumulation mode ...... 160
9 Contents
7.1.2 Analytical expressions for the local charge derivatives ...... 162
7.1.3 Simulations and discussion ...... 166
7.2 Model derivation in Gate-All-Around junctionless naowire FETs ...... 170
7.2.1 Equivalent parameters definition ...... 171
7.2.2 Simulations and discussion ...... 173
7.3Summary...... 176
8 Modeling asymmetric operation in double-gate junctionless FETs by means of sym- metric devices 177
8.1 Electrostatics in asymmetric state of junctionless double-gate MOSFET . . . . . 179
8.1.1 Analysis restricted to depletion/accumulation ...... 180
8.1.1.1 General Approach ...... 180
8.1.1.2 Charge-based approach ...... 183
8.1.1.2.1 Extremum potential inside the channel ...... 183
8.1.1.2.2 Extremum potential outside the channel ...... 185
8.1.1.2.3 Ultimate charge-based solution ...... 186
8.1.2 Coexistence of depletion and accumulation ...... 188
8.1.2.1 General Approach ...... 188
8.1.2.2 Charge-based approach for mixed states ...... 189
8.2 Assessment of the mobile charge density ...... 190
8.3Derivationofthecurrent...... 192
8.4 Assessment of continuity at transitions ...... 193
8.5 Limitations and constraints ...... 195
8.6Summary...... 196
10 Contents
9 Modelling channel thermal noise and induced gate noise, and cross correlation noise in junctionless FETs 197
9.1 Thermal noise modeling ...... 198
9.1.1 Channel thermal noise ...... 198
9.1.2 Spatial dependence of the mobile charge density ...... 199
9.2 Induced gate noise in junctionless FET ...... 201
9.3 Cross-correlation noise in junctionless MOSFET ...... 205
9.4Summary...... 208
10 Carrier mobility extraction methodology in junctionless and inversion mode FETs 209
10.1 Principle of the mobility extraction method ...... 210
10.1.1 Mobility extraction based on the Y -function in junctionless FETs . . . . 210
10.1.2 A new approach for electron mobility extraction in junctionless FETs . . 212
10.1.3 A simplified process for carrier mobility extraction ...... 216
10.1.4 Extending the method to inversion mode FETs ...... 218
10.2 Derivatives of Qm with respect to VGS and VDS ...... 219
10.3Summary...... 220
11 The EPFL Junctionless MODEL ver.1.0 221
11.1 The EPFL-Junctionless model modules ...... 222
11.2 Source code modules and library ...... 223
11.2.1 The EPFL-JL model Parameters ...... 223
11.2.2 DC implementation in junctionless FETs ...... 223
11.2.3 Small signal AC analysis in junctionless FETs ...... 224
11.2.4 Junctionless double-gate and nanowire FET amplifier ...... 227
11 Contents
11.2.5 Junctionless double-gate and nanowire FET inverter ...... 228
11.3Summary...... 228
12 Conclusion and perspectives 231
12.1 Conclusion ...... 231
12.2 Recommendations for future work ...... 233
A Appendix 235
A.1 Principle operation for junction FETs ...... 235
A.2 Discussion ...... 236
Bibliography 255
Curriculum Vitae 257
12 List of Figures
1.1 Moore’s law, depicting the generation of mainstream computer processors and the size of random access memory chips, Intel corporation...... 30
1.2 A simple junctionless double-gate MOSFET presented by Colinge and co-workers [1]...... 33
1.3 Electron concentration contour plots in an n-type junctionless gated resistor. . 34
1.4 DIBL and subthreshold slope at VDS = 50mV in junctionless and regular inver-
sion mode devices with Tsc = 5nm [2]...... 37
1.5 The architecture of a single cell n-type VeSFET for high density integration. . . 39
1.6 VeSFET in canvas and VeSFET routing concept ...... 40
3.1 Schematic view of the n-type junctionless symmetric double-gate MOSFET. . . 58
3.2 Sketch of the band energy diagram for the n-type junctionless double-gate MOSFET...... 59
3.3 Sketch of the energy band diagram for the n-type double-gate MOSFET at flat- band condition...... 62
3.4 Semiconductor charge density as a function of the center potential in a 20nm silicon layer of a junctionless double-gate MOSFET with various doping concen- trations...... 64
3.5 Comparison of the mobile charge density in a 20nm junctionless double-gate MOSFET obtained from (3.14) and (3.15), and from ‘regional’ approximations givenby(3.18)and(3.21)...... 66
13 List of Figures
3.6 Mobile charge density versus the gate voltage for a 10nm silicon thickness junc- tionless double-gate MOSFET for different doping concentrations...... 67
3.7 Mobile charge density versus the gate voltage for a 20nm silicon thickness junc- tionless double-gate MOSFET for different doping concentrations...... 67
3.8 Mobile charge density versus the gate voltage for a 40nm silicon thickness junc- tionless double-gate MOSFET for different doping concentrations...... 68
3.9 Drain current versus the gate voltage in linear and saturated regimes in a 20nm − silicon thickness junctionless double-gate MOSFET doped at 1 × 1019cm 3... 72
3.10 Drain current versus the gate voltage in linear and saturated regimes in a 10nm − silicon thickness junctionless double-gate MOSFET doped at 5 × 1019cm 3... 73
3.11 Drain current versus the drain voltage for various gate potentials in a 20nm − silicon thickness junctionless double-gate MOSFET doped at 1019cm 3..... 74
3.12 Drain current versus the drain voltage for various gate potentials in a 10nm − silicon thickness junctionless double-gate MOSFET doped at 5 × 1019cm 3... 74
3.13 Gate transconductance versus the gate voltage at VDS = 1V in a 10nm silicon thickness junctionless double-gate MOSFET for different doping concentration. 75
3.14 Drain transconductance versus the drain voltage for different gate potentials in − a20nm silicon thickness junctionless double-gate MOSFET doped at 1019cm 3.76
3.15 Schematic view of an n-type junctionless nanowire FET...... 77
3.16 Mobile charge density and drain current versus gate voltage in a junctionless
nanowire with various doping densities (VDS = 0)...... 82
4.1 Schematic view of the n-type junctionless double-gate MOSFET...... 88
4.2 Dependence of the body center potential and surface potential versus the gate voltage for different values of silicon thickness...... 90
4.3 Dependence of the body center potential and surface potential versus the gate
voltage for different values of Vch...... 92
4.4 Derivatives of the center potential with respect to the surface potential...... 94
14 List of Figures
4.5 Critical body center potential according to the silicon thickness for different values of doping concentration...... 97
4.6 Critical space of junctionless double-gate MOSFET ...... 98
4.7 Mobile charge density for different values of doping concentration and thickness in junctionless double-gate MOSFET ...... 98
4.8 Mobile charge density and intrinsicoff -current with respect to the doping con- centration for different values of silicon thickness in junctionless double-gate MOSFET...... 100
4.9 I-V characteristics of a 20nm-silicon thickness junctionless double-gate MOS- FET for different values of doping concentration ...... 102
4.10 Pattern of normalized critical current versus doping concentration and silicon thickness in a junctionless double-gate MOSFET...... 103
4.11 On/Off -current ratio of junctionless double-gate MOSFET with respect to silicon thickness for different values of doping concentration...... 104
4.12 IDS −VGS characteristics for 20nm-silicon thickness junctionless double-gate MOSFET for different values of oxide thickness...... 105
4.13 Rail to rail supply voltage (VGS(on)−VGS(off )) according to the silicon thickness for different values of doping concentration in junctionless double-gate MOSFET106
4.14 Top view and 3D geometry of an n-type junctionless VeSFET...... 107
4.15 Electrostatic potential distribution through the channel for different values of r in an n-type junctionless VeSFET...... 108
4.16 IDS −VGS characteristics obtained with TCAD simulations for different values of radius, in an n-type junctionless VeSFET...... 109
4.17 Design space of an n-type junctionless VeSFET ...... 110
4.18 The pattern of normalized off -current versus doping concentration and radius inajunctionlessVeSFET...... 111
4.19 The pattern of on/off current ratio versus doping concentration and radius in a junctionless VeSFET...... 112
15 List of Figures
4.20 Subthreshold swing versus doping concentration and radius in a junctionless VeSFET...... 113
4.21 DIBL function of doping concentration (ND ) and radius (r ) in a junctionless VeSFET...... 113
5.1 Schematic view of the n-type junctionless double-gate MOSFET...... 116
5.2 Dependence of the body center potential and surface potential versus the gate voltage for different values of the channel potential...... 122
5.3 Dependence of the body center potential and surface potential versus the gate voltage for different values of the channel potential...... 122
5.4 Total charge density versus gate potential for different physical parameters and channel potential in junctionless double-gate MOSFETs ...... 123
5.5 Hole concentration at the surface and center of the channel with respect to the gate potential for different values of silicon thickness ...... 124
5.6 Dependence of the intrinsic gate capacitance versus the gate voltage for different values of doping concentration and gate lengths in junctionless double-gate MOSFETs ...... 125
5.7 Dependence of the intrinsic gate capacitance versus the gate voltage for different values of physical parameters in junctionless double-gate and nanowire FETs. . 125
5.8 Drain current versus gate potential for different values of doping concentrations in an n-type junctionless double-gate MOSFET...... 126
6.1 Schematic view of an n-type junctionless double-gate MOSFET...... 131
6.2 Body center potential and surface potential along the lateral direction for 20nm and 50nm gate lengths...... 136
6.3 Variation of the electrostatic potential along lateral and vertical directions in a 10nm-silicon-thickness junctionless double-gate MOSFET...... 137
16 List of Figures
6.4 Distribution of the body center potential along the lateral direction in 10nm- silicon-thickness junctionless double-gate MOSFET devices for different drain
voltages, with VGS = 0V ...... 139
6.5 Minimum body center potential and its location according to drain-source volt- 19 −3 age, imposing VGS = 0V , Δφms = 0.54V and ND = 10 cm in 10nm channel length junctionless double-gate MOSFET ...... 140
6.6 IDS −VGS and its shift versus the shift in VDS fora10nm-silicon thickness junc- − tionless double-gate MOSFET doped at 1019cm 3 for 22nm channel length. . . 144
6.7 IDS −VGS and its shift versus the shift in VDS fora10nm-silicon thickness junc- − tionless double-gate MOSFET doped at 1019cm 3 for 30nm channel length. . . 144
6.8 Subthreshold slope versus the gate length for a 10nm-silicon thickness junction- 19 −3 less double-gate MOSFET doped at 1 × 10 cm and biased at VDS = 10mV .. 145
6.9 Subthreshold slope versus the doping concentration through the channel for a10nm-silicon-thickness junctionless double-gate MOSFET with 22nm gate
length biased at VDS = 100mV and VGS = 0V ...... 146
6.10 Definitions of DIBL according versus gate length for a 10nm-silicon thickness junctionless double-gate MOSFET...... 148
6.11 Threshold voltage shift versus the shift in the minimum center potential for 22nm gate length in a 10nm-silicon thickness junctionless double-gate MOSFET.151
7.1 Schematic view of an n-type junctionless double-gate MOSFET...... 154
7.2 Estimation of flat band position through the channel versus the gate potential
for different values of VDS...... 166
7.3 Mobile charge density along the channel for different values of gate voltages
while VDS = 1V ...... 167
7.4 Dependence of the trans-capacitance versus the gate voltage for VDS = 0V ... 168
7.5 Dependence of the trans-capacitance versus the gate voltage for VDS = 1V ... 169
7.6 Dependence of the trans-capacitance versus the gate voltage for VDS = 0V ... 169
17 List of Figures
7.7 Dependence of the trans-capacitance versus the gate voltage for VDS = 1V . . . 170
7.8 Dependence of the gate capacitance versus the gate voltage for VDS = 0V in heavily doped channel confirming that a hole inversion layer can also build up atthechannelinterface...... 171
7.9 Schematic view of an n-type junctionless nanowire FET...... 171
7.10 Dependence of the trans-capacitance versus the gate voltage for VDS = 0and1V shown in (a) and (b) respectively...... 174
7.11 Dependence of the trans-capacitance versus the gate voltage for VDS = 0and1V shown in (a) and (b) respectively...... 175
8.1 Schematic view of the n-type junctionless asymmetric double-gate MOSFET and two junctionless symmetric double-gate MOSFETs with equivalent physical parameters...... 178
8.2 Sketch of potentials distributions for an n-type junctionless asymmetric double- gate MOSFET for different situations (when the extremum potential appears inside or outside of the channel and also when there is no more extremum). . . 181
8.3 Potential distribution between two gates in an n-type junctionless asymmetric double-gate MOSFET when the extremum potential appears inside or outside of the channel and also when there is no more extremum...... 187
8.4 Mobile charge density with respect to the effective gate potentials in linear and logarithmic scales for different junctionless asymmetric double-gate MOSFET devices...... 191
8.5 Mobile charge density (C/m2) with respect to the effective gate potentials in linear and logarithmic scales for smooth transitions between three possible conditions...... 192
8.6 Drain current versus gate potentials in linear and saturated regime in 10nm- − silicon thickness junctionless ADG MOSFET doped at 1 × 1019cm 3 for different valuesofdrainpotential...... 194
8.7 Transition of the extremum potential inside or outside of the channel arises when gates are not equivalent and/or biased at different potentials...... 196
18 List of Figures
9.1 Schematic view of an n-type junctionless double gate MOSFET...... 198
9.2 Thermal noise power spectral density of the drain current fluctuation versus
effective gate voltage, drain current, and gm/IDS for different values of drain po- tentials and channel doping concentration in junctionless double-gate MOSFET and inversion mode double-gate MOSFETs...... 202
9.3 The power Spectral Density (PSD) of induced gate noise versus drain current for different values of drain potentials...... 203
9.4 The power Spectral Density of induced gate noise versus effective gate voltage for different values of physical parameters...... 204
9.5 The power Spectral Density of cross-correlation noise versus effective gate volt- age for different values drain potentials...... 207
10.1 Schematic view of an n-type junctionless double-gate MOSFET...... 210
10.2 Electron mobility given by non-homographic and homographic models and obtained by Y -Function with respect to effective gate potential and also the IDS/( gm) versus gate potential obtained by Y -Function for two different mo- bility models...... 211
10.3 Comparison between RHS and LHS of relation (10.7) in an n-type junctionless double-gate MOSFET for two values of silicon thickness, Ratio of mobile charge
densities at VG1 and vg for different values of VG1, and mobile charge density
with respect to vg for 10nm and 15nm silicon thicknesses obtained by (10.13). 215
10.4 Electron mobility given by (10.15) and (10.17) for an n-type junctionless double- gateMOSFET)...... 217
10.5 The mobile charge density with respect to vg for 10nm-silicon thickness ob- tained by (10.13) and (10.16) in junctionless double-gate MOSFETs...... 218
10.6 Electron mobility given by (10.15) and (10.17) for an n-type junctionless double- gateMOSFET)...... 219
11.1TheEPFL-JL1.0modules...... 222
11.2TheEPFL-JL1.0modules...... 225
19 List of Figures
11.3 Drain current versus gate voltage for various drain potentials and versus drain voltage for different gate potentials ...... 226
11.4 Small signal equivalent circuit used in the EPFL-JL 1.0 model ...... 227
11.5 A common-source amplifier based on n-type junctionless FETs...... 227
11.6 The junctionless FETs inverter...... 228
A.1 Schematic view of an n-type double-gate junction FET (JFET) and its equivalent (an n-type double-gate junctionless FET with an infinite oxide capacitance). . . 236
A.2 Schematic view of an n-type double-gate junction FET and its equivalent (an n-type double-gate junctionless FET with an infinite oxide capacitance). . . . . 237
20 List of Tables
2.1 List of physical quantities used in Chapter 2 for junctionless FETs ...... 44
3.1 Correspondence between junctionless nanowire physical parameters and equiv- alent junctionless double-gate FET model parameters...... 81
7.1 Correspondence between nanowire physical parameters and equivalent double- gate FET model parameters...... 172
11.1 The transistor parameters assigned to EPFL-JL 1.0 model ...... 223
11.2 values and the descriptions of the various physical constants used in EPFL-JL 1.0 model...... 224
11.3 combination of the on-state and the off -state of eight switches depending on
VGS as a control signal and comparing to the flat-band gate voltage in EPFL-JL 1.0 model...... 225
21
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