Modeling Junctionless Metal-Oxide-Semiconductor Field- Effect Transistor THÈSE NO 6811 (2015) PRÉSENTÉE LE 27 NOVEMBRE 2015 À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR GROUPE DE SCIENTIFIQUES STI PROGRAMME DOCTORAL EN MICROSYSTÈMES ET MICROÉLECTRONIQUE ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES PAR Farzan JAZAERI acceptée sur proposition du jury: Prof. M. A. Ionescu, président du jury Dr J.-M. Sallese, directeur de thèse Prof. G. Baccarani, rapporteur Prof. B. Iniguez, rapporteur Prof. Y. Leblebici, rapporteur Suisse 2015 Simplicity is the ultimate sophistication. —LeonardodaVinci To my dear parents who made my education possible, through their sacrifice, devotion, and support. To my brothers you will always be in my heart no matter how far I go. Acknowledgements Scientific research is often a collaborative endeavor, and the work presented in this dissertation is certainly no exception. During the past four years I have had the pleasure of working with a number of bright and enthusiastic people that I would like to mention here. First of all, it has been my honor and privilege to have had Dr. Jean-Michel Sallese as my research advisor during my graduate career at EPFL and I would like to express my utmost gratitude to him for his generous help and support throughout the course of this work. He taught me not only his unsurpassed technical knowledge, but his exceptional professionalism and his sincere attitude towards scientific research. He impressed me very much by his humility, responsibility and strict attitude in training students. He always provided timely and warm encouragement and support in difficult times. He was never hesitant to get involved with details of my calculations and I am grateful for that. Jean-Michel gave me not only the supervision of my research but also the guidance on my future life. His great knowledge in semiconductor physics motivated my devotion to the field of semiconductor devices. He was a role model for me; a great friend put things in proper perspective, and contributed to my positive attitude. I would especially like to thank him for giving me freedom to pursue my research interests. Indeed, without his invaluable guidance, and encouragement, this work could not have come to fruition. It is my pleasure to thank to the professors from my doctoral and exam commission: Prof. Giorgio Baccarani, Prof. Benjamin Iniguez, Prof. Yusef Leblebici, and Prof. Adrian M. Ionescu. v Acknowledgements I appreciate the time they have taken to participate in these crucial last steps of my PhD and also their insightful advices. I must say thanks to Dr. Wladek Grabinski and Dr. Adil Koukab for sharing their invaluable experiences and encouragements. I wish to thank Dr. Didier Bouvet for his friendly and patient support during the cleanroom fabrication processes. I feel very lucky to have had the opportunity to explore my academic interests for the past four years at EPFL. Indeed, my life in Lausanne would not have been wonderful and fulfilling without many of my friends who I met during the time in Lausanne. I would especially like to thank Dr. Maria-Anna Chalkiadaki and Dr. Lucian Barbut, and who made it possible. I would thank my good friends and colleagues. It was very enjoyable working with nice friends. We stablished friendships in this big family. I really want to send my thanks and best wishes to them: Dr. Antonios Bazigos, Dr. Anurag Mangla, Dr. Mehrad Azizighannad, Dr. Omid Talebi, Dr. Naser Khosropour, Dr. Sarah Rafiee, Mariana Barbut, Dr. José Luis Padilla, Dr. Ehsan Kazemi, Dr. Mani Bastani Parizi, Dr. Georgios Lilis, Lauriane Richer, Ramona Rosu, and Silvia Puche. I would like to thank all of my colleagues for many valuable discussions and helpful suggestions. I am very thankful to have had the camaraderie and support of so many people in so many places. Thanks to Isabelle and Karin, our dear assistances for bureaucratic matters, and to Raymond Sutter, Marc Paster for IT and software support. The financial support for this work from Swiss National Science Foundation organization (SNF) is greatly appreciated. I would like to express appreciation to the people that helped me to complete this project. Last, but certainly not least, I am deeply grateful for never-ending love from my parents (Ferdos and Jamal) and my brothers; Dr. Farshid and Dr. Farzad. I owe more than words can describe to my parents. I would like to sincerely thank them for their support, sacrifices, and encouragement in the past 30 years which made all these possible. This work is dedicated to them. Lausanne,1st October 2015 Farzan Jazaeri vi Abstract Metal-oxide semiconductor (MOS) field-effect transistor (FET) scaling is following the predic- tion of the Moore’s law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap. In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. This dissertation focuses on the physics and modeling of nanoscale junctionless double-gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double-gate configuration as well as junctionless nanowires topologies will be presented. Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson-Boltzmann equation and on the drift- diffusion transport to derive charges and current in long-channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long-channel concept. This includes modeling short-channel effects 1 Abstract and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off -state currents. Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge-based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture. Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design-space tool with explicit links between silicon thickness and doping ensuring safe operation. Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law. Based on these developments, the EPFL-JL-model was implemented into Hspice platforms to be used by circuit designers. Key words: MOSFET, junctionless FET, nanowire FET, compact modeling, short-channel effects, Trans-capacitance, noise, CMOS scaling, mobility, design space, transient analysis, asymmetric double-gate MOSFET. 2 Résumé La miniaturisation du transistor à effet de champ de type Métal-Oxide-Semiconducteur (MOS) poursuit une miniaturisation prédite par la loi de Moore depuis 45 ans. Cette miniaturisation est une facteur clef qui permet à l’industrie de la microélectronique de satisfaire la demande constante pour des performances toujours plus exigeantes. Cependant, cette miniaturisation devient particulièrement compliquée au delà du nœud de 28 nm à causes des limitations en terme de procédé de fabrication et de performance du composant. Afin de parer à ce possible ralentissement, de nouvelles architectures non standards ont été introduites dans la ’roadmap’. Dans ce contexte, le transistor à effet de champ sans jonction, communément désigné par ’junction less FET’, représente un nouveau type de composant qui est théoriquement en mesure de satisfaire la miniaturisation de la technologie CMOS car il garantit un contrôle optimal par la grille, un faible courant de fuite, une mobilité accrue des porteurs de charge, tout en présentant des étapes de fabrication simplifiées. Cette thèse traite essentiellement de la modélisation de ces transistors ‘junctionless’ de type double-grille et nano cylindriques (‘nanowires’) en conservant une approche physique. La première partie discute les avantages et les inconvénients de cette nouvelle technologie tout en présentant les modéles qui ont été développés jusqu’à présent. Par la suite, la modélisation adopté dans ce travail sera exposée dans les différent chapitres. Le modèle développé est un modèle en charge qui se base sur l’équation de Poisson-Boltzmann et qui utilise le concept de drift and diffusion pour le transport des charges. Un modèle rigoureux du courant dans le canal du transistor est ainsi obtenu. Deux jeux de solutions apparaissent selon que le transistor opère en mode de déplétion ou d’accumulation. Il n’est introduit aucun paramètre d’ajustement, et le modèle prédit avec précision tous les modes opératoires. Au cours de ce travail, la modélisation a été étendue pour prendre en compte la plupart des phénomènes physiques tels que la modélisation des effets canaux courts aux dimension nanométriques et la modélisation du bruit blanc dans le canal avec la corrélation 3 Abstract avec le bruit de la grille.