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The WD9000 Pascal MICRO,ENGINE™ Microprocessor Chip Set

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The WD9000 Pascal MICRO,ENGINE™ Microprocessor Chip Set The WD9000 Pascal MICRO,ENGINE™ Microprocessor Chip Set FEATURES • Direct Exe9ution of Pascal Intermediate Code (P-Code) • High Level Language Programming with Assembly Language Efficiency • 16-Bit Stack-Based Architecture • Executes Full UCSD Pascal, Version 111.0 • Program Size to 128K Bytes • 3.0 MHz Four-Phase Clock • Four-Level Interrupt Structure • Hardware Multiply/Divide • Hardware Floating Point • Single and Multi-Byte Instructions Pascal MICROENGINE™ Five Chip Set • TTL Compatible Three-State Interface • Memory Mapped I/O The WD9000 Microprocessor includes: • P-Machine Architecture - implements the UCSD Version 111.0 P-Machine, an ideal architec­ DESCRIPTION ture (stack oriented) for execution of Pascal pro­ The WD9000 Microprocessor is a 16-bit MOS/LSI grams. This approach replaces the alternative of Chip Set that directly executes programs written software intepreters or compilation to architec­ in the Pascal programming language at speeds five tures less suited for Pascal. or more times greater than equivalent systems • Sixteen-Bit I/O and Data Paths for High Through­ using intepreters. The Chip Set consists of five put - all address, data and I/O paths are sixteen LSI com,ponents: bits wide. • Arithmetic Component - contains the arith­ • Stack Architecture for Reentrant and Recursive metic logic unit, microinstruction decode, Programs - all Pascal programs are reentrant register file, and paths to control processor and recursive with no performance penalty. operation. • High-Level Language Programming of I/O and • Control Processor - contains macroinstruc- , Interrupts - simple access to device and sys­ tion decode, portions of the control circuitry, tem control provided in the Pascal language. microinstruction counters, and I/O control logic. • Hardware Mu/tiply/Divide -:- 16-bit multiply and • MICROM Components - three high-speed, divide instructions. 512 x 22 bit, custom MICROMs implement P­ • Floating Point Hardware - execution of float­ Code instructions. ing pOint instructions using the proposed IEEE standard. • Four-Level Interrupt Structure - each level The MICROENGINE™ Microprocessor Chip Set is represents an interrupt priority. designed for a large range of applications which • TTL Compatible Three-State Interface - stand­ could gain from 16-bit throughput and/or direct Pas­ ard parts may be used to interface to the Chip Set. cal execution. Pascal is a high-level programming language which provides an environment conducive • Memory Mapped I/O - the language and Chip to structured software development. The WD9000 Set support memory mapped I/O, where I/O de­ Microprocessor Chip Set directly executes the Uni­ vices are accessed as memory locations. versity of California at San Diego (UCSD) Pascal • Suitable for RAM or RAM/ROM Configurations System, Version 111.0, which is widely used through­ - P-machine architecture is designed to sup­ out the industry on eight- and sixteen-bit port applications residing in RAM memory or in processors. a combination of RAM and ROM (or PROM). A Subsidiary of WESTERN DIGITAL BENEFITS • Transportability - programs written in the industry standard UCSD Pascal may be exe­ Use of the WD9000 Pascal MICROENGINE™ Micro­ cuted on other Pascal-based systems. processor Chip Set has significant benefits for the system designer: • Efficient Memory Utilization - since the P­ Machine is an ideal architecture for Pascal exe­ • High Performance - throughput of the 16-bit cution, memory utilization is equivalent to that CPU provides processing power needed for of software programmed in assembly language many applications. on other processors and less than on systems • Lower Software Development Cost - use of using interpreters or compilers operating on Pascal increases programmer productivity, architectures not optimized for Pascal. decreasing software development costs over· • System Reliability - reliability, the probability alternative approaches. These productivity in­ that programs will perform their intended func­ creases are the result of the language's high­ tion, is improved by extensive compiler error level nature, extensive error checking, auto­ checking. In addition, since Pascal programs matic' reentrancy and recursion. are simpler statements of the algorithm to be • Shortened Development Schedules - critical executed than the alternative tools, reliability software development schedules are shortened. is further enhanced. t!...otJ r~ 0 L : ~ -p LbIB ~ 0 z- P/1-Tr G.( 2./ ~I ' r1. rcf2.t.')r/l I 810 Z- B 12.- 5V +12V I +12V 8l'S Gi+rl G,D +rf .3 10 II INTERRUPT 12 LINES 13 } 3 ' MICR~MS CONTROL COMPUTE 512 X 22 CHIP REPLY + 5V RESET lACK SYSTEM DIN CONTROL > LINES > DOUT ~ ,> SYNC ~ BUSY ~04 02 W/A +5V ~- 03- 01 ~ +5V co "- COlI) '<1'(') N~ col'- COlI) '<I'M N~O ~~ 00 00 00 000 OJ CD CiiCii CiiCii CiiCii rnCIl CIlCIl CIlCIl CIlCIl CIlCIlCIl +12V :E :E :E:E :E:E :E:E :E:E :E:E :E:E :E:E :E:E:E 01 + 12 A A OJ'.YYv 01 Y" II) 02 02 N VVY rvvv- '"(') en 03 A 03 Cl Y"" + 5 ~~ 04 04 YYY Uvvv- CLK 50 -3MHZ GND ':'J N Cl !:: 03 01 DALOO ~ '-- ~ '- ~04 02 DAL01 ?==) 01 I-- '-- DAL02 DAL03 02 I-- ~ DAL04 6 03 t-- >===, DAL05 >===, L 041--- DAL06 3.0MHZ f:===) DATA CHIP DALO? j ~ DALOS f:===) GND DAL09 f:===) DAL10 ?==) DAL11 ~ DAL12 ~ DAL13 f:===) ~O DAL14 USED FOR DAL15 ~ MICROM TO c::=::> MICROM COMMUNICATION I I I GND +5V +12V TYPICAL WD9000 CPU CIRCUIT 2 PIN ASSIGNMENTS 03 by the Processor every time READ or WRITE instructions are taking place. Whenever the BUSY The following are pin assignments for the Pascal MICRO· signal is found to be on, the Processor enters a ENGINETM MieroproeessorChip Set: WAIT state inhibiting any access operation from DATA CHIP PIN ASSIGNMENTS taking place. The Processor will resume normal Ab operation as soon as BUSY is turned off. PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL NO. NO. NO. NO. 1 03 11 DAL08 21 02 31 MIB07 CS CS (Chip Select) is always connected to +5 Volts. 2 VBB 12 DAL09 22 WAIT 32 MIB06 3 DALOO 13 DAL10 23 MIB15 33 MIB05 4 DAL01 14 DAL11 24 MIB14 34 lVfrn04 01-04 CLOCK CYCLES 5 DAL02 15 DAL12 25 MIB13 35 MIB03 These cycles may be generated by the WD2143 6 DAL03 16 DAL13 26 MIB12 36 MIB02 Clock Chip or by external user supplied circuitry. 7 DAL04 17 DAL14 27 MIB11 37 MIB01 Cycles occur every 83 nanoseconds,· yielding a 333 nanosecond interval between each occurrence 8 DAL05 18 DAL15 28 MIB10 38 'fJTBOO of a given clock. 9 DAL06 19 Vss 29 MIB09 39 Vee 10 DAL07 20 04 30 MIB08 40 01 COMPUTE (TTL) CONTROL CHIP PIN ASSIGNMENTS /-\5 The processor examines COMPUTE during every PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 01 to determine whether or not it should execute NO. NO. NO. NO. the present microinstruction. In the case of a two cycle instruction, COMPUTE need be high only 1 03 11 MIB16 21 02 31 MIB07 during 01 of the first cycle. Among other things, 2 VBB 12 REPLY 22 Vee 32 MIB06 COMPUTE may be used to control single stepping 3 13 13 WAIT 23 MIB15 33 MIB05 of microinstructions. This line should not be 4 12 14 DOUT 24 MIB14 34 MIB04 confused with the WAIT signal on the MIS bus. 5 11 15 W/R 25 MIB13 35 MIB03 6 10 16 lACK 26 MIB12 36 MIB02 DAL OO-DAL 15 (TTL) 7 MIB17 17 SYNC 27 MIB11 37 MIB01 Data/Address Lines, used to transfer addresses 8 BUSY 18 DIN 28 MIB10 38 MIBOO· and data from the processor and receive data into the processor. Signals are logical true data. 9 COMPUTE 19 Vss 29 Mi'B59 39 Veo 10 RESET 10 04 30 MIB08 40 01 DIN (TTL) MICROM CHIP PIN ASSIGNMENTS The DATA-IN (DIN) is a Control signal from the PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL Processor to cause the address unit to gate its NO. NO. NO. NO. Read data on the Data lines. It is made high at the 1 03 11 MIB16 21 02 31 MIB06 time the address is removed from the lines, or one cycle after the SYNC is made high (the second 2 V 12 MIB17 22 BB Vee 32 MIB05 02 of the INPUT) and is a function of the READ 3 NC 13 MIB18 23 CS 33 MIB04 instruction. The DATA-IN is made low at the end 4 NC 14 NC 24 NC 34 MIB03 of the Input Byte or Input Word instruction or 5 NC 15 NC 25 NC 35 MIB02 when SYNC is made low. This signal can be used to control the enabl i ng of external TTL Tri-State 6 NC 16 NC 26 MIB11 36 NC Bus Driver/Receivers. 7 MIB15 17 NC 27 MIB10 37 MIB01 8 MIB14 18 NC 28 MIB09 38 MIBOO DOUT(TTL) 9 MIB13 19 Vss 29 MIB08 39 Voo 10 MIB12 20 04 30 MIB07 40 01 The DATA-OUT (DOUT)is a Control signal from the Processor which is made high at the same time as the Write data (01 following the OUTPUT) is placed PIN FUNCTIONS on the DAL bus by the Processor. It remains high . The following describes the function of each pin: for the duration of the OUTPUT instruction, dropping one phase before the data is taken off BUSY (TTL) the DAL bus. The BUSY is a Control signal from an external unit to the Processor requesting access to the bus. The signal can be used by a DMA unit to access lACK (TTL) the memory. The BUSY signal is interrogated at The lACK is a Control signal from the Processor 3 which signifies that the Processor is responding and also to transfer the results of conditional to an Interrupt. This signal is made high at the jump tests from the Data Chip to the Control Chip.
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