Suggested PCB Land Pattern Designs for Leaded and Leadless Packages, and Surface-Mount Guidelines for Leadless Packages
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Smd Packages
TEL JHB : (011) 493-9307 MANTECH CAPE : (021) 535-3150 KZN : (031) 309-7692 ELECTRONICS FAX : (011) 493-9319 International Components Distributor [email protected] www.mantech.co.za SMD PACKAGES Contents 1. Two-terminal packages 2. Three-terminal packages 3. Packages with four or more terminals Surface-mount components are usually smaller than their counterparts with leads, and are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes (the leading standardisation body is JEDEC). These include: _______________________________________________________________________________________________ PO BOX 260455 - EXCOM - 2023 - SOUTH AFRICA Two-terminal packages o Rectangular passive components (mostly resistors and capacitors): . 01005 (0402 metric) : 0.016" × 0.008" (0.4 mm × 0.2 mm) Typical power rating for resistors 1/32 Watt . 0201 (0603 metric) : 0.024" × 0.012" (0.6 mm × 0.3 mm) Typical power rating for resistors 1/20 Watt . 0402 (1005 metric) : 0.04" × 0.02" (1.0 mm × 0.5 mm) Typical power rating for resistors 1/16 Watt . 0603 (1608 metric) : 0.063" × 0.031" (1.6 mm × 0.8 mm) Typical power rating for resistors 1/16 Watt . 0805 (2012 metric) : 0.08" × 0.05" (2.0 mm × 1.25 mm) Typical power rating for resistors 1/10 or 1/8 Watt . 1206 (3216 metric) : 0.126" × 0.063" (3.2 mm × 1.6 mm) Typical power rating for resistors 1/4 Watt . 1210 (3225 metric) : 0.126" × 0.1" (3.2 mm × 2.5 mm) Typical power rating for resistors 1/2 Watt . 1806 (4516 metric) : 0.177" × 0.063" (4.5 mm × 1.6 mm) . -
Land Grid Array (LGA) Package Rework
Freescale Semiconductor Document Number: AN3241 Application Note Rev. 1.0, 10/2009 Land Grid Array (LGA) Package Rework 1 Introduction Contents 1 Introduction . 1 This application note describes rework considerations 2 What is LGA? . 3 for the Land Grid Array (LGA) style package. 3 LGA Rework . 5 4 Package Removal . 6 Freescale has introduced radio frequency (RF) modules 5 LGA Reliability . 14 such as the MC1320x and MC1321x in LGA packages as 6 References . 14 an alternative package to ball grid array (BGA). The LGA packages reduce the amounts of lead in finished products and are Reduction of Hazardous Substances (RoHS) compliant, optimized for improved radio-frequency (RF) performance for wireless applications, and/or reduce the overall height of the package by eliminating the stand-off height associated with BGA balls. For assistance with any questions about the information contained in this note or for more details about the MC1320x and MC1321x devices, visit www.freescale.com/802154. or contact the appropriate product applications team. © Freescale Semiconductor, Inc., 2009. All rights reserved. Introduction 1.1 Acronyms and Abbreviations BGA Ball Grid Array BT Bismaleimide Triazine CBGA Ceramic Ball Grid Array CTE Coefficient of Thermal Expansion EU European Union ESD Electrostatic Discharge HCTE High Coefficient of Thermal Expansion HDI High Density Interconnect LGA Land Grid Array LTCC Low Temperature Co-fired Ceramic MSLn Moisture Sensitivity Level n NSMD Non-Solder Mask Defined OSP Organic Solderability Protectant PCB Printed Circuit Board RF Radio Frequency RoHS Reduction of Hazardous Substances SMD Solder Mask Defined SMT Surface Mount Technology Land Grid Array (LGA) Package Rework Application Note, Rev. -
EE Concierge Style Guide PCB Layout and Component Creation
EE Concierge Style Guide PCB Layout and Component Creation For more information or component creation services visit EEConcierge.com Version 1.2 For more information or component creation services visit EEConcierge.com Table of Contents Introduction Checklist: What a perfect part looks like Style Guide: Pins Number of Pins Pin Numbers Pin Names Pin Types Style Guide: Attributes Step by Step Walkthrough Style Guide: Symbols Step by Step Walkthrough Headers Pin Organization Style Guide: Footprints General Tips Component Origin Layers Top Component Top Package Outline Top Solder Mask Top Paste Mask Top Copper Top Courtyard Top Silkscreen Top Keepout Bottom Layers Mechanical Details, Rulers, Notes, Design Rules Hole Layer Hole Sizing Plated Through Holes TO-92 and Other Parts With Overlapping Holes/Pads Non Plated Through Holes (NPTH) Axial Components DIP Components Thermal Pads BGAs Additional Guidelines Common Mistakes Made Missing refdes (both symbol and footprint) For more information or component creation services visit EEConcierge.com Holes not big enough (exact size of the hole) The datasheet is for a different part No part number on IC schematic No keepouts (this came up with antennas) Ground or power pins on the top or bottom of a symbol No pin one marker (footprint) Footprints not centered Missing mechanical details or holes on the wrong layers Wrong number of pins Bad pin names Missing overbars or # or n in the pin name Marking pin one improperly Specific Guidelines for Axial Components Specific Guidelines for Radial Components -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
Electronic Materials and Components-Semiconductor Packages
Electronic materials and components-Semiconductor packages Semiconductor ‘back-end’ processes We will learn much more about semiconductor ‘back end’ processes in subsequent modules, but you need to understand at least something of the terminology and what is involved in turning a ‘chip’ into a finished package1. 1 It is always very dangerous to point people at sources of information on packaging, especially now that the wonderful Fullman site has disappeared. However, you might like to take a look at what a doctoral student can achieve at http://chenjian.virtualave.net/packaging. The starting point for semiconductors is the wafer, which contains a (very large) number of devices, separated by small gaps, and electrically isolated from each other as part of the processing. Starting with a blank wafer of extremely pure silicon, building up layers by deposition techniques, etching patterns, and implanting dopants into the silicon structure using high energy particles, the semiconductor ‘fab’ ships a wafer which is partially probe-tested, but needs terminations in order to communicate with the outside world. These ‘front end’ processes attract the headlines, but the back end of the pantomime horse is just as important! The ‘back end’ process consists of sawing the wafer into individual dice (the terms ‘chip’ and ‘die’ are equivalent), mounting the die on a lead-frame or other mount using conductive adhesive, and finally making fine wire connections to the top surface – this ‘wire bonding’ process uses gold and aluminium wires typically 25-33 µm in diameter. Because wires and semiconductor are relatively fragile and easy to contaminate, the die will then be protected in some way. -
Classification of Semiconductor Package
www.connect.co.jp www.jccherry.com Technical Data Classification of semiconductor package SIP ZIP Single In-line Package Zigzag In-line Package A package having leads on a single side of the body. A package having Zig-zag formed leads on a single side of the body. DIP PGA Dual In-line Package Pin Grid Array A package having leads in parallel rows A package having pins on top or bottom on two opposite sides of the body for face in a matrix layout of at least three through-hole insertion. rows and three columns. SDIP Shrink DIP A package which reduced the lead pitch of DIP. SOP SON Small Outline Package Small Outline Non-leaded Package A package having gull-wing-shaped leads A package having single-inline terminal on two opposite sides of the body. pads along two opposite edges of the bottom face. The terminal pads may or may not be exposed on the package sides. TSOP Thin SOP SOJ A package height of SOP exceeds 1.0 mm, Small Outline J-leaded Package and 1.2 mm or less. A package having J-shaped leads on two opposite sides of the body. SSOP Shrink SOP A package which reduced the lead pitch of SOP. 50-01 www.connect.co.jp www.jccherry.com Classification of semiconductor package QFP LGA Quad Flat Package Land Grid Array A package having gull-wing-shaped leads A package having lands on top or bottom on four sides of the body. face in a matrix of at least three rows and three columns. -
Building Your Prototype
Building Your Prototype Prototype Construction Techniques Part Numbers Package Types Specification Sheets Schematic Diagrams Practical Advice T. Grotjohn, [email protected] Prototype Construction Techniques 1) Protoboard Use DIP components Keep your wires neat and color coded Prone to bad connections Maximum operating speed: ~ few MHz 2) Wire Wrap Often done using wire wrap sockets on a vector board Use DIP components Wire used is good for digital signals Be careful with high current lines because the wire is small. Typical wire: 30 gauge 0.34 Ω/m 28 gauge 0.21 Ω/m 3) Soldered Board Single solder points board Tied solder points board (Your mini project #1) PCB: printed circuit board PCB can be made for ECE 480 projects in the ECE Shop: See the shop’s web page. (Also see the next page) . Printed Circuit Board System General Information T-Tech Protyping Machine ECE 482 Student Project Design Department of Electrical and Computer Engineering, 1999 Michigan State University, East Lansing, Michigan, USA Part Numbers Typical Part Number: DM8095N Prefix: Indicates the manufacture of the part. See two pages in Attachment 1. Suffixes: Indicates temperature range: “military”, “industrial”, “commercial” Also the suffixes are used to indicate package types. The ECE shop deals most often with the following electronic part suppliers. Allied Electronics (www.alliedelec.com) Digi Key (www.digikey.com) Newark Electronics (www.newark.com) For other (non-electronic) supplies, suppliers often used are Grainger (www.grainger.com) McMaster Carr (www.mcmaster.com) Package Types DIP: Dual Inline Package Easiest to use. Works in protoboards, solder boards, wire wrapping, easiest to solder components to PCB This is your choice for ECE 480. -
(12) United States Patent (10) Patent No.: US 6,236,223 B1 Brady Et Al
USOO6236223B1 (12) United States Patent (10) Patent No.: US 6,236,223 B1 Brady et al. (45) Date of Patent: May 22, 2001 (54) METHOD AND APPARATUS FOR WIRELESS O 527 321 2/1993 (EP). RADIO FREQUENCY TESTING OF RFID O 646 983 4/1995 (EP). INTEGRATED CIRCUITS WO 98/16070 4/1998 (WO). (75) Inventors: Michael John Brady, Brewster; OTHER PUBLICATIONS Dah-Weih Duan, Yorktown, both of NY (US) “RF Measurements On SIEGET Bipolar Transistors: Pre dicting Performance Straight From The Wafer, By: Jakob (73) Assignee: Intermec IP Corp., Woodland Hills, Huber and Gerhard Lohninger: XP000598992 Applications CA (US) Discrete Semiconductors Mar. 1, 1996, pp. 34-36. (*) Notice: Subject to any disclaimer, the term of this “Multifunction Credit Card Package”, IBM Technical Dis patent is extended or adjusted under 35 closure Bulletin, vol. 38, No. 08, Aug. 1995, p. 17. U.S.C. 154(b) by 0 days. “A Low-Power CMOS Integrated Circuit for Field-Pow ered Radio Frequency Identification Tag”. By Friedman et al., 1997 IEEE International Solid State Circuits Confer (21) Appl. No.: 09/247,900 ence, Paper SA 17.5, pp. 294, 295, 474. (22) Filed: Feb. 10, 1999 * cited by examiner Related U.S. Application Data (60) Provisional application No. 60/107.593, filed on Nov. 9, 1998. Primary Examiner Safet Metahic ASSistant Examiner-E PLeRoux (51) Int. Cl." ................................................. G01R 31/26 (74) Attorney, Agent, or Firm-O'Melveny & Myers (52) U.S. Cl. .............................................................. 324/765 (58) Field of Search ... ... 324/754, 72.5, (57) ABSTRACT 324/764, 601, 605, 763, 765, 158 P, 752; A method and apparatus for wireless radio frequency (RF) 713/189, 168; 714/733, 30; 370/225, 390, testing of radio frequency identification integrated circuits 400; 361/777, 774, 780; 174/260, 261; (RFIDIC) is disclosed. -
501-5736 Lever Actuated Land Grid Array 1207 Position Socket ( Socket
Lever Actuated Land Grid Array 1207 Qualification test report Position Socket 501-5736 ( Socket F 1207 ) th 25 SEP 2006 Rev.B 1. Introduction 1.1 Testing was performed on the LGA1207 socket to determine if it meets the requirements of product specification 108-78375 1.2 Scope This report covers the electrical, mechanical and environmental performance requirements of the LGA1207 socket. 1.3 Product description LGA1207 socket has arrayed contacts and solder to printed circuit board (PCB). The socket is used by compressing its contacts to the arrayed CPU land in the normal direction of the PCB. The CPU lands are arrayed with same grid pitch to the socket and has gold plating finish on the surface. LGA1207 socket is actuated by the lever and generates required compression force by the back plate attach to the bottom side of the PCB and the socket actuation mechanism. 1.4 Conclusion 1.2 This test report confirmed that Tyco socket F 1207 satisfied the requirements of the product specification of 108-78375 Rev.A 1.5 Test samples Samples were taken randomly from current production. The following samples were used : Part Number Description LF-LGA1207 socket ( Lead free ) 0-1871554-1 Right / U-lever shape Leaded-LGA1207 socket ( Leaded ) 0-1871554-2 Right / U-lever shape Fig. 1 TYCO Electronics AMP K.K. : Tel 044-844-8079 Fax 044-812-3203 1 of 17 Copyright 2000 by Tyco Electronics AMP K.K. All Right Reserved. RESTRICTED TO AMD Lever Actuated Land Grid Array 1207 Qualification test report Position Socket ( Socket F 1207 ) 501-5736 2. -
Ball Grid Array (BGA) Packaging 14
Ball Grid Array (BGA) Packaging 14 14.1 Introduction The plastic ball grid array (PBGA) has become one of the most popular packaging alternatives for high I/O devices in the industry. Its advantages over other high leadcount (greater than ~208 leads) packages are many. Having no leads to bend, the PBGA has greatly reduced coplanarity problems and minimized handling issues. During reflow the solder balls are self-centering (up to 50% off the pad), thus reducing placement problems during surface mount. Normally, because of the larger ball pitch (typically 1.27 mm) of a BGA over a QFP or PQFP, the overall package and board assembly yields can be better. From a performance perspective, the thermal and electrical characteristics can be better than that of conventional QFPs or PQFPs. The PBGA has an improved design-to-produc- tion cycle time and can also be used in few-chip-package (FCPs) and multi-chip modules (MCMs) configurations. BGAs are available in a variety of types, ranging from plastic overmolded BGAs called PBGAs, to flex tape BGAs (TBGAs), high thermal metal top BGAs with low profiles (HL- PBGAs), and high thermal BGAs (H-PBGAs). The H-PBGA family includes Intel's latest packaging technology - the Flip Chip (FC)-style, H-PB- GA. The FC-style, H-PBGA component uses a Controlled Collapse Chip Connect die packaged in an Organic Land Grid Array (OLGA) substrate. In addition to the typical advantages of PBGA pack- ages, the FC-style H-PBGA provides multiple, low-inductance connections from chip to package, as well as, die size and cost benefits. -
2 LGA1366 Socket
Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series and LGA1366 Socket Thermal and Mechanical Design Guide March 2011 Document Number: 320837-005 2 Thermal and Mechanical Design Guide INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. -
Surface Mount • Chips, Melfs & Sots Introduction
® Association Connecting Electronics Industries DRM-18H (G) Global License This PDF document is licensed for simultaneous usage on every computer throughout all company facilities and locations. Global License files may be opened, copied or downloaded onto individual computers, or over computer networks, intranets, internet or web. Appropriate security measures and policies must be in place to prevent access to this PDF version of the IPC-DRM-18H by anyone from outside the licensed company. DEMO ONLY Version This is a promotional sample of the IPC Training and Reference Guide — DRM-18H / PDF Version. Please do not use this SAMPLE for training or reference purposes. IPC is a not-for-profit association for the electronics industry. Please respect our copyright. You may order printed or PDF versions of DRM-18H from IPC at: www.ipctraining.org, [email protected], or call (847) 597-2862. Table of Contents Terminology Surface Mount • CHIPs, MELFs & SOTs Introduction ......................... 2 Chip Components ....................... 39 Through Hole vs. Surface Mount ....... 3 Chip Components/Resistor .............. 40 Through Hole Leads ................ 3, 4 Chip Components/Capacitor ............. 41 Surface Mount Leadless .............. 4 Tantalum Capacitor ..................... 42 Surface Mount Leaded ............... 5 MELF ................................. 43 Component Packaging ................ 6 SOT/SOD .............................. 44 Identifying Components ............... 7 DPAK.................................. 45 Lead-Free Components