Top-Down Design of the 8080 CPU in VHDL

Rep ort TopDown Design Of the CPU

In VHDL

Shengxin Wang Nick Kanop oulos and Kishor S Trivedi

July

Contents

Intro duction

TopDown Design In Digital Systems

The Abstraction Hierarchy : : : : : : : : : : : : : : : : : : : :

TopDown Design Pro cess With Logic Synthesis : : : : : : : :

Imp ortant Features of VHDL

Classes of Ob jects : : : : : : : : : : : : : : : : : : : : : : : : :

Attributes : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

Mo deling concurrency : : : : : : : : : : : : : : : : : : : : : :

Signal Assignment : : : : : : : : : : : : : : : : : : : : : : : :

Pro cess Mo del Graph : : : : : : : : : : : : : : : : : : : : : : :

Guidelines for synthesizable VHDL : : : : : : : : : : : : : : :

The Central Pro cessing Unit

Architecture of the Central Pro cessing Unit : : : : : : :

The Pro cessor Cycle : : : : : : : : : : : : : : : : : : : :

VHDL Design of the CPU

Pro cess Mo del Graph of the CPU : : : : : : : : : : : : :

Mo del of the Control Unit : : : : : : : : : : : : : : : : : : : :

Mo del of the InstructionDeco der : : : : : : : : : : : : : : : : :

Mo del of the Register Array : : : : : : : : : : : : : : : : : : :

Mo del of the ALU Unit : : : : : : : : : : : : : : : : : : : : : :

Simulation and Synthesis of the VHDL mo del of the

CPU

Mo del test vectors and input les : : : : : : : : : : : : : : : :

Simulation Results : : : : : : : : : : : : : : : : : : : : : : : :

Synthesis and Optimization of the VHDL design : : : : : : : :

VHDL Mo deling Summary : : : : : : : : : : : : : : : : : : : :

List of Figures

Abstraction levels in digital systems : : : : : : : : : : : : : : :

TopDown Design Pro cess With Logic Synthesis : : : : : : : :

Logic blo ck structure : : : : : : : : : : : : : : : : : : : : : : :

Three concurrent pro cesses : : : : : : : : : : : : : : : : : : : :

Pro cess Mo del Graph : : : : : : : : : : : : : : : : : : : : : : :

CPU Functional Blo ck Diagram : : : : : : : : : : : : : :

TwoPhase Nonoverlapping Clo ck : : : : : : : : : : : : : : : :

CPU Pro cess Mo del Graph : : : : : : : : : : : : : : : : :

CPU State Transition Diagram : : : : : : : : : : : : : : : : :

The Waveforms of the External Control Signals : : : : : : : :

TopSheet of the Synthesized Schematics of CPU Mo del :

One Sample GateLevel Sheet : : : : : : : : : : : : : : : : : :

Intro duction

One of the main directions of mo dern CAD environments is the develop

ment of metho dologies and to ols that supp ort a topdown hierarchical design

paradigm This direction is necessitated in part by the design complexities

encountered by designers to day and by the need to share design data bases

among large design teams One highly touted to ol in this pro cess is the

VHSIC Hardware Description Language VHDL The main reason for the

p opularity of VHDL is the fact that it has one of the b est sets of constructs

for hardware b ehavior mo deling

Early developments of VHDL to ols were fo cused primarily on simulation

and were not part of integrated to ol environments Lately new generations

of to ols have emerged that oer an integrated environment where a design

captured hierarchically with VHDL can b e executed from functional b ehavior

to circuit layout

The ob jectives of this pro ject were two fold First we intended to demon

strate a topdown hierarchical design metho dology based on VHDL with a

b enchmark of substantial complexity This was accomplished with the design

of the Intel CPU which was p erformed in a topdown fashion starting

at the b ehavior level and ending with layout for a targeted CMOS technology

The second ob jective was to develop a hierarchical b ehavioral and structural

b enchmark mo del which can b e used to p erform faultinjection exp eriments

that can b e used to validate fault secure features of hardware structures The

b enchmark is currently used in this capacity for the continuation of this

pro ject which is also sp onsored in part by CACC

The choice of the CPU for this pro ject is based simply on the avail

ability of structural information in the public domain for this design The

design metho dology demonstrated and the fault injection metho dology b eing

develop ed are indep endent of the particular circuit under design However

any design attempted using the metho dology presented in this pro ject should

assume the availability of somelevel of structural design information at the

The outcome of this pro ject is a topdown hierarchical b ehavioralstructural

mo del and an assembler for the CPU all develop ed in VHDL The mo del

was veried and validated through simulations at all levels and with the en

tire instruction set All mo del development was p erformed with Mentor

Graphics to ols and the develop ed VHDL mo del can b e used by interested

users as a macro cell in the Mentor database

TopDown Design In Digital Systems

With the increasing complexity of VLSI circuits and timetomarket pressure

the b ottomup design metho dologies of the s are no longer viable solutions

b ecause they are tedious slow and error prone A higher level topdown

synthesis approach is mandatory to meet to days design needs A design

can b e quickly dened using VHDL and veried through simulation Once

functionality is veried synthesis can rapidly move the design to the gate

level layout automating a task that previously was tedious and errorprone

In addition with a topdown design metho d employing VHDL synthesis

functional changes can b e made rapidly and veried through simulation

The Abstraction Hierarchy

Using VHDL designs can b e describ ed in topdown fashion through varying

levels of abstraction The levels of abstraction in digital systems are shown

in Figure They are the chip level the register level the gate level the

circuit level and the silicon level Note that the abstraction hierarchy has

a pyramidal shap e The broadening of the pyramid as one moves to lower

levels represents the increasing amount of detail that must b e managed in

representing a VLSI device at that level

Abstraction can b e expressed in two domains which are now dened as

follows

Structural domain a domain in which a comp onent is describ ed in

terms of an interconnection of more primitive comp onents

Behavioral domain a domain in which a comp onent is describ ed by

dening its inputoutput resp onse by means of a pro cedure

CHIP

GATE

CIRCUIT

SILICON

Figure Abstraction levels in digital systems

TopDown Design Pro cess With Logic Synthesis

The ow chart in Figure shows the topdown design pro cess and the Mentor

Graphics to ols that can b e used to implement this pro cess The design

pro cess includes the following steps

Dene the design sp ecication and build a blo ck diagram by partition

ing the functionality

Build the functional mo del for each toplevel comp onent The toplevel

is the top level of what will b e a multilevel design hierarchy And one

can describ e each comp onent in the toplevel using a VHDL mo del

schematics or a combination of b oth The VHDL mo dels need to b e

synthesizable RTLlevel mo dels This mo del creation in the Mentor

Graphics CAD framework can b e p erformed using Design Architect or

just a plain editor

Verify the functionality of the toplevel mo del by simulation If any

problems are revealed by simulation the VHDL mo del is edited and DEFINE THE DESIGN SPECIFICATION

PARTITION FUNCTIONALITY (BLOCK DIAGRAM)

| M DESIGN Enter DEVELOP Input | E VHDL ARCHITECT or | Schematics description N MODEL EDITOR | T | O | R Refine FUNCTIONAL QUICKSIM II | SIMULATION | C | A | D | SYNTHESIS/ AUTOLOGIC OPTIMIZATION | F | R | A | M Refine QUICKSIM II FUNCTIONAL | E VERIFICATION | W | O | R | LAYOUT and K Detailed Analysis |

Figure TopDown Design Pro cess With Logic Synthesis

corrected QuickSim Logic Simulator of Mentor Graphics oers the

capabilities needed to p erform the verication

Once the VHDL design is mo deled correctly and veried the Auto

logic Synthesis to ol for Mentor Graphics environment can b e used to

synthesize and optimize the design

Verify the b ehavior of the synthesized gatelevel design to determine

whether the synthesized design op erates correctly Again Quicksim is

used to simulate the design

The pro cess of developing a synthesizable VHDL mo del in step ab ove in

cludes the following steps

Develop an abstract b ehavioral VHDL mo del

Verify the abstract b ehavior of the mo del

Decomp ose the b ehavioral mo del into a synthesizable RTLlevel mo del

Verify the b ehavior of the rened mo del

Imp ortant Features of VHDL

TopDown design requires a common medium a requirement satised by

the VHDL language The basic descriptions of the syntax and constructs

of VHDL could b e found in many publications Some imp ortant

features of VHDL make it very eective for mo deling a logic design These

features are briey describ ed to provide context for the pro ject describ ed in

this rep ort

Classes of Ob jects

There are three classes of ob jects in VHDL constants variables and signals

An ob ject is created when it is declared The dierence b etween signals

and variables is that signals have a time dimension and direct hardware

corresp ondence

Attributes

Signal attributes are particularly imp ortant in mo deling Some examples are

SLAST VALUE is the previous value of S immediatedly b efore the last

change of S It is very useful for checking changes in a signal

SSTABLET is of typ e BOOLEAN It is true if S has b een stable for

last T time units

SDELAYEDT is the value of S T time units earlier

Another useful set of attributes are those asso ciated with arrays For exam

ple supp ose that an array variable was dened as follows

VECTOR to variable A BIT

Then the following attributes can b e indicated

Attribute Value

ARANGE to

ALEFT

ARIGHT

Mo deling concurrency

The mo deling of logic circuits has a requirement that is not shared by many

other mo deling applications that is the mo del must include provision for

concurrency of execution This is b ecause logic signals ow in parallel Fig

illustrates this concept Three logic blo cks are shown If one assumes that

input set and set are activated simultaneously logic blo cks and will

b e activated together Logic blo ck will b e activated as so on as either of

the outputs from logic blo ck Z or from logic blo ck Z change While

signals are propagating through logic blo ck new input signal changes can

b e propagating through blo ck and blo ck Thus signal ow can take place

through all blo cks simultaneously

INPUT

LOGIC BLOCK

SET

OUTPUT

LOGIC BLOCK

INPUT

LOGIC BLOCK

SET

Figure Logic blo ck structure

BLOCK LOGIC

Pro cess Input Set

b egin

end pro cess LOGIC BLOCK

LOGIC BLOCK

Pro cess Input Set

b egin

BLOCK end pro cess LOGIC

Pro cess Input Set

LOGIC BLOCK

b egin

BLOCK end pro cess LOGIC

Figure Three concurrent pro cesses

The hardware description language must have a mechanism for mo deling this

op eration In VHDL this requirement is handled by the pro cess construct

Each pro cess represents a blo ck of logic and all pro cesses execute in parallel

In VHDL a pro cess is activated when a signal in its sensitivity list changes

Figure shows the corresp onding VHDL pro cess structures for the logic blo ck

structure in Figure Note that the sensitivity list for the pro cess contains

in general the input signal set for the logic blo ck

Signal Assignment

Signals are used to transmit information b etween pro cesses A signal assign

ment statement is the ma jor imp ortant b ehavior statement in the language

There are two typ es of delay that can b e applied when assigning a timevalue

pair into the driver of a signal inertial and transp ort They have the follow

ing forms

Signal name < Value after timeexpression

Signal name < transp ort value after timeexpression

The rst assignment statement implies inertial delay Inertial delay is used

for devices that do not resp ond unless a value on its input p ersists for a

given amount of time and it is useful in mo deling devices that ignore spikes

on their inputs The default delay typ e in VHDL is inertial In the second

case the transp ort delay is sp ecied All changes on input will propagate to

output regardless of how long the changes stay at the new level Transp ort

delay would more likely b e employed at higher levels of abstraction

Pro cess Mo del Graph

A graph representation for highlevel mo dels is very useful b ecause it allows

us to mo del complex signal ow within such mo dels Pro cess mo del graphs

represent a partitioning of the mo del with each no de representing a function

This partitioning can also b e applied into the no des so a no de could b e

decomp osed into subfunctions such as no de D in the example ow graph

illustrated in Figure When mo deling in VHDL each such subfunction can

b e implemented by a VHDL pro cess Arcs are used to denote signal passage

b etween the pro cess mo dels Each arc is lab eled with a designator of the

signal which transmits from one pro cess to another

Output

Input

Figure Pro cess Mo del Graph

The pro cess mo del graph clearly illustrates the structure of a high level mo del

in the b ehavioral domain All mo dels are made more understandable by the

use of pro cess mo del graphs And this approach was eectively used to

illustrate clearly the signal ow very clearly in the VHDL design of the

CPU

Guidelines for synthesizable VHDL

There are certain guidelines that need to b e followed when using VHDL

for synthesis They encompass syntax requirements constructs constrains

mo deling metho ds and design metho ds These guidelines exist b ecause syn

thesizable VHDL is actually a large subset of the entire VHDL language

Some of these guidelines are summerized as follows

There could b e only one clo ck for each pro cess Attributes like EVENT

LAST VALUE are only for clo ck signals AUTOLOGIC VHDL sup

p orts clo cks dened of typ e bit b o olean qsim stateqim logic package

or std ulogcstd logic package

For an unclo cked pro cess when assigning to variables with conditional

assignments one needs to assign the variables all the time since they

are not going to b e synthesized into latches Otherwise unsynthesizable

internal state errors will b e issued But if the pro cess is a clo cked one

the variables are going to b e synthesized into ipops

Signals are not allowed to app ear on b oth sides of the assignments

in one pro cess unless they are in the sensitivity list of that pro cess

Otherwise unsynthesizable internal state errors will b e issued Care

must b e taken when adding signals to a pro cess sensitivity list since the

pro cess gets activated each time if there is any change in its sensitivity

list The b ehavior could then b e altered dramatically

INOUT p ort could only b e of the BUS typ e TriState Logic needs to

b e handled carefully There are two ways for handling tristate logic

One is to use the pro cess statement signals of the BUS kind and the

null waveform assignment When a signal is assigned a null waveform

it is disconnected

For more information ab out synthesizable VHDL refer to Autologic

VHDL Synthesis Guide by Mentor Graphics These constrains

have a very signicant eect on the mo dels design A synthesizable

mo del sometimes needs to b e reconstructed to guarantee that it has

the right b ehavior at the same time

The Central Pro cessing Unit

The central pro cessing unit CPU controls the functions p erformed by al

most all other comp onents of a computer system The CPU must b e able to

fetch instructions from memory deco de their binary contents and then exe

cute them In addition the CPU should b e able to recognize and resp ond to

certain external control signals such as INTERRUPT and WAIT requests

Figure CPU Functional Blo ck Diagram

Architecture of the Central Pro cessing Unit

Figure illustrates the functional blo cks within the CPU The

CPU consists of the following functional units

Arithmetic and logic unit ALU

Instruction register and control section

Bidirectional state data bus buer

The register section consists of a static RAM array organized into six bit

registers including the program counter PC stack p ointer SP and six

bit general purp ose registers arranged in pairs referred to as BC DE HL

and a temp orary register pair called W Z

The ALU contains an bit accumulator an bit temp orary accumulator

an bit temp orary register and a bit ag register with ags zero carry

sign parity and auxiliary carry Arithmetic logical and rotate op erations

are p erformed in the ALU ALU is fed by the temp orary register TMP

and the temp orary accumulator ACT and carry ipop The result of the

op eration can b e transferred to the internal bus or to the accumulator the

ALU also feeds the ag register

The rst byte of an instruction containing the op co de is loaded from the

internal bus to the bit instruction register during an instruction fetch The

contents of the instruction register are in turn available to the instruction

deco der The output of the deco der combined with various timing signals

from the control unit provides the control signals for the register array

ALU and data buer blo cks In addition the outputs from the instruction

deco der and external control signals feed the timing and state control unit

which generates the timing and state status signals

The control circuitry is the primary functional unit within a CPU Using

twophase clo ck inputs the control circuitry maintains the prop er sequence

of events required for any pro cessing task After an instruction is fetched

and deco ded the control circuitry issues the appropriate signals to units

b oth internal and external to the CPU for initiating the prop er pro cessing

action The control circuit is capable of resp onding to external signals such

as an INTERRUPT HOLD WAIT and RESET requests An interrupt re

quest will cause the control circuitry to temp orarily interrupt main program

execution jump to a sp ecial routine to service the interrupting device then

automatically return to the main program A wait request is often issued

by a memory or IO element that op erates slower than the CPU The con

trol circuitry will idle the CPU until the memory or IO p ort is ready with

the data Some p eripheral devices are capable of transferring information

to and from memory much faster than the pro cessor itself can accomplish

the transfer So the hold provision enables Direct Memory Access op erations

DMA which improves the throughput of a pro cessor The pro cessor must

temp orarily susp end its op eration during such a transfer to prevent con

icts that would arise if pro cessor and p eripheral device attempted to access

memory simultaneously A reset signal is used to startup the CPU

The Pro cessor Cycle

An instruction cycle is dened as the time required to fetch and execute an

instruction During the fetch a selected instruction is extracted from memory

and dep osited in the CPUs instruction register During the execution phase

the instruction is deco ded and translated into sp ecic pro cessing activities

Every instruction cycle consists of one to ve machine cycles A machine

cycle is required each time the CPU accesses the memory or an IO p ort

The following ten dierent typ es of machine cycles may o ccur within an

instruction cycle while no one instruction cycle will consist of more than ve

machine cycles

FETCHM

MEMORY READ

MEMORY WRITE

STACK READ

STACK WRITE

INPUT

OUTPUT

INTERRUPT

HALT

HALTINTERRUPT

The machine cycles that actually o ccur in a particular instruction cycle de

p end up on the kind of instruction executed However the rst machine cycle

in every instruction cycle is always a FETCH cycle Each machine cycle con

sists of three to ve states A state is the smallest unit of pro cessing activity

and is marked by a clo ck cycle

To summarize each clo ck p erio d marks a state three to ve states constitute

a machine cycle and one to ve machine cycles comprise an instruction cycle

VHDL Design of the CPU

Pro cess Mo del Graph of the CPU

The system VHDL mo del is interconnected by the following comp onents

ALU

State Control

Signal Control

InstructionDeco der

Phi

Figure TwoPhase Nonoverlapping Clo ck

In addition to those main pro cessor mo del comp onents it is necessary to

have a package that contains data typ es and functions that p erform signal

increment and decrement and signed s complement conversion

The CPU needs to b e driven by a twophase clo ck oscillator And the

two phases of the clo ck generated by the oscillator are nonoverlapping and are

lab eled as phi and phi Figure illustrates the two phase nonoverlapping

clo ck All pro cessing activities for the VHDL mo del of the are actually

referred to the events of these two clo ck phases

Figure shows the Pro cess Mo del Graph of the VHDL design of the

CPU In what follows the function of the VHDL mo del of the is ex

plained by referring to the Pro cess Mo del Graph in Figure It is the rising

edge of clo ck pulse phi that divides each machine cycle into states repre

sented by signal T in the Control State pro cess With this state signal at

the falling edge of clo ck phi the InstructionDeco der pro cess activates its

output signals such as enabling and multiplexing signals owing to ALU and

ST and other instruction ag signals FLAGS owing to Control Signal

pro cess The Control Signal pro cess then triggers the control signals such as

SYNC DBIN and others at the rising edge of clo ck pulse phi with all the

machine cycle status signals and instruction ag signals that have already

b een set by the InstructionDeco der pro cess at the falling edge of phi The

BUS bit is used to transmit data from ALU to Register Unit INTERNAL

and viceversa While the DATABUS bit is used to transmit data from

BUS reads in transmitted outside to CPU and viceversa The INTERNAL

data from registers in either ALU or Register Unit whenever its enabling

signals are set by the InstructionDeco der pro cess at the falling edge of phi

The DATABUS gets data from outside whenever the DBIN signal is set ALU

ALU_PROCESS

ACC_PROCESS ENABLE_SIGNALS ACT_PROCESS MUX_SIGNALS TEMP_PROCESS

CONTROL UNIT INSTRUCTION_DECODER INTERNAL_BUS_PROCESS

PHI1 DATABUS_PROCESS

INT CONTROL_STATE T INSTRUCTION HOLD PROCESS DATABUS M DECODER READY PROCESS CONTROL_SIGNAL FLAGS PROCESS ST INTERNAM_BuS PC_PROCESS SP_PROCESS SYNC DBIN INTE HLDA WAIT WRBAR WZ_PROCESS MUX_SIGNALS REGISTER_PROCESS

INC_DEC_PROCESS ENABLE_SIGNALS INTERNAL_BUS_PROCESS

DATABUS_PROCESS PHI2

REGISTER_FILE

Figure CPU Pro cess Mo del Graph

which is done by the Control Signal pro cess at the rising edge of phi All

the registers in b oth ALU and Register Unit actually read the transmitted

data at the falling edge of clo ck phi from INTERNAL BUS and DATABUS

where the data has b een available since the falling edge of clo ck phi or the

rising edge of clo ck phi The fact that these pro cessing activities get initi

ated at dierent states of the twophase clo ck guarantees the right order of

complex signal and data ow within the VHDL mo del of the CPU

Mo del of the Control Unit

The control unit is implemented as two pro cesses namely Control State and

Control Signal Control State is activated by the rising edge of phi which

controls the state transition and sets the control signals that are related to

the leading edge of phi Control Signal issues the external control signals

which need to b e activated at the rising edge of phi

The state transition diagram in Figure shows how the pro ceeds from

state to state in the course of a machine cycle The diagram also shows

how the external signal lines such as READY HOLD and INTERRUPT

are sampled during the machine cycle and how the conditions on these lines

may mo dify the basic transition sequence

Every machine cycle within an instruction cycle consists of three to ve active

states referred to as T T T T T or TW The SYNC signal identies

the rst state T in every machine cycle and is related to the leading edge

of phi The following transition o ccurs at the next phi pulse

During T the pro cessor sends an address to memory There is an op

p ortunity for the memory to request a WAIT This is done by pulling the

pro cessors READY line low The READY signal is sampled during T by

the pro cessor The pro cessor resp onds to a wait request by entering an idle

state TW at the end of T rather than pro ceeding directly to state T

This gives the memory time to resp ond to the addressed data request Entry

into TW state is indicated by a WAIT signal from the pro cessor acknowl

edging the memorys request And the lowtohigh transition on the WAIT

line is triggered by the rising edge of phi and o ccurs at the actual entry of

the TW state

Figure CPU State Transition Diagram

When a halt instruction HLT is executed the CPU enters the halt state

TWH after state T of the next machine cycle There are three ways for

the to exit the halt state

A high on the RESET line will always reset the to state T

RESET also clears the program counter

A HOLD input will cause the to enter the hold state When the

hold line go es low the reenters the halt on the rising edge of the

next phi clo ck

An interrupt will cause the to exit the HALT state and enter T

on the rising edge of the next phi clo ck NOTE The interrupt enable

INTE ag must b e set when the halt state is entered

The HOLD request line is sampled during T An internal hold latch is set

as a coincidence of the READY the HOLD and the phi signals Setting the

latch enables the subsequent rising edge of the phi clo ck to trigger the HLDA

hold acknowledgement signal output and the CPU enters the HOLD mo de

During an acknowledged HOLD the address and data busses are under con

trol of the p eripheral which originated the request enabling it to conduct

memory transfers without pro cessor intervention However internally cer

tain functions may continue If a HOLD REQUEST is acknowledged at T

and if the pro cessor is in the middle of a machine cycle which requires four

or more states to complete the CPU pro ceeds through T and T b efore

coming to a rest Not until the end of the machine cycle is reached will

pro cessing activities cease Internal pro cessing is thus p ermitted to overlap

the external DMA transfer improving the eciency of the system After the

HOLD REQUEST is terminated the HLDA output returns to a low level

following the leading edge of the next phi clo ck pulse

A p eripheral device can initiate an interrupt simply by driving the pro cessors

interrupt INT line high The interrupt INT request arriving during the

time that the interrupt enable line INTE is high acts in coincidence with

the phi clo ck to set the internal interrupt latch This event takes place

during the last state of the instruction cycle in which the request o ccurs thus

ensuring that any instruction in progress is completed b efore the interrupt

can b e pro cessed

All pro cessor machine cycles consist of at least three states T T and T If

the pro cessor has to wait for a resp onse from the p eripheral or the memory

with which it is communicating then the machine cycle may also contain

one or more TW state After the T state the pro cessor will terminate any

machine cycle as so on as its pro cessing activities are completed rather than

pro ceeding through the T and T states every time Thus the may

exit a machine cycle following the T the T or the T state and pro ceed

directly to the T state of the next machine cycle

In reference to other external control signals the DBIN signal is used ex

ternally to enable data transfer Machine cycles in which DBIN is available

include FETCH MEMORY READ STACK READ and INTERRUPT

DBIN is initiated by the rising edge of phi during T and terminated by the

corresp onding edge of phi during T Any TW phases intervening b etween

T and T will therefore extend DBIN by one or more clo ck p erio ds A

WRBAR output control signal is generated by the CPU for the syn

chronization of external transfers during those machine cycles in which the

pro cessor outputs data Those include MEMORY WRITE STACK WRITE

and OUTPUT The negativegoing leading edge of WRBAR is referenced to

the rising edge of the rst phi clo ck following T It remains low until re

triggered by the leading edge of phi during the state following T Note

that any TW states intervening b etween T and T at the output machine

cycle will necessarily extend WRBAR in much the same way that DBIN is

aected during data input op erations

Mo del of the InstructionDeco der

The InstructionDeco der pro cess is implemented by using three nested case

when statements for dierent machine cycles dierent states and dierent

instructions All the events that actually take place dep end on the kind of

instruction involved and on the particular state and machine cycle within

the instruction cycle Those events include issuing the appropriate enabling

and multiplexing signals for initiating pro cessing actions in the ALU and

ags that will ow into Control Signal pro cess The InstructionDeco der is

a clo cked pro cess in which all the events are activated at the falling edge of

clo ck phi with the state status signal initiated at the rising edge of phi by

the Control State pro cess So there is also enough time for the Control Signal

pro cess to get the instruction ag and machine cycle status signals from the

InstructionDeco der pro cess to activate the external control signals

Mo del of the Register Array

There are several pro cesses for the mo del of the register array unit

A pro cess to increment or decrement the Program Counter PC Stack

Pointer SP or other register pairs It is not a clo cked pro cess and

gets activated by any change in the pro cesss sensitivity list

The register pair pro cesses like Register Pro c PC MUX Pro c SP MUX Pro c

and WZ MUX Pro c which b ehave pretty much like the register hard

ware primitives The transferred data are read into the registers at the

falling edge of phi when their enabling signals are set to high by the

InstructionDeco der pro cess And their inputs are multiplexed accord

ing to the multiplexing signals triggered also by the InstructionDeco der

pro cess

The address latch pro cess ADDRESS LATCH Pro c is enabled to read

in the address if its enable signal is set to high and the pro cess gets

activated by any change in its sensitivity list

BUS and DATABUS are b oth TriState Logic mul The INTERNAL

tiply driven signals they need to b e resolved very carefully The IN

TERNAL BUS OUT Pro c and DATABUS OUT Pro c pro cesses assign

null waveform to the BUS kind signals whenever they are not driving

the bus signals When a bus signal is assigned a null waveform it is

disconnected from the driver

Mo del of the ALU Unit

The ALU mo del has the following comp onents

ALU Pro c pro cess which do es arithmetic logic and rotation op era

tions is not a clo cked pro cess and gets activated by any change in the

pro cesss sensitivity list

The register pro cesses including TEMP MUX Pro c and ACC MUX Pro c

are each enabled by the enabling signals from the InstructionDeco der

pro cess The data transfers are triggered by the falling edge of the

clo ck phi and are multiplexed by the multiplexing signals

The pro cess of ACT latch ACT MUX Pro c is actually enabled when

the enabling signal is set to high by the InstructionDeco der pro cess

and is activated by any change in its sensitivity list

BUS OUT Pro c and DATABUS OUT Pro c pro cesses are INTERNAL

similar to those describ ed in the Register Array Mo del

Note that the usage of several pro cesses in the Register Array Mo del and also

the ALU Mo del has to do with the concurrent events among these pro cesses

since the concurrent activities can not b e implemented within one pro cess In

addition it relates to the synthesis purp ose since there are some constrains

for a synthesizable VHDL design which have b een discussed briey in section

Simulation and Synthesis of the VHDL mo del

of the CPU

Mo del test vectors and input les

In order to verify the functionalities of the CPU mo del two test les

were prepared The rst le consists of binary numb ers which represent the

stimuli including a clo ck signal and external request signals such as RESET

READY HOLD INT The stimuli are added to the CPU system by

using a VHDL le which reads in the stimuli from the binary stimuli le

and then connects these stimuli to the system mo del Another test

le is the entire instruction set of the CPU in assembly language The

instructions are added to the CPU system by using a VHDL le which

reads in instructions in assembly language converts them to binary co des

and then adds these binary co des to the system mo del This VHDL

le acts like an assembler in the sense that it converts assembly language

into binary co des for the entire instruction set of CPU This assembler

was also develop ed in VHDL during the course of this pro ject It greatly

facilitates the pro cess of debugging if the instruction test le for the entire

instruction set is in assembly language instead of binary co des

Simulation Results

The state transition is veried for each of the instructions of the

CPU to make sure that it has the the right numb er of T states for

every machine cycle and the right numb er of machine cycles for each

instruction cycle An output sample is shown b elow

MT State T of the first machine cycleM

Instruction binary code

The waveform of external control signals like SYNC DBIN and WR

BAR are traced for the rst several instructions b eing executed to make

sure that they get set and reset prop erly Figure shows the waveform

of these signals

The values for all the registers in b oth ALU and Register Array Unit

are checked at the end of each of the instructions to make sure that

each instruction gets executed in the way it is supp osed to A sample

output is shown b elow

IR Instruction Register

PC Program Counter

SP Stack Pointer

Reg B Register B

Reg C Register C

Reg D Register D

Reg E Register E

Reg H Register H

Reg L Register L

Figure The Waveforms of the External Control Signals

ALU ALU ouptut

ACC Accumulator Register

TEMP Temporary Register

FLAGS ZO P S CY AC Flag Register in ALU

Reg B

Reg C

Reg D

Reg E

Reg H

Reg L

ALU

ACC

TEMP

FLAGS ZO P S CY AC

Reg B

Reg C

Reg D

Reg E

Reg H

Reg L

ALU

ACC

TEMP

FLAGS ZO P S CY AC

Reg B

Reg C

Reg D

Reg E

Reg H

Reg L

ALU

ACC

TEMP

FLAGS ZO P S CY AC

Synthesis and Optimization of the VHDL design

Synthesis is the pro cess of transforming one representation in the design

abstraction hierarchy to another representation AUTOLOGIC is such a to ol

from Mentor Graphics which is used to synthesize the compiled VHDL design

into gatelevel schematics and to optimize this description AUTOLOGIC is

used to optimize gatelevel design for area by applying sp ecied options We

chose the option to map the synthesized design to a technology like CMOSN

and to use algebraic and Bo olean techniques to combine terms or eliminate

redundant logic The optimized topsheet schematics shown in Figure

have ve mo dules connected with each other with each corresp onding to a

comp onent of the VHDL design of the Each of the ve mo dules in

the topSheet consists of gatelevel schematic sheets One sample gatelevel

sheet is shown in Figure There are ab out such gatelevel sheets in

total for the whole synthesized design and there are ab out logic gates

involved overall The synthesized schematic is also simulated to make sure

that the synthesized design functions the same way as the validated VHDL

mo del

VHDL Mo deling Summary

An abstract b ehavioral VHDL mo del was develop ed and veried And then

the b ehavior mo del was decomp osed into the synthesizable VHDL mo del

which was used to pro duce the gate level design of the There are

ab out lines of VHDL co de for the synthesizable version including the

assembler which was develop ed also in VHDL and contains lines of co de

Figure TopSheet of the Synthesized Schematics of CPU Mo del

Figure One Sample GateLevel Sheet

References

James R Armstrong ChipLevel Modeling with VHDL Prentice Hall

Englewo o d Clis New Jersey

James R Armstrong and F Gail Gray Structured Logic Design with

VHDL Prentice Hall Englewo o d clis New Jersey

Mentor Graphics Autologic VHDL Synthesis Guide unpublished work

of Mentor Graphics Corp oration Mentor Graphics Corp oration

Mentor Graphics QuickSim II Users Manual unpublished work of

Mentor Graphics Corp oration Mentor Graphics Corp oration

Mentor Graphics System Quick Reference unpublished work of

Mentor Graphics Corp oration Mentor Graphics Corp oration

M Morris Mano COMPUTER SYSTEM ARCHITECTURE Prentice

Hall Englewo o d Clis New Jersey

Intel marketing communications The Microprocessor Book

A WileyInterscience Publication Intel Corp oration

Cary Ussery Roger Lipsett Carl Scharfer VHDL Hardware Description

and Design Kluwer Academic Publishers Norwell Massachusette