Rep ort TopDown Design Of the CPU In VHDL Shengxin Wang Nick Kanop oulos and Kishor S Trivedi July Contents Intro duction TopDown Design In Digital Systems The Abstraction Hierarchy : : : : : : : : : : : : : : : : : : : : TopDown Design Pro cess With Logic Synthesis : : : : : : : : Imp ortant Features of VHDL Classes of Ob jects : : : : : : : : : : : : : : : : : : : : : : : : : Attributes : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Mo deling concurrency : : : : : : : : : : : : : : : : : : : : : : Signal Assignment : : : : : : : : : : : : : : : : : : : : : : : : Pro cess Mo del Graph : : : : : : : : : : : : : : : : : : : : : : : Guidelines for synthesizable VHDL : : : : : : : : : : : : : : : The Central Pro cessing Unit Architecture of the Central Pro cessing Unit : : : : : : : The Pro cessor Cycle : : : : : : : : : : : : : : : : : : : : VHDL Design of the CPU Pro cess Mo del Graph of the CPU : : : : : : : : : : : : : Mo del of the Control Unit : : : : : : : : : : : : : : : : : : : : Mo del of the InstructionDeco der : : : : : : : : : : : : : : : : : Mo del of the Register Array : : : : : : : : : : : : : : : : : : : Mo del of the ALU Unit : : : : : : : : : : : : : : : : : : : : : : Simulation and Synthesis of the VHDL mo del of the CPU Mo del test vectors and input les : : : : : : : : : : : : : : : : Simulation Results : : : : : : : : : : : : : : : : : : : : : : : : Synthesis and Optimization of the VHDL design : : : : : : : : VHDL Mo deling Summary : : : : : : : : : : : : : : : : : : : : List of Figures Abstraction levels in digital systems : : : : : : : : : : : : : : : TopDown Design Pro cess With Logic Synthesis : : : : : : : : Logic blo ck structure : : : : : : : : : : : : : : : : : : : : : : : Three concurrent pro cesses : : : : : : : : : : : : : : : : : : : : Pro cess Mo del Graph : : : : : : : : : : : : : : : : : : : : : : : CPU Functional Blo ck Diagram : : : : : : : : : : : : : : TwoPhase Nonoverlapping Clo ck : : : : : : : : : : : : : : : : CPU Pro cess Mo del Graph : : : : : : : : : : : : : : : : : CPU State Transition Diagram : : : : : : : : : : : : : : : : : The Waveforms of the External Control Signals : : : : : : : : TopSheet of the Synthesized Schematics of CPU Mo del : One Sample GateLevel Sheet : : : : : : : : : : : : : : : : : : Intro duction One of the main directions of mo dern CAD environments is the develop ment of metho dologies and to ols that supp ort a topdown hierarchical design paradigm This direction is necessitated in part by the design complexities encountered by designers to day and by the need to share design data bases among large design teams One highly touted to ol in this pro cess is the VHSIC Hardware Description Language VHDL The main reason for the p opularity of VHDL is the fact that it has one of the b est sets of constructs for hardware b ehavior mo deling Early developments of VHDL to ols were fo cused primarily on simulation and were not part of integrated to ol environments Lately new generations of to ols have emerged that oer an integrated environment where a design captured hierarchically with VHDL can b e executed from functional b ehavior to circuit layout The ob jectives of this pro ject were two fold First we intended to demon strate a topdown hierarchical design metho dology based on VHDL with a b enchmark of substantial complexity This was accomplished with the design of the Intel CPU which was p erformed in a topdown fashion starting at the b ehavior level and ending with layout for a targeted CMOS technology The second ob jective was to develop a hierarchical b ehavioral and structural b enchmark mo del which can b e used to p erform faultinjection exp eriments that can b e used to validate fault secure features of hardware structures The b enchmark is currently used in this capacity for the continuation of this pro ject which is also sp onsored in part by CACC The choice of the CPU for this pro ject is based simply on the avail ability of structural information in the public domain for this design The design metho dology demonstrated and the fault injection metho dology b eing develop ed are indep endent of the particular circuit under design However any design attempted using the metho dology presented in this pro ject should assume the availability of somelevel of structural design information at the register transfer level including timing The outcome of this pro ject is a topdown hierarchical b ehavioralstructural mo del and an assembler for the CPU all develop ed in VHDL The mo del was veried and validated through simulations at all levels and with the en tire instruction set All mo del development was p erformed with Mentor Graphics to ols and the develop ed VHDL mo del can b e used by interested users as a macro cell in the Mentor database TopDown Design In Digital Systems With the increasing complexity of VLSI circuits and timetomarket pressure the b ottomup design metho dologies of the s are no longer viable solutions b ecause they are tedious slow and error prone A higher level topdown synthesis approach is mandatory to meet to days design needs A design can b e quickly dened using VHDL and veried through simulation Once functionality is veried synthesis can rapidly move the design to the gate level layout automating a task that previously was tedious and errorprone In addition with a topdown design metho d employing VHDL synthesis functional changes can b e made rapidly and veried through simulation The Abstraction Hierarchy Using VHDL designs can b e describ ed in topdown fashion through varying levels of abstraction The levels of abstraction in digital systems are shown in Figure They are the chip level the register level the gate level the circuit level and the silicon level Note that the abstraction hierarchy has a pyramidal shap e The broadening of the pyramid as one moves to lower levels represents the increasing amount of detail that must b e managed in representing a VLSI device at that level Abstraction can b e expressed in two domains which are now dened as follows Structural domain a domain in which a comp onent is describ ed in terms of an interconnection of more primitive comp onents Behavioral domain a domain in which a comp onent is describ ed by dening its inputoutput resp onse by means of a pro cedure CHIP REGISTER GATE CIRCUIT SILICON Figure Abstraction levels in digital systems TopDown Design Pro cess With Logic Synthesis The ow chart in Figure shows the topdown design pro cess and the Mentor Graphics to ols that can b e used to implement this pro cess The design pro cess includes the following steps Dene the design sp ecication and build a blo ck diagram by partition ing the functionality Build the functional mo del for each toplevel comp onent The toplevel is the top level of what will b e a multilevel design hierarchy And one can describ e each comp onent in the toplevel using a VHDL mo del schematics or a combination of b oth The VHDL mo dels need to b e synthesizable RTLlevel mo dels This mo del creation in the Mentor Graphics CAD framework can b e p erformed using Design Architect or just a plain editor Verify the functionality of the toplevel mo del by simulation If any problems are revealed by simulation the VHDL mo del is edited and DEFINE THE DESIGN SPECIFICATION PARTITION FUNCTIONALITY (BLOCK DIAGRAM) | M DESIGN Enter DEVELOP Input | E VHDL ARCHITECT or | Schematics description N MODEL EDITOR | T | O | R Refine FUNCTIONAL QUICKSIM II | SIMULATION | C | A | D | SYNTHESIS/ AUTOLOGIC OPTIMIZATION | F | R | A | M Refine QUICKSIM II FUNCTIONAL | E VERIFICATION | W | O | R | LAYOUT and K Detailed Analysis | | Figure TopDown Design Pro cess With Logic Synthesis corrected QuickSim Logic Simulator of Mentor Graphics oers the capabilities needed to p erform the verication Once the VHDL design is mo deled correctly and veried the Auto logic Synthesis to ol for Mentor Graphics environment can b e used to synthesize and optimize the design Verify the b ehavior of the synthesized gatelevel design to determine whether the synthesized design op erates correctly Again Quicksim is used to simulate the design The pro cess of developing a synthesizable VHDL mo del in step ab ove in cludes the following steps Develop an abstract b ehavioral VHDL mo del Verify the abstract b ehavior of the mo del Decomp ose the b ehavioral mo del into a synthesizable RTLlevel mo del Verify the b ehavior of the rened mo del Imp ortant Features of VHDL TopDown design requires a common medium a requirement satised by the VHDL language The basic descriptions of the syntax and constructs of VHDL could b e found in many publications Some imp ortant features of VHDL make it very eective for mo deling a logic design These features are briey describ ed to provide context for the pro ject describ ed in this rep ort Classes of Ob jects There are three classes of ob jects in VHDL constants variables and signals An ob ject is created when it is declared The dierence b etween signals and variables is that signals have a time dimension and direct hardware corresp ondence Attributes Signal attributes are particularly imp ortant in mo deling Some examples are SLAST VALUE is the previous value of S immediatedly b efore the last change of S It is very useful for checking changes in a signal SSTABLET is of typ e BOOLEAN It is true if S has b een stable for last T time units SDELAYEDT is the value of S T time units earlier Another useful set