A 65 Nm Single-Chip Application and Dual-Mode Baseband Processor
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 83 A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU Masayuki Ito, Kenichi Nitta, Koji Ohno, Member, IEEE, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Member, IEEE, Teruyoshi Komuro, Toshihiro Hattori, Member, IEEE, Yasuhiro Arai, and Yukio Kodama Abstract—Supporting both WCDMA with HSDPA and GSM/ is superior in performance, power consumption, and cost, P GPRS/EDGE, the 9.3 9.3 mm SoC fabricated in triple-Vth 65nm such SoC is widely adopted especially for high performance CMOS, has three CPU cores and 20 separate power domains. Un- cellular phone system [1]–[3]. For the SoCs targeted at cel- used power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music lular phone system, efficient power control is mandatory to playback scene dynamically stops a PLL and clock trees when not satisfy the handset’s requirements. As for the leakage power necessary and reduces power consumption from 33.6 mW to 19.6 reduction, power domain separation to shut down power supply mW. IP-MMU translates virtual address to physical address for of unnecessary power domains is very important [4], [5]. In 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external addition, lower power consumption and longer battery time for memory by 43 MB. Video performance of D1 (720 520) size with a certain scene such as music playback is one of the biggest 30 frames per second for MPEG/AVC decoding and encoding can key features for the handsets and is strongly required. We be achieved under mixed virtual and physical address usage. have introduced a partial clock activation scheme especially Index Terms—Application processor, baseband processor, cel- focused on low-power music playback. Another requirements lular phone, clock activation, memory space, power domains. for the SoCs used for the cellular phone system is efficient memory management, because ever-increasing diversity of applications require huge size of external memory. We have I. INTRODUCTION introduced memory management unit for intellectual property ELLULAR phones are used not only for voice communi- (IP-MMU), which translates virtual address to physical address C cations, e-mail, and web browsing, but also used for more for hardware-IPs (HW-IPs). By using IP-MMU, virtual address advanced functions such as video telephony, 3D Java games, space can be allocated when necessary and can be freed after and high-class business applications. So, high-level operating its operation. Thus IP-MMU contributes to external memory systems, such as Symbian or Linux, are being widely adopted size reduction. In this paper, some previous work of our single for cellular phone system. A high performance application chip integration is reviewed in Section II. Architecture and key processor is required to handle such a high-level operating features of our SoC are explained in Section III. Then we ex- system together with ever-increasing applications with heavy plain the details of two schemes namely partial clock activation data traffic. Moreover using a separate media accelerator along scheme and memory management scheme with IP-MMU with with the application processor is a preferred solution for han- some evaluation results in Sections IV and V, respectively. dling high-end multimedia applications. On the baseband side, Conclusions are in Section VI. a baseband processor is required to handle modem sub-system and WCDMA/GSM/GPRS services which are the services II. PREVIOUS WORK generally available worldwide these days. The cellular phone Our first generation SoC SH-MobileG1 (G1) in which both handsets in the past are implemented by mounting two or three baseband and application processors are integrated, has three processors. Since one-chip integration of a baseband processor processor domains [1]. These three processor domains cor- and an application processor along with a media accelerator respond to the conventional three chips of the cellular phone system as shown in Fig. 1. Each domain has a separate CPU Manuscript received April 15, 2008; revised August 31, 2008. Current version that runs a different operating system. The major benefits of the published December 24, 2008. 3-domain architecture is to 1) maximize the reuse of huge soft- M. Ito is with the Renesas Technology Corporation, System Core Tech- nology Division, Kodaira, Tokyo 187-8588, Japan (e-mail: ito.masayuki2@re- ware assets of conventional cellular phones by keeping the same nesas.com). system architecture; 2) enable separate system development K. Nitta, S. Yoshioka, T. Irita, T. Koike, T. Kamei, and T. Hattori are with in cellular phone design; 3) can implement different efficient Renesas Technology Corporation, Tokyo, Japan. K. Ohno and M. Saigusa are with NTT DoCoMo, Inc., Tokyo, Japan. power shut down schemes according to the cellular phone use M. Nishida is with Sharp Corporation, Hiroshima, Japan. for the reduction of leakage power consumption; 4) reduce the T. Komuro is with Sony Ericsson Mobile Communications Japan, Inc. conflicts between each subsystems; and 5) support separate Y. Arai is with Fujitsu Ltd., Yokosuka, Japan. Y. Kodama is with Sanda Works, Mitsubishi Electric Company, Japan. dynamic clock frequency changes for each domain for the Digital Object Identifier 10.1109/JSSC.2008.2007169 reduction of dynamic power consumption. G1 is implemented 0018-9200/$25.00 © 2008 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on January 14, 2009 at 10:01 from IEEE Xplore. Restrictions apply. 84 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 TABLE I FEATURE OF SH-MOBILE G3 Fig. 1. Conventional 3-chip configuration and one chip integration of 3-pro- cessor domains of SH Mobile G series. with 20 separate power domains to control the leakage power effectively. Our second generation SoC namely SH-MobileG2 (G2) re- fines the design in both terms of performance and power dis- sipation keeping the same 3 processor domain architecture [2]. The design highlights of G2 are: 1) CPU core standby mode for both high-performance application CPUs where cache/RAMs are kept powered, while shutting down the logic part, is in- troduced to reduce the leakage power; 2) dynamic clock-stop scheme is introduced, where the clock supply for bus-routers and bus-bridges are dynamically stopped when no bus transac- tion is in progress to reduce the dynamic power; and 3) 512KB media-RAM is embedded into the system which can be split up to 32 interconnect buffer (ICB) pieces that acts as read fill buffers, write back buffers, or interconnect buffers through the ICB controller to enhance the performance of media IPs. III. G3 ARCHITECTURE AND KEY FEATURES We have now developed a third generation of our SoC series namely, SH-MobileG3 (G3), with a further evolved design in terms of both low power consumption and good performance Fig. 2. Chip micrograph of SH-Mobile G3. keeping the same 3 processor domain architecture of SH-Mobile G series. G3 has the following key features: 1) With the help of triple-Vth technology in low-power 65 nm with image processing unit that handles up to 12M pixel camera. CMOS process we were able to make both the application The baseband part has a support for dual-baseband system. The CPUs to operate at 500 MHz. WCDMA block supports HSDPA service and the GSM block 2) A total of 20 power domains are defined to reduce the supports EDGE mode. leakage power. Fig. 3 shows CPU and bus architecture. In G3 system, mul- 3) Partial clock activation method focused on music playback tiple operation systems (OS) run on heterogeneous multi-CPU scene is newly introduced in which unnecessary clock sys- cores. In the application part, ARM1176 runs high-level OS and tems are turned off. SH-X2 runs realtime media applications. In the baseband part, 4) IP-MMU is also newly introduced, which translates vir- ARM926 controls the baseband IPs including DSPs that handle tual address to physical address for 18 different kinds of modem protocols. 2D and 3D graphics IP cores have a built in media IPs (2D-graphics, 3D-graphics, capturing, movie, IP-MMU between the controllers and an on-chip-bus. 16 media displaying, blending etc). IP-MMU contributes to the re- IPs are connected to ICB that has another built in IP-MMU. duction of external memory size. Thus in G3 system, CPUs and IP-cores share single page table 5) Interconnect buffer (ICB) is enhanced to incorporate with for virtual address space controlled by OS-control CPU. IP-MMU to give a better performance. The power domain view of G3 is shown in Fig. 4. A total Table I shows G3 chip features and Fig. 2 shows G3 chip mi- of 20 hierarchical power domains are defined. The application crograph. Die size is 9.3 mm 9.3 mm. Supply voltages are and the baseband parts are divided into 13 and 6 power domains 1.2V(internal) and 1.8/2.5/3.3V(I/O). G3 chip size is 307M tran- respectively with one additional common power domains (C5). sistors (28.2M gates and 30.7 M memory bits). In the applica- The arrows indicate hierarchical relation between the power do- tion part, a large number of media engines are integrated. 2D and mains. A right power domain shown by the head of an arrow 3D graphics accelerators, video processing unit supporting D1 must be awake for a power domain in the left. Clock buffers, size (720 520) video decoding and encoding and a camera-IF clock dividers, repeater cells, hardware back-up flip-flops, and Authorized licensed use limited to: IEEE Xplore.