11/20/2019

DIGITAL ELECTRONICS GROUP 2 LAB EXTENSION SYSTEM DESIGN  I have decided to extend the deadline for group 2 labs to FALL 2019 Wednesday, Nov. 20 at 6:30pm PROF. IRIS BAHAR  Please note that you should not expect similar extensions NOVEMBER 18, 2019 for groups 3 and 4. Please plan your time accordingly LECTURE 20: FAST ADDITION,  For lab 7, please note that now is a good time to make use of the logic analyzer for your debugging, if you haven’t done so already

MIDTERM EXAM PROBLEM 3B

 The exam has been graded. Here are some stats:  Average: 68.5 J m1 m m5  Min: 35 m3 m7 Q 3  Max: 92 Clk  Median: 69 m4 m8 K m2 m6 Q’  Here is a rough grade distribution:  A: ≥ 76  A/B: 70 ≤ B ≤ 75  B: 60 ≤ B ≤ 69  B/C: 55 ≤ B ≤ 59  C: 40 ≤ B ≤ 54  F: < 40

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FULL ADDER THE FULL ADDER

Truth Table Cin A Cin Id a b cin carry sum S A 1-bit Full 0 0 0 0 0 0 B Adder S a 1 0 0 1 0 1 B (FA) Cin 2 0 1 0 0 1 Sum 3 0 1 1 1 0 Cout 4 1 0 0 0 1 b 5 1 0 1 1 0 Cout Carry 6 1 1 0 1 0 7 1 1 1 1 1

 How do you express sum and carry as Boolean functions?

THE RIPPLE CARRY ADDER GLITCHING IN A RIPPLE CARRY ADDER

A B A B A B A B 3 3 2 2 1 1 0 0 Cin 3 S15 S14 S2 S1 S0

Cout=C4 FA FA FA FA C0=Cin

2 S3 S4 S15 S3 S2 S1 S0 Cin S2 1 S5  The carry out of one stage ripples to the carry in of the S10 S1 next (V) Voltage Output S S0 0 024681012 Time (ps)

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FAST CARRY CHAIN DESIGN CARRY OUT LOGIC FOR 4-BIT ADDER

 The key to fast addition is a low latency carry network  Ps and Gs are computed at time 0  What matters is whether in a given position a carry is  C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0 C0  generated Gi = Ai & Bi = AiBi = G3 + P3(G2 + P2(G1+ P1G0 )) + (P3P2P1P0) C0  propagated Pi = Ai  Bi

G : carry generation P3:0 : carry propagation  annihilated (killed) Ki = !Ai & !Bi 3:0 from bits 3-0 from bits 3-0  Giving a carry recurrence of

Ci+1 = Gi + PiCi G = A & B C1 = G0 + P0C0 i i i Pi = Ai  Bi C2 = G1 + P1C1 = G1 + P1G0 + P1 P0 C0 Pi can also be expressed as C3 = G2 + P2G1 + P2P1G0 + P2P1P0 C0 Pi = Ai + Bi C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0 C0

32-BIT CARRY LOOKAHEAD ADDER WITH 4-BIT RIPPLE CARRY ADDERS 32-BIT CLA WITH 4-BIT RCAS

 Carry out logic gets more complicated beyond 4 bits  CLAs are often implemented as 4-bit modules and instantiated in a hierarchical way to realize wider adders

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WORST CASE DELAY CARRY-SKIP (CARRY-BYPASS) ADDER

A3 B3 A2 B2 A1 B1 A0 B0

Co,4 FA FA FA FA Ci,0

Co,4 S3 S2 S1 S0

BP = P0 P1 P2 P3 “Block Propagate”

If (P0 & P1 & P2 & P3 = 1) then Co,4 = Ci,0 otherwise the  What is the longest delay to compute the full add? block itself kills or generates the carry internally (and doesn’t need Ci,0 to compute Co,4)

MIRROR ADDER MIRROR ADDER 24+4 transistors B A B BBA A 12 B 12 B 4 Cin A 0-propagate kill 0-propagate kill !P G A Cin 12 A 4 !Cout !S !Cout Cout Cin Cin Cin A Cin 62A K 1-propagate generate 1-propagate generate P A A BB A B Cin A 66BB2 B

C = AB + BC + AC out in in Ci+1 = Gi + PiCi SUM = ABCin + !COUT(A + B + Cin) Note that P, K, and G are all mutually exclusive

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MANCHESTER CARRY CHAIN 4-BIT SLICED MCC ADDER

A B A B A B A B  Switches controlled by Gi and Pi 3 3 2 2 1 1 0 0 clk !Pi G !Ci+1 = !(CiPi + Gi ) Ci+1 i &  &  &  &  C GP GP GP GP !Ci i G Ki i P !C4 !C0 Pi i clk

 Total delay of !C3 !C2 !C1

 time to form the switch control signals Gi and Pi      setup time for the switches  signal propagation delay through N switches in the worst case S3 S2 S1 S0 = P0  C0

DOMINO MANCHESTER CARRY CHAIN CARRY-SKIP (CARRY-BYPASS) ADDER

A B A B A B A B clk 3 3 2 2 1 1 0 0 P3 P2 P1 P0

Co,4 Ci,4 Ci,0 FA FA FA FA Ci,0

G3 G2 G1 G0 Co,4 clk S3 S2 S1 S0

!(G0 + P0 Ci,0) BP = P0 P1 P2 P3 “Block Propagate” !(G2 + P2G1 + P2P1G0 + P2P1P0 Ci,0) If (P0 & P1 & P2 & P3 = 1) then Co,4 = Ci,0 otherwise the !(G1 + P1G0 + P1P0 Ci,0) block itself kills or generates the carry internally (and !(G + P G + P P G + P P P G + P P P P C ) 3 3 2 3 2 1 3 2 1 0 3 2 1 0 i,0 doesn’t need Ci,0 to compute Co,4)

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CARRY-SKIP CHAIN IMPLEMENTATION CARRY-SKIP CHAIN IMPLEMENTATION block carry-out block carry-out carry-out carry-out BP BP block carry-in block carry-in Not strictly necessary

P3 P2 P1 P0 !BP P3 P2 P1 P0

!C out Cin !C out Cin

G3 G2 G1 G0 G3 G2 G1 G0

BP BP

4-BIT BLOCK CARRY-SKIP ADDER STATIC VS. VARIABLE BLOCK SIZE

bits 12 to 15 bits 8 to 11 bits 4 to 7 bits 0 to 3

Setup Setup Setup Setup

Carry Carry Carry Carry Propagation Propagation Propagation Propagation Ci,0

Sum Sum Sum Sum Worst-case delay  carry from bit 0 to bit 15 carry generated in bit 0, ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15

Tadd = tsetup + B tcarry + ((N/B) -1) tskip +B tcarry + tsum

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CARRY SELECT ADDER CARRY SELECT ADDER A’s B’s  AND/OR Mux select “carry-1” or “carry-0” block depending on carry in of previous stage  Pre-compute the carry 4-b Setup P’s G’s  Here, C starts the Mux selection process. out of each block for 4 both carry_in = 0 and “0” carry propagation 0  Compared to carry skip, avoids having to wait for the ripple carry_in = 1 (can be carry of the last block. “1” carry propagation 1 A B A B A B A B done for all blocks in 16:13 16:13 12:9 12:9 8:5 8:5 4:1 4:1

0 0 0 parallel) and then multiplexer C + + + Cout in

Cout C12 C8 C C’s 1 1 1 4 C select the correct one + + + + in Sum generation 1 1 1 0 0 0

S S S S S’s 16:13 12:9 8:5 4:1 Figure 11.24 from Weste&Harris

CARRY SELECT ADDER: CRITICAL PATH

bits 12 to 15 bits 8 to 5 bits 4 to 7 bits 0 to 3 A’s B’s A’s B’s A’s B’s A’s B’s

1 Setup Setup Setup Setup P’s G’s P’s G’s P’s G’s P’s G’s

“0” carry “0” carry “0” carry “0” carry 0 +4

“1” carry “1” carry “1” carry “1” carry 1

+1mux mux+1 mux+1 +1mux C C out C’s C’s C’s C’s in

Sum+1 gen Sum gen Sum gen Sum gen

S’s S’s S’s S’s

Tadd = tsetup + B tcarry + N/B tmux + tsum

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