64-Bit Z/Architecture Overview Part I: Application Facilities

64-bit z/Architecture Overview Part I: Application Facilities

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Bob Rogers IBM Corporation [email protected] 1-845-435-1647 zSeries

Copyright IBM Corporation 2000, 2001 zSeries Copyright Corporation IBM 2000, 2001 Addressing Modes General Purpose Registers Non-modal and modal Instructions Instructions Addressing Mode Switching Instructions in Support ofNew 64-bit Immediate InstructionsNew Some other Interesting Instructions 2 Extended Translation Facility Part I - Non-Authorized Facilities Part I - Non-Authorized Architecture Elements Architecture zSeries Copyright Corporation IBM 2000, 2001 The Style of z/Architecture The Style z/Architecture has extended ESA/390 to 64-bit in a z/Architecture has extended different than other platforms. For manner somewhat architecture, 64-bit addressing and in PowerPC example, 64-bit operation are inseparable. When running in 64-bit 64-bit definitions. mode, all register operations also have modes is restricted to the between to switch The ability supervisor. The z/Architecture definition separates the control of 64-bit addressing mode from operations. This style to 64-bit in an to be extended software of definition allows manner. 32-bit and 64-bit operations are evolutionary supported in 24-, 31- and 64-bit addressing mode. Any addressing modes and between program can switch 32-bit and 64-bit operations. intermix zSeries 00 = 24-bit mode 00 = 24-bit mode 01 = 31-bit = 64-bit mode 11 64-bit instruction address instruction 64-bit Copyright Corporation IBM 2000, 2001 31-bit IA 31-bit Addressing mode bits: mode Addressing 31-32 The 31-bit addressing mode bit is on in 64-bit mode. 64-bit on in is bit modeaddressing The 31-bit A PSW seem indicating 64-bit addressing mode to will programs mode "unknowing" to 31-bit indicate PSWmode. 31 addressing bitsdesignate 32 and Address generation Base and Index uses 64-bit addresses. 64-bit produces and values in bits 24 or 31 to truncated are addresses Effective mode. 24-bit31-bit or addressing Addressing Modes Addressing Actual PSW z/OSPSW Apparent zSeries .32-63{0-31} 2 Copyright Corporation IBM 2000, 2001 .32-63{0-31} from R 1 sets R 2 ,R 1 The z/Architecture is a 64-bit architecture with several of 64-bit registers and areas, such as 64-bit types General Purpose Registers. The numbering of the bits for these entities is cause change to be 0 63. This may confusion when dealing with some of the compatible aspects of the architecture. For example, The ESA/390 Load instructions sets bits 0-31 of a General Purpose Register. In z/Architecture, the Load instructions sets bits 32-63, due to the renumbering of the bits. To ease understanding, sometimes the ESA/390 bit positions will also in be provided braces. Bit positions are usually designated after a dot. For example: LR R Renaming the bits Renaming zSeries 63 32-bit GPR 32-bit 32{0} 63{31} Copyright Corporation IBM 2000, 2001 64-bit General64-bit Purpose Register 0 Address generation in 64-bit mode ofGPR operands non-modal 64-bit instructions ofGPR operands modal instructions in 64-bit mode Address generation in 24/31-bit modes (so it seems) ofGPR operands non-modal 32-bit instructions ofGPR operands modal instructions in 24/31-bit modes The register is treated as 64-bits for: The register is treated as 32-bits for: General Purpose Registers zSeries 11 Displacement 0 + 63 Index Register 0 64-bit General Purpose Register64-bitPurpose General + 63 ) is[this an RX example] Copyright Corporation IBM 2000, 2001 2 ,B 2 (X 2 ,D 1 Base RegisterBase In 24-bit mode, the leftmost 40 bits are set to zeros. to set are 40 bits leftmost mode, the 24-bit In zeros. to set are 33 bits leftmost mode, the 31-bit In truncated. not is address 64-bit mode, the 64-bit In Address generation takes the value contained in a the value 64-bit base register plus (optionally) contained in a 64-bit index register plus the value of the 12-bit displacement in instruction. The result is then truncated on the left depending upon the current addressing mode. 0 64-bit General Register Purpose Op R Address Generation Address zSeries . Copyright Corporation IBM 2000, 2001 When in executing 24- or 31-bit opaque Since z/Architecture allows the intermixing of addressing modes and operand precisions, care was taken to ensure that old 32-bit programs could not inadvertently register informationdestroy which new 64-bit programs assumed to be preserved. high-orderThe of the 64-bithalves registers are only in 64-bit mode or visible when newexecuting instructions. addressinginstructions modeissuing and which only are defined in ESA/390, the high-order 32-bits of the 64-bit registers are Old programs, which do not save/restore the full 64-bit alterunknowingly registers, the contents of cannot halveshigh-order of the registers. A "meta rule" of z/Architecture rule" "meta A zSeries 0-31 ). 2 ,B 2 (X 2 depending on mode. from D

1.0-63 applies to instructions or R or

1.32-63{0-31} is applied to instructions for Copyright Corporation IBM 2000, 2001 1.32-63{0-31} Non-Modal Modal E.g.LA set R For these instructions, addressing mode is only used during used during mode only is addressing instructions, these For generation. address operand storage R loads L always E.g. operands register some all of or width the Specifically, mode. depends upon addressing which the operation is different in 64-bit addressing mode than in 24-/31-bit mode. The term The term which perform the same operation regardless of addressing mode. Modal vs Non-Modal Instructions Modal vs

. zSeries (32) 32-bit Register 32-bit Register Storage Operand ) 2 ,B 2 regardless ofaddressing mode (X 2 Copyright Corporation IBM 2000, 2001 D 2 1 Bits 0-31 of the 64-bit GPRs are unexamined and unexamined are 0-31 of the 64-bit GPRs Bits unmodified AL L, A, ALR, AR, LR, Examples: R R ESA/390 32-bit operand instructions which behave as in ESA/390 - Non-modal instructionsNon-modal zSeries 32-bit Register Storage Operand ) 2 ,B 2 (X 2 Copyright Corporation IBM 2000, 2001 D ) (32) Example 2 ,B 2 (X 2 ,D 1 1 R ADD (32) takes the value of a fullword in storage adds it to the contents of and arithmetically low-order 32-bits of a general purpose register. The high-order 32-bits of the general purpose register are neither interrogated nor modified. The operation is the same in all addressing modes. A R Non-modal Non-modal zSeries . G , AL G , A G R, L (64) G R, AL G 64-bit GPR R, A Storage Operand Copyright Corporation IBM 2000, 2001 G 64-bit Register Operand regardless of addressing mode 2 1 ) 2 R R All 64-bits of the first operand register 64-bits of the first operand register are modified All second operand is also 64-bits wide The L Examples: ,B 2 New 64-bit operand instructions operate on operands - (X Non-modal instructionsNon-modal 2 D zSeries 64-bit GPR ) Storage Operand 2 Copyright Corporation IBM 2000, 2001 (64) Example ,B 2 (X 2 ,D 1 1 ) 2 R ,B 2 ADD (64) takes the value of a 8-bytes in storage and ADD (64) takes the value of a 8-bytes adds it to the contents of full 64-bit arithmetically general purpose register. The entire 64-bit general purpose register is both input to and output of the operation . The operation is the same in all addressing modes. (X AG R 2 Non-modal D zSeries SLAG SLLG SRAG SRLG SG[R] SLG[R] STG STMG LG[R] LGH LGHI LMG LNGR LPGR MGHI MSG[R] OG[R] Copyright Corporation IBM 2000, 2001 BRXLG CG[R] CSG CDSG CGHI CLG[R] CVBG CVDG XG[R] AG[R] AGHI ALG[R] NG[R] BCTG[R] BXHG BXLEG BRCTG BRXHG 64-bit Analogs of ESA/390 Instructions of ESA/390 64-bit Analogs Non-priviledged General Purpose Instructions General Purpose Non-priviledged zSeries LCTLG LURAG STCTG STURG TRACG Privileged Operations Privileged CEGBR CDGBR CXGBR CGEBR CGDBR CGXBR Copyright Corporation IBM 2000, 2001 Binary Floating Point Floating Binary CEGR CDGR CXGR CGER CGDR CGXR 64-bit Analogs of ESA/390 Instructions of ESA/390 64-bit Analogs Hex Floating Point Floating Hex zSeries LRVG, LRVGR MLG, MLGR DLG, DLGR ALCG SLBG STRVG RLLG Non-modal 64-bit Copyright Corporation IBM 2000, 2001 Load Reversed - LRV, LRVR Logical - ML, MLR Multiply Divide Logical - DL, DLR - ALC Carry Add Logical w/ - SLB Borrow Subtract Logical w/ Store Reversed - STRV Rotate Left Single Logical - RLL New Instructions w/ 64-bit Analogs Non-modal 32-bit Instructions * * All these 32-bit non-modal instructionsto are ESA/390 added zSeries GF , AL regardless of GF , A (64/32) GF Storage Operand 32-bit Reg Operand R, L GF . 64-bit General Purpose Register 64-bit General Purpose R, AL Copyright Corporation IBM 2000, 2001 GF sign propagation or padding with zeros sign propagation or padding with zeros R, A 2 1 ) GF R 2 R ,B The 32-bit second operand is internally extended to extended is internally operand second 32-bit The is performed operation the before 64-bits the 64-bits of firstAll operand register participate 2 addressing mode New instructions operate on 32-bit second operands into 64-bit first - (X 2 Non-modal instructionsNon-modal E.g. L D zSeries Storage Operand ) 2 64-bit General Purpose Register 64-bit General Purpose Copyright Corporation IBM 2000, 2001 ,B 2 (64/32) Example (X 2 sign propagation propagation sign ,D 1 1 ) 2 R ,B 2 ADD (64/32) takes the value of a fullword in storage, propagates the sign to extend it 64-bits, and then adds the sign-extented value to the arithmetically contents of the 64-bit general purpose register. The entire 64-bit general purpose register is both input to and output of the operation . The operation is the same in all addressing modes. (X 2 AGF R Non-modal Non-modal D zSeries LLGT[R] LPGFR LNGFR MSGF[R] SGF[R] SLGF[R] Copyright Corporation IBM 2000, 2001 LLGF[R] AGF[R] ALGF[R] CGF[R] CLGF[R] LGF[R] 64/32 Analogs of ESA/390 Instructions Other 64/32 Instructions 64/32 Instructions zSeries 24/31-bit mode 64-bit mode Copyright Corporation IBM 2000, 2001 64-bit General Purpose General Register 64-bit Instructions which operate differently depending Instructions which operate differently the difference is upon addressing mode. Usually the width of register operands. e.g. LA, MVCL, TRT, BASR, BASSM Note: instructions like BCR are not considered modal because address generation naturally truncates the address taken from register according to current addressing mode. Modal instructions

. zSeries 1.0-63 is set to to set is

1.32{0} /R . 1.32-39{0-7} 24/31-bit mode and R

64-bit mode ) 1.33-63{1-31} Copyright Corporation IBM 2000, 2001 2 remains unchanged /R ,B 2 1.0-31 (X 2 R 64-bit General Purpose General Register 64-bit ,D 1 1.40-63{8-31} zero. 24-/31-bit mode: a 24-/31-bit address is placed in R 64-bit mode: a 64-bit address is placed in R Load Address produces a result dependent upon the current addressing mode. LA R Modal InstructionExample

1 zSeries 1 1 Convert UTF-8 to Unicode UTF-8to Convert AddressLoad Extended AddressLoad Long Relative AddressLoad Load Real Addressonly) (LRA Move Long Extended Move Long Move String String Search Translate Extended Translate and Test Update Tree 1 1 2 1 Copyright Corporation IBM 2000, 2001 1 Branch and Link (BAL, BALR) BASR) (BAS, and Save Branch Branch and Save and Set Mode Branch Relative and Save Branch Relative and Save Long Checksum Compare and Form Codeword Compare Logical Long Compare Logical Long Extended Compare Logical String Compare Until Substring Equal Convert Unicode to UTF-8 The length registers are 32 bits in 24/31-bit and 64 bits mode in 64-bit mode See the Principle of Operation for mode-dependent differences 1 2 Modal Non-privileged Instructions Modal Non-privileged zSeries Copyright Corporation IBM 2000, 2001 Set Addressing Mode to 24-bit Mode (SAM24) Addressing Set to 31-bit Mode (SAM31) Addressing Set to 64-bit Mode (SAM64) Addressing Set Branch and Set Mode (BASSM) and Save (BSM) Mode and Set Branch There are 3 new instructions which change addressing mode without branching: There are 2 instructions which change addressing mode and branch: Addressing Mode SwitchingAddressing * * SAM24 and SAM31 are added to ESA/390

63{31} zSeries . 2.32 =1. unchanged. 1.63{31} 1.0-31 and R 32{0} 2.63 =1 1.63{31} is not 0). not is 64-bit General Purpose Register 1 =1 (when R =1 (when Copyright Corporation IBM 2000, 2001 1.63{31) Amode to switch to BASSM sets a 64-bit return address with R with address return a 64-bit sets BASSM BSM sets R R set BALR and BASR do not 32 In all modes, BASSM and BSM switch addressing mode based on the contents of R In 64-bit mode: In 24/31-bit mode, these instructions set a return address as in ESA/390, and leave R Mode Switching Branches 63 0 24-bit mode 0 1 31-bit mode mode 64-bit 1 x zSeries Copyright Corporation IBM 2000, 2001 Test Addressing Mode Addressing Test Thirty-one Logical Load Load/Store Multiple High Load/Store Multiple Disjoint (word,Logical Load character)and halfword Insert Mask High Under Characters New Instructions in support of 64-bit zSeries 64-bit instruction address instruction 64-bit Copyright Corporation IBM 2000, 2001 Addressing mode bits: 00 bits: = 64-bit = mode 24-bit; 01 = 11 31-bit; Addressing Condition Code Condition CC=0: 24-bit mode 24-bit CC=0: mode 31-bit CC=1: mode 64-bit CC=3: Test Addressing Mode Addressing sets the condition code Test based on the current addressing mode: Test Addressing Mode -TAM Mode Addressing Test PSW * * TAM is added to ESA/390 zSeries to zeros. to LLTG LLTGR 1.0-32 , and set bits R , and set 31-bit Address 32-bit Register Storage Operand 1.33-63 Copyright Corporation IBM 2000, 2001 ) 2 33 bits of 0 padding ,B 2 Load Logical Thirty One (LLTG, LLTGR) takes the LLTGR) (LLTG, One Load Logical Thirty 31-bits of the 32-bit secondand operand low-order place them in bits R produces31-bit It a clean 64-bit address from a mode. addressing of regardless address, (X 2 1 2 Load Logical Thirty One - LLTG[R] R D R zSeries Low-order 32-bit 3 High-order 32-bit R - - Storage Operand Copyright Corporation IBM 2000, 2001 - - - Low-order 32-bit ) 2 (B Load Multiple High (LMH) works like LM except that it loads into the high-order 32-bits of 64-bit registers. Store Multiple High (STMH) works like STM except that it stores from the high-order 32-bits of the 64-bit registers. 1 2 Storage Operand High-order 32-bit R D Load/Store Multiple High - LMH, STMH zSeries Storage Operand Low-order 32-bits - - - 3 High-order 32-bits ) R 4 (B 4 Storage Operand D - - - Storage Operand Copyright Corporation IBM 2000, 2001 - - Low-order 32-bits ) 2 Load Multiple Disjoint (LMD) works like a Load Multiple plus a Load High. It can be used when the registers could not stored in a single contiguous area, as on call from an old 31-bit program to a new 64-bit one. It's performance is not better than LM plus LMH (B 1 2 Storage Operand High-order 32-bits Load Multiple Disjoint - LMD R D zSeries Low-order 32 bits 32-bit Register Storage Operand Copyright Corporation IBM 2000, 2001 000000000000000000000000000000000 1 2 The 32 bit (or low-order bits for LLGFR) of the second operand are loaded into the low-order 32 bits of the first operand register. The high-order 32 bits of the first operand register are set to zeros. R R Load Logical - LLGF[R] zSeries Storage Operand Low-order Low-order 16 bits Copyright Corporation IBM 2000, 2001 0000000000000000000000000000000000000000000000000 1 The 16 bit of the second operand are loaded into the low-order 16 bits of first operand register. The high-order 48 bits of the first operand register are set to zeros. R Load Logical Halfword-LLGH zSeries Low-order Low-order 8 bits Storage Operand Copyright Corporation IBM 2000, 2001 000000000000000000000000000000000000000000000000000000000 1 The 8 bits of the second operand are loaded into the low-order 8 bits of first operand register. The high-order 56 bits of the first operand register are set to zeros. R Load Logical Character- LLGC zSeries Copyright Corporation IBM 2000, 2001 1 ) 2 R (B 2 D Insert and Store Characters Under Mask High like ICM and (ICMH and STCMH) work exactly operate on the 4 high-order STCM except that they of the first operand register. bytes Insert/Store Characters Under Mask High zSeries Copyright Corporation IBM 2000, 2001 Load Logical Immediate Logical Load Insert Logical Immediate AND Immediate OR Immediate Under Mask (High/Low) Test New Instructions Immediate zSeries Immediate Copyright Corporation IBM 2000, 2001 1 LLIHH LLIHL LLILH LLILL R OP 016324863 Instruction 1 R The Load Logical Immediate Instructions (LLIHH, LLIHL, LLILH, LLILL) load an immediate 16-bit value of the 4 halfwords a 64-bit register. into any The other 3 halfwords are cleared to zeros. Load Logical Immediate - LLIxx Load Logical Immediate zSeries Immediate Copyright Corporation IBM 2000, 2001 1 ILIHH ILIHL ILILH ILILL R OP 016324863 Instruction 1 R The Insert Logical Immediate Instructions (ILIHH, ILIHL, ILILH, ILILL) insert an immediate 16-bit value of the 4 halfwords a 64-bit register. into any The other 3 halfwords are left unchanged. Insert Logical Immediate - ILIxx Insert Logical Immediate zSeries Immediate Copyright Corporation IBM 2000, 2001 1 NIHH NIHL NILH NILL R OP 016324863 Instruction 1 R The AND Immediate Instructions (NIHH, NIHL, AND an immediate 16-bit value NILH, NILL) logically of the 4 halfwords a 64-bit register. into any The other 3 halfwords are left unchanged. AND Immediate - NIxx Immediate AND zSeries Immediate Copyright Corporation IBM 2000, 2001 1 OIHH OIHL OILH OILL R OP 016324863 Instruction 1 R The OR Immediate Instructions (OIHH, OIHL, OILH, OR an immediate 16-bit valueOILL) into logically of the 4 halfwords a 64-bit register. any The other 3 halfwords are left unchanged. OR Immediate - OIxx zSeries Immediate Copyright Corporation IBM 2000, 2001 1 TMHH TMHL TMLH TMLL R OP 016324863 Instruction 1 R The Test Under Mask High/Low Instructions (TMHH, The Test TMHL, of the 4 TMLH, TMLL) tests the 16 bits of any halfwords of a 64-bit register against 16-bit immediate mask. Under Mask (TM). The condition is set like with Test Test Under Mask High/Low Under - TMxx Test * and* TMLH TMLL exist in ESA/390 as TMH and TML zSeries (BRCL) is like (BRASL) is like like is (BRASL) (LARL) computes the computes (LARL) Copyright Corporation IBM 2000, 2001 Note: the immediate designates a number of of number a designates immediate the Note: BRC but has a 32-bit signed immediate value. Branch Relative on Condition Long Branch Relative and Save Long Load Address Relative Long the be used to load LARL can only Therefore, halfwords. boundary. on a halfword address BRAS but has a 32-bit signed immediate value. address as would BRCL or BRASL, but instead of address as would branching, it places the address in first operand register. New Long Relative Instructionsb *BRCL and *BRCL and BRASL are ESA/390 added to zSeries ) 2 (B 2 are unexamined and are unexamined 3 and R 1 ) 2 ) is rotated to the left and result is unchanged. 2 (B 3 3 2 Copyright Corporation IBM 2000, 2001 (B 2 ,D 3 . R 1 ,D 3 ,R 1 ,R 1 RLL R RLLG R determines determines the number of positions to rotate unchanged. The value in R value The R in stored 6 D bits calculated from The rightmost RLL are and RLLG both model instructions For RRL, bits 0-31 of R Rotate Left Single Logical -RLL/RLLG * * RLL is added to ESA/390 zSeries ) ) 2 2 (B (B 2 2 ,D ,D 1 1 ) R LRVG ) STRVG R ) STRVG 2 2 (B (B 2 2 ,D ,D 1 1 Copyright Corporation IBM 2000, 2001 ) LRV R ) STRV R ) STRV 2 2 (B (B 2 2 ,D ,D 1 1 The low-order 2, 4 or 8 bytes of a register are loaded or The low-order 2, 4 or 8 bytes order. This is an assist in reverse stored in byte-wise between big/little endian. converting the high-order portion of register For Load Reversed, is remain unchanged. the second operand of 4 or 8 bytes, For Load Reversed can be a register (LVR, LVGR) Load/Store Reversed * * LRVH, LRV, LRVR, STRVH, STRV are added to ESA/390 STRVH R LRVH R zSeries (SLB, SLBR, (ALC, ALCR, ALCG, ALCGR) (ALC, ALCR, ALCG, ALCGR) (ML, MLR, MLG, MLGR) and Divide MLGR) MLG, MLR, (ML, Copyright Corporation IBM 2000, 2001 (DL, DLR, DLG, DLGR) treat their operands treatoperands their DLGR) DLG, DLR, (DL, as unsigned numbers, again facilitating arithmetic on again facilitating arithmetic as unsigned numbers, large integers. very Add Logical with Carry Add Logical with Logical Multiply Logical SLBG, SLBGR) use the condition code set by a SLBG, SLBGR) use the condition code set by previous instruction to participate in the operation so on large integers. can be performed that arithmetic and Subtract Logical with Borrow and Subtract Logical with New Logical Arithmetic InstructionsNew Logical Arithmetic *ALC, ALCR, SLB, *ALC,SLBR, ML, MLR, DL and DLR are ALCR, SLB, added to ESA/390 zSeries +1 and 1 +1 and the 1 +1 by a 32-bit +1 by 1 1 +1 by a 64-bit second +1 by 1 1 Copyright Corporation IBM 2000, 2001 (DSG, DSGR, DSFG, DSGFR) is the 64-bit remainder is placed in R DSG and DSGR divide a 64-bit R DSGF and DSGFR divide a 64-bit R second operand. The 64-bit quotient is placed in R 64-bit remainder is placed in R operand. The 64-bit quotient is placed in R Divide Single like Divide except that the 64-bit dividend is in rather than in both the odd 64-bit register only quotient and even and odd 32-bit registers. The are both 64 bits. remainder Divide Single Divide zSeries Copyright Corporation IBM 2000, 2001 The facility consists of 11 instructions which which instructions consistsof 11 facility The facilitate the manipulation of ASCII and Unicode are to z/Architecture. added data 1 Translationaugment Extended Facility They Extended, Translate ASCII to (Translate Test and UTF-8Translateand UTF-8to ASCII) are which available on G5/G6and z900 processors. available is not at GA initial facility This of z900, atbut will be added GA2. List Store Facility by Bit 16 of the list produced this presence/absence of the facility. indicates Extended Translation Facility 2 TranslationExtended Facility zSeries (CLCLU) is like CLCLE (MVCLU) is like MVCLE Copyright Corporation IBM 2000, 2001 except that it compare pairs of bytes rather than than rather compareofexcept that it pairs bytes even number an operates on only It bytes. single of bytes. except that it moves pairs of bytes rather than than moves rather except that it of pairs bytes even number an operates on only It bytes. single of bytes. Move Long Unicode Unicode Long Compare Move/Compare Long Unicode Long Move/Compare zSeries . Copyright Corporation IBM 2000, 2001 (UNPKA) converts packed decimal (PKA) converts ASCII numeric numeric ASCII converts (PKA) The low-order 4-bits of each byte are treated as a treated are each byte of 4-bits The low-order digit. decimal (sign=1100) positive always is The result 1 32 second to 16; is is length operand The first binary 0011 with on left the extended is Each digit setting code condition by indicated is The sign 1 32 to is 16; first is length operand The second characters to packed decimal format. characters to packed decimal Pack ASCII ASCII Unpack are and results validity checked for are not Digits operands overlap the if unpredictable to ASCII characters. to ASCII Pack/Unpack ASCII Pack/Unpack zSeries (UNPKU) converts packed decimal packed decimal converts (UNPKU) Copyright Corporation IBM 2000, 2001 (PKU) converts Unicode Basic Latin Unicode Basic converts (PKU) The low-order 4-bits of each double-byte are treated as as treated are each double-byte of 4-bits The low-order digit. a decimal (sign=1100) positive always is The result secondeven must be 16; is length operand The first 003 hex with on left the extended is Each digit setting code condition by indicated is The sign even must be 16; first is length operand The second Pack Unicode Pack Unicode Unpack are and results validity checked for are not Digits operands overlap. the if unpredictable to Unicode Basic Latin characters. Basic to Unicode numerics to packed decimal format. to packed decimal numerics Pack/Unpack Unicode Pack/Unpack zSeries (TP) tests for valid decimal decimal valid for tests (TP) Copyright Corporation IBM 2000, 2001 CC=0: alland digitsCC=0: sign valid CC=1: sign invalid atCC=2: least one digit invalid signone and at leastCC=3: digit invalid invalid Test Decimal digits and validThedigits codes. sign and results of thetest are reportedin thecondition code. Test Decimal - TP Decimal Test zSeries +1 1 (TROO) translates from a Copyright Corporation IBM 2000, 2001 The single-byte characters of the second operand are are operand second the of characters single-byte The table a from characters function single-byte select to used 1 register purpose general by to pointed are compared a against characters The function the If 0. register purpose general in character single-byte operation the value, this equals character function the to moved is character function the not, If terminates. location operand first R of the second The operand is length in register The second operand is not modified 256 of the table is The bytes length single-byte code to another single-byte code code to another single-byte single-byte Translate One to Translate toTranslate One One - TROO zSeries +1 1 (TROT) translates from a Copyright Corporation IBM 2000, 2001 The bytes of the second operand are used to select select to used are operand second the of bytes The by to pointed a table from characters function double-byte 1 register purpose general are compared a against characters The function 0. If the purpose register in general character double-byte operation the value, this equals character function the to moved is character function the not, If terminates. location operand first of the second The operand is length in R The second operand is not modified 512 of the table is The bytes length single-byte code to a double-byte code code to a double-byte single-byte Translate One to Two Translate One to Translate One Two - TROT zSeries +1 1 (TRTO) translates from a Copyright Corporation IBM 2000, 2001 The double-byte characters of the second operand are characters The double-byte table a from characters function single-byte select to used 1 register purpose general by to pointed are compared a against characters The function the If 0. register purpose general in character single-byte operation the value, this equals character function the to moved is character function the not, If terminates. location operand first R of the second The operand is length in register The second operand is not modified (64K) 65,536 of the table is bytes The length doube-byte code to a single-byte code code to a single-byte doube-byte Translate Two to One Translate Two to One - TRTO zSeries +1 1 (TRTT) translates from one Copyright Corporation IBM 2000, 2001 The double-bytes of the second operand are used to select select to used are second operand the of The double-bytes by to pointed a table from characters function double-byte 1 register purpose general are compared a against characters The function 0. If the purpose register in general character double-byte operation the value, this equals character function the to moved is character function the not, If terminates. location operand first of the second The operand is length in R The second operand is not modified (128K) 132,072 of the table is bytes The length double-byte code to another double-byte code code to another double-byte double-byte Translate Two to Translate Two to Two - TRTT