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64-Bit Z/Architecture Overview Part I: Application Facilities 64-bit z/Architecture Overview Part I: Application Facilities SHARE Nashville, TN Session 2824 Bob Rogers IBM Corporation [email protected] 1-845-435-1647 zSeries Copyright IBM Corporation 2000, 2001 Architecture Elements zSeries Part I - Non-Authorized Facilities Addressing Modes General Purpose Registers Non-modal and modal Instructions Addressing Mode Switching Instructions New Instructions in Support of 64-bit New Immediate Instructions Some other Interesting Instructions Extended Translation Facility 2 Copyright IBM Corporation 2000, 2001 The Style of z/Architecture z/Architecture has extended ESA/390 to 64-bit in a zSeries manner somewhat different than other platforms. For example, in PowerPC architecture, 64-bit addressing and 64-bit operation are inseparable. When running in 64-bit mode, all register operations also have 64-bit definitions. The ability to switch between modes is restricted to the supervisor. The z/Architecture definition separates the control of 64-bit addressing mode from 64-bit operations. This style of definition allows software to be extended to 64-bit in an evolutionary manner. 32-bit and 64-bit operations are supported in 24-, 31- and 64-bit addressing mode. Any program can switch between addressing modes and intermix 32-bit and 64-bit operations. Copyright IBM Corporation 2000, 2001 Addressing Modes Actual PSW zSeries 64-bit instruction address Addressing mode bits:00 = 24-bit mode z/OS Apparent PSW 01 = 31-bit mode 11 = 64-bit mode 31-bit IA 31-32 PSW bits 31 and 32 designate addressing mode. The 31-bit addressing mode bit is on in 64-bit mode. A PSW indicating 64-bit addressing mode will seem to indicate 31-bit mode to "unknowing" programs Address generation uses 64-bit Base and Index values and produces 64-bit addresses. Effective addresses are truncated to 31 or 24 bits in 31-bit or 24-bit addressing mode. Copyright IBM Corporation 2000, 2001 Renaming the bits zSeries The z/Architecture is a 64-bit architecture with several types of 64-bit registers and areas, such as 64-bit General Purpose Registers. The numbering of the bits for these entities is change to be 0 to 63. This may cause confusion when dealing with some of the compatible aspects of the architecture. For example, The ESA/390 Load instructions sets bits 0-31 of a General Purpose Register. In z/Architecture, the Load instructions sets bits 32-63, due to the renumbering of the bits. To ease understanding, sometimes the ESA/390 bit positions will also be provided in braces. Bit positions are usually designated after a dot. For example: LR R1,R2 sets R1.32-63{0-31} from R2.32-63{0-31} Copyright IBM Corporation 2000, 2001 General Purpose Registers zSeries 0 64-bit General Purpose Register 63 32-bit GPR 32{0} 63{31} The register is treated as 64-bits for: Address generation in 64-bit mode GPR operands of non-modal 64-bit instructions GPR operands of modal instructions in 64-bit mode The register is treated as 32-bits for: Address generation in 24/31-bit modes (so it seems) GPR operands of non-modal 32-bit instructions GPR operands of modal instructions in 24/31-bit modes Copyright IBM Corporation 2000, 2001 Address Generation Op R1,D2(X2,B2) [this is an RX example] zSeries 64-bit General Purpose Register 64-bit General Purpose Register Base Register + Index Register + Displacement 0 63 0 63 0 11 Address generation takes the value contained in a 64-bit base register plus (optionally) the value contained in a 64-bit index register plus the value of the 12-bit displacement in the instruction. The result is then truncated on the left depending upon the current addressing mode. In 24-bit mode, the leftmost 40 bits are set to zeros. In 31-bit mode, the leftmost 33 bits are set to zeros. In 64-bit mode, the 64-bit address is not truncated. Copyright IBM Corporation 2000, 2001 A "meta rule" of z/Architecture Since z/Architecture allows the intermixing of addressingzSeries modes and operand precisions, care was taken to ensure that old 32-bit programs could not inadvertently destroy register information which new 64-bit programs assumed to be preserved. The high-order halves of the 64-bit registers are visible only in 64-bit mode or when executing new instructions. When executing in 24- or 31-bit addressing mode and issuing only instructions which are defined in ESA/390, the high-order 32-bits of the 64-bit registers are opaque. Old programs, which do not save/restore the full 64-bit registers, cannot unknowingly alter the contents of the high-order halves of the registers. Copyright IBM Corporation 2000, 2001 Modal vs Non-Modal Instructions zSeries The term Non-Modal applies to instructions which perform the same operation regardless of addressing mode. For these instructions, addressing mode is only used during storage operand address generation. E.g. L always loads R1.32-63{0-31} from D2(X2,B2).0-31 The term Modal is applied to instructions for which the operation is different in 64-bit addressing mode than in 24-/31-bit mode. Specifically, the width of some or all register operands depends upon addressing mode. E.g. LA set R1.32-63{0-31} or R1.0-63 depending on mode. Copyright IBM Corporation 2000, 2001 Non-modal instructions (32) zSeries D2(X2,B2) Storage Operand R1 32-bit Register R2 32-bit Register ESA/390 32-bit operand instructions which behave as in ESA/390 - regardless of addressing mode. Bits 0-31 of the 64-bit GPRs are unexamined and unmodified Examples: LR, AR, ALR, L, A, AL Copyright IBM Corporation 2000, 2001 Non-modal (32) Example zSeries D2(X2,B2) Storage Operand R1 32-bit Register A R1,D2(X2,B2) ADD (32) takes the value of a fullword in storage and arithmetically adds it to the contents of the low-order 32-bits of a general purpose register. The high-order 32-bits of the general purpose register are neither interrogated nor modified. The operation is the same in all addressing modes. Copyright IBM Corporation 2000, 2001 Non-modal instructions (64) zSeries D2(X2,B2) Storage Operand R1 64-bit GPR R2 64-bit Register Operand New 64-bit operand instructions operate on 64-bit operands - regardless of addressing mode. All 64-bits of the first operand register are modified The second operand is also 64-bits wide Examples: LGR, AGR, ALGR, LG, AG, ALG Copyright IBM Corporation 2000, 2001 Non-modal (64) Example zSeries D2(X2,B2) Storage Operand R1 64-bit GPR AG R1,D2(X2,B2) ADD (64) takes the value of a 8-bytes in storage and arithmetically adds it to the contents of the full 64-bit general purpose register. The entire 64-bit general purpose register is both input to and output of the operation . The operation is the same in all addressing modes. Copyright IBM Corporation 2000, 2001 64-bit Analogs of ESA/390 Instructions Non-priviledged General Purpose Instructions zSeries AG[R] BRXLG LG[R] SLAG AGHI CG[R] LGH SLLG ALG[R] CSG LGHI SRAG NG[R] CDSG LMG SRLG BCTG[R] CGHI LNGR SG[R] BXHG CLG[R] LPGR SLG[R] BXLEG CVBG MGHI STG BRCTG CVDG MSG[R] STMG BRXHG XG[R] OG[R] Copyright IBM Corporation 2000, 2001 64-bit Analogs of ESA/390 Instructions zSeries Hex Floating Point Binary Floating Point Privileged Operations CEGR CEGBR LCTLG CDGR CDGBR LURAG CXGR CXGBR STCTG CGER CGEBR STURG CGDR CGDBR TRACG CGXR CGXBR Copyright IBM Corporation 2000, 2001 New Instructions w/ 64-bit Analogs zSeries Non-modal 32-bit Instructions Non-modal 64-bit Load Reversed - LRV, LRVR LRVG, LRVGR Multiply Logical - ML, MLR MLG, MLGR Divide Logical - DL, DLR DLG, DLGR Add Logical w/ Carry - ALC ALCG Subtract Logical w/ Borrow - SLB SLBG Store Reversed - STRV STRVG Rotate Left Single Logical - RLL RLLG * All these 32-bit non-modal instructions are added to ESA/390 Copyright IBM Corporation 2000, 2001 Non-modal instructions (64/32) sign propagation or D2(X2,B2) padding with zeros Storage Operand zSeries R1 64-bit General Purpose Register sign propagation or R2 padding with zeros 32-bit Reg Operand New instructions operate on 32-bit second operands into 64-bit first operands - regardless of addressing mode. The 32-bit second operand is internally extended to 64-bits before the operation is performed All 64-bits of the first operand register participate E.g. LGFR, AGFR, ALGFR, LGF, AGF, ALGF Copyright IBM Corporation 2000, 2001 Non-modal (64/32) Example D2(X2,B2) sign propagation Storage Operand zSeries R1 64-bit General Purpose Register AGF R1,D2(X2,B2) ADD (64/32) takes the value of a fullword in storage, propagates the sign to extend it to 64-bits, and then arithmetically adds the sign-extented value to the contents of the 64-bit general purpose register. The entire 64-bit general purpose register is both input to and output of the operation . The operation is the same in all addressing modes. Copyright IBM Corporation 2000, 2001 64/32 Instructions 64/32 Analogs of ESA/390 Instructions zSeries AGF[R] LPGFR ALGF[R] LNGFR CGF[R] MSGF[R] CLGF[R] SGF[R] LGF[R] SLGF[R] Other 64/32 Instructions LLGF[R] LLGT[R] Copyright IBM Corporation 2000, 2001 Modal instructions 64-bit General Purpose Register zSeries 64-bit mode 24/31-bit mode Instructions which operate differently depending upon addressing mode. Usually the difference is the width of register operands. e.g.
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