A DIGITAL PHASE ANGLE METER
FOR
POWER FREQUENCY MEASUREMENTS
BY
JOHN P. GILES B.Sc., B.E.
PROJECT REPORT FOR THE DEGREE OF MASTER OF ENGINEERING SCIENCE IN THE
SCHOOL OF ELECTRICAL ENGINEERING UNIVERSITY OF NEW SOUTH WALES
DECEMBER 1974 UNIVERSITY OF N.S.W.
46353 -2. SEP 75 LIBRARY DECLARATION
It is hereby declared that the work described in this thesis has been performed by the author and has not previously been submitted for a post-graduate degree to any other University or institution. ABSTRACT
A Digital phase angle meter is described which is primarily designed for power frequency phase angle measurements in the range 40 - 1000 Hz. The instrument is designed for measuring slowly changing signals of the type found in standardization or calibration of industrial phase angle indicators or transducers, where the 1 second or 10 second aperture time is of no consequence. The result is displayed digitally directly in degrees. No setting up procedures are necessary before taking a measurement. The accuracy of the instrument described is 0.5 of a degree plus or minus one digit. A frequency measuring function is also provided for measurements in the range 1 - 2000Hz. The factors which limit phase angle measure ment accuracy are described, together with the methods by which the induced errors are reduced or eliminated. ACKNOWLEDGMENTS
This investigation was conducted as part of the require ments for a Master of Engineering Science in the School of Electrical Engineering of the University of New South Wales*
The guidance of Associate Professor G* J. Johnson in this project is sincerely appreciated*
The comments of Mr* F* Lewin on the draft copy are gratefully acknowledged* 1
CONTENTS
page number
ABSTRACT ACKNOWLEDGMENTS TABLE OF CONTENTS 1 1. INTRODUCTION 6 1*1 The Definition of Phase Angle 6 1*2 Analogue Phase Angle Measurement Techniques 7 1.3 Digital Phase Angle Measurement Techniques 13 2. ERRORS IN ZERO CROSSING PHASEMETERS 20 2.1 D.C. Offset 20 2.2 Noise 21 2.3 Harmonic Distortion 21 2.4 Frequency Stability 23 3. DESIGN CONSIDERATIONS 24 3«1 General 24 3«2 Input Circuits 25 3.3 Phase Angle to Pulse Width Converter 27 3*4 Gate Circuit 31 3*5 Quantising Pulse Generator 32 3*6 Timing Signals Divider 36 3«7 Control Signal Generator 38 3*8 Display Divider 39 3*9 Display and Over range Circuits 39 3«10 Phase Sign Circuit 41 3.11 Frequency Measuring Circuit 43 3*12 Power Supply 43
4. INSTRUMENT OPERATION 47 5. PERFORMANCE OF THE PHASEANGLE METER 48 5*1 Measurement Method 48 5.2 Sources of Error 50 5*3 Effect of the Variation of Ambient Temperature 52 5*4 Performance as a Phase Angle Meter 54 5*5 Performance as a Frequency Meter 56 2
Contents cont*d page number
6. EVALUATION OF THE INSTRUMENT DESIGN 57 6.1 Design Philosophy for Further Work 57 6.2 Recommended Design Changes 59 6.3 Improved Input Facilities 60
7. CONCLUDING REMARKS 6l
8. BIBLIOGRAPHY 63
9. APPENDIX 65 Contents cont'd Page number
Figure 1*1 Typical patterns produced by a C.R.O. when sinusoidal voltages of different phases are applied* 7k
Figure 1*2 Single phase power-factor meter -
dynamometer type* 8a
Figure 1*3 Equilibrium position of the moving coils for an arbitrary phase angle theta. 9A
Figure l*4a Basic analogue phase angle meter* 10A
Figure l*4b Waveforms associated with the basic analogue phase angle meter* 10B
Figure 1*5» Basic analogue phasemeter with an extra flip-flop to remove the 0 degree, 180 degree ambiguity* 11A
Figure l*5b Diagram illustrating how the 0 degree, 180 degree ambiguity arises* 11B
Figure 1*6 Analogue phasemeter utilising both forward and reverse zero crossings* 12A
Figure 1*7 Diagram illustrating the effect of input noise on the phase detector output* 12B
Figure 1*8 Block diagram of phasemeters in which the phase angle is measured during a single period. 13A
Figure 1*9 Single period phase measurement using the heterodyne principle to obtain a frequency suitable for direct display in degrees* 15®
Figure 1*10 Basic multi-period digital phasemeter* 15A Figure 1*11 Diagram illustrating some of the measure ment periods due to the arbitrary start ing and stopping of the gate circuit* 17A
Figure 1.12 Two wire phase angle measurement circuit* 18a
Figure 1*13 Waveform for (a) lagging power factor 18a (b) leading power factor 4
Contents cont’d Page number
Figure 2.1 Distortion phase errors. 22A
Figure 3*1 Instrument block diagram. 25A
Figure 3.2 aero crossing detector circuit. 26a
Figure 3.3 Logic level translator circuit. 26A
Figure 3.4 Zero-crossing detector output waveforms. 27A
Figure 3*5 Special case of waveform illustrated in Figure 3*4. 27A
Figure 3*6 Zero crossing detector output with Channel B shifted by 180 degrees with respect to
Figure 3.5 28a
Figure 3-7 Phase measuring circuit. 29A
Figure 3.8a Timing diagram A. 29B
Figure 3-8B Timing diagram B. 29B
Figure 3.9 Gate circuit. 31A
Figure 3*10 Basic MECL gate circuit. 35A
Figure 3.11 Equivalent circuit of a quartz crystal. 34a
Figure 3*12 Crystal oscillator circuit. 34a
Figure 3.13 72MHz divider circuit. 35A
Figure 3*14 Timing signals divider circuit. 35B
Figure 3.15 Timing signals 36a
Figure 3.16 Control signal generating circuit. 3&A
Figure 3.17 Display divider circuit. 39A
Figure 3*16 Block diagram of the display devices. 40A
Figure 3*19 Display circuit. 40B
Figure 3.20 Sign sensing circuit. 4lA
Figure 3-21 Timing diagram for Figure 3*20. 4lA
Figure 3*22 Channel inversion circuit. 42A
Figure 3.23 Plus five volt supply circuit. 44a 5
Contents cont*d Page number
Figure 3«24 Minus five point two volt supply circuit* 45A
Figure 3*25 Plus or minus fifteen volt supply circuit* 46a
Figure 5»1 Block diagram of test set-up* 49A
Figure 5*2 Equivalent circuit of test set-up* 49A
Figure 3*3 Vector diagram of test set-up. 50A
Figure 3*4 Digital record of synthesizer period.
Figure 5*5a Digital record of the time interval unit's output for a fixed input. 51A
Figure 5»5b Analogue record of the time interval output for a fixed period. 51B
Figure 5*6 Output of the 3243L showing the variation of the measured period. 52A
Figure 5»7 Low frequency modulation of 3243L output. 53A
Figure 5«8 Variation of error with phase angle. 55A
Figure 6.1 Voltage controlled oscillator. 57A
Figure 6.2 Block diagram of phase looked loop. 59A
Figure 6.3 Circuit diagram of phase locked loop. 59A
Figure 6.4 Suggested input circuit. 60A -6- A DIGITAL PHASE ANGLE METER FOR POWER FREQUENCY MEASUREMENT
1. INTRODUCTION
This work is concerned with the description of an accurate digital phasemeter capable of operation in the power frequency range* The investigation was primarily concerned with the dev elopment of an instrument suitable for use in the calibration of general industrial phase angle and power factor measuring equipment* 1* 1 THE DEFINITION OF PHASE ANGLE For a phase angle to be meaningfult the two signals being invest igated must be two periodic signals of the same waveform, but rel atively displaced in time* The phase angle may then be defined as the angular separation between a pair of corresponding points selected arbitrarily* As measurements in the time domain may be made with very high resolution, it is usual to use a phase to time conversion* There are two obvious choices for the corresponding points: a) Maxima or minima b) Zero crossings In the phasemeter to be described the latter points were sel ected because the first derivative of a sine function is a maximum when the value of the function is zero* This means that the zero crossing point enables maximum resolution in time to be obtained* A further advantage is that the zero crossings are independant of the signal amplitude* If X is the time interval between corresponding zero crossings and u is the frequency, the phase angle 0 in radians as defined above is
0 se 2.TCX>H a —1*1 T where T is the signal period
Tr 1 -1.2 V -7A-
SINE 0 r JL A
TYPICAL PATTERNS PRODUCED BY A C.R.O, WHEN SINUSOIDAL VOLTAGES OF DIFFERENT PHASE ARE APPLIED Fi gure 1 - 1 7-
1. 2 ANALOGUE PHASE ANGLE MEASUREMENT TECHNIQUES a) Cathode-ray-tube Methods Where a measurement of relatively low precision is required, use can be made of a cathode ray oscilloscope* To obtain the phase angle between two voltages of the same frequency, one voltage is applied to the horizontal deflecting electrodes and the other to the vertical deflectors* The resulting pattern is elliptical in nature varying according to the relative amplitude and phase of the two signals being measured* The shape of the ellipse determines the phase angle according to the formula
sin © » + B “ A -1*3 where B is the y ordinate cut by the ellipse, and A is the maximum y value* (See figure 1*1) The quadrant may be determined from the orientation of the major axes of the ellipse and the direction in which the trace moves. Uncertainty as to the direction of the trace rotation may be eliminated by shifting the phase of one of the deflecting voltages in a known direction and noting the effect on the pattern* When the two voltages are in phase the resulting pattern is a straight line at 45 degrees to both axes* By utilizing this fact it is possible to insert a variable phase shifter in series with one of the signals and then vary the phase shift until the pattern becomes a line* The amount of phase shift to accomplish this result is then the desired phase shift* Obviously this method is more accurate than that obtained from equation 1*3• as the introduced phase shift can be determined more accurately than can the division of an elliptical pattern* If an oscilloscope with a circular time base is available, two further methods present themselves* The circular timebase is adjusted to have the same frequency as the input signals* Their relative phase is indicated by the angular position on the circle - one complete revolution being 3&0 degrees* In one method, the signal whose phase is to be measured is applied to the electrode controlling the beaus intensity, which is biased approximately to cutoff* The resulting pattern is a semi circular arc, the position of which is a function of phase.
The other method consists of deriving zero crossing pulses -8A-
MAINS LOAD
SINGLE PHASE POWER-FACTOR METER DYNAMOMETER -TYPE Figure 1-2 -8
and using these to modulate the beam intensity* The position at which the circle is interupted by the pulse is used to determine the relative phase* b) Phase Determination by Voltage Addition This method consists of superimposing the two voltages involved and then varying the amplitude and phase of one of the voltages until the sum is zero* The phase angle is then related to the phase shift required to give zero output* In practice the two voltages whose relative phase is to be determined are applied to a differential voltmeter* One signal is passed through a variable phase shifter and amplifier* When a null is obtained the relative phase shift can be obtained from the phase shifter* c) Dynamometer Phase Angle Meters For a long period the most usual industrial phase angle meter has been the electrodynamic or rotary iron type* These instruments indicate the phase angle directly, as distinct from instruments from whose readings the phase angle may be calculated* For example, the phase angle may be calculated by dividing the watts supplied by the Volt-Amperes of the system* Dynamometer power factor meters, like wattmeters, have a current circuit and a voltage circuit* The former carries the current in the circuit whose phase angle is to be measured* The voltage circuit is usually split into two parallel paths, one inductive and one non-inductive* The deflection of the instrument depends on the phase difference between the main current and the currents in the two branches of the voltage circuit* As an example of this type of instrument, an electrodynamic type single phase phase angle indicator will be described* Figure 1*2 illustrates the basic principle* The two fixed coils FF carry the load current and thus their magnetic field is proportional to the main current* Pivoted within this field, between the fixed coils, are two coils A and B rigidly fixed at an angle of 90°degrees* These coils move together and carry the pointer which indicates on a scale* Both coils A and B have identical windings and so produce equal magnetic fields, 90 degrees displaced in time and space, when equal currents at 90 degrees are passed through them* The resistor R and inductor L -9A-
90-0
FIELD FIXED DUE TO FIXED COILS
EQUILIBRIUM POSITION 0 F THE MOVING COILS FOR AN ARBITRARY PHASE ANGLE 0 Figure 1 - 3 -9-
in series with the coils are adjusted so the currents are equal when the frequency is at its normal value. At other values of frequency the two currents will be different due to the variations in reactance of the inductor with frequency. There is no controlling torque on the moving system - the currents are led into the coils by fine ligaments which exercise no control, The operation of the instrument is as follows (Reference 7) and figure 1*3* Assume that the field of the two fixed coils is uniform, and in the direction arrowed. The torque on each coil for the given current will be maximum when the coil is parallel to the field, ie. along XX. Suppose that when the phase angle is 0 the coils take up a position of equilibrium displacedOfrom the vertical. Then the torques due to the two coils must be equal and opposite. The current in coil A is in phase with the system voltage, and the field in which it moves is proportional to the system current. Coil A is essentially a wattmeter movement displaced 90°- 0 from the maximum torque position. The torque on a is
TA * kVI Cos 0 Cos (90°-0) -1.4 where k is a constant. Similarly, since the current in coil B lags 90° on the system voltage, coil B is a varmeter movement.
Tb - kVI Sin0 Cos © -1.5 At rest in the equilibrium position
TA = tb or Co60 Cos (90°-0) « Sin0 Cos© which reduces to Tan © = Tan0 or © « 0 ie. The angular position taken up by the coils is equal to the system phase angle. Rotary iron instruments are constructed of three windings mech anically spaced at one hundred and twenty degrees. These attract an iron attached to the moving spindle. One of the signals to be measured is connected to a network of inductors and capacitors which produce an approximately one hundred and twenty degree magnetic field in the three windings. The second signal is connected to a single central coil. In operation the rotary iron -10A-
Reference Limiting Zero input amplifier detector
RS Low pass Flip-flo p filter
Signal Limiting Zero input amplifier detector
Meter calibrated in degree*.
BASiC ANALOGUE PHASE ANGLE METER F igure 1 -4a -1GB-
a) Input to channel A zero crossing detector
(b ) Input to channel B zero crossing detector
(c ) Output of channel A zero crossing detector
( d) Output of channel B zero crossing detector . IK______I \ (e) Channel A trigger pulse f IY I[ Itv ^ (f)ChannelB trigger pulse r
(g) Output of R.S.flip-flop If !il l! li (h) Gated output •------■------H ' i
WAVEFORMS ASSOCIATED WITH THE BASIC ANALOGE PHASE ANGLE METER Figure 1 - 4 b -10- is held in a position corresponding to the phase angle by the interaction of the three phase and single phase fields. Electrodynamic and rotary iron instruments both suffer from a high sensitivity to line current and frequency changes. This sensitivity is due to the use of frequency sensitive phase shifting networks which are inherent in the operation of the instrument. d) Transducer Type Phasemeters The dynamometer is a complex instrument when compared with a moving coil instrument. This fact, coupled with the increased use of recorders, data loggers, and so on, in power systems has led to the development of the black box phase angle to current transducer with a D.G. moving coil meter used as the readout device. This latter device allows smaller overall dimensions and increased versatility. Nearly all transducers operate on the zero crossing principle. The basic transducer is shown in Figure 1.4a and associated waveforms in Figure 1.4b. The signal and reference inputs are first amplified and limited to •symmetrical1 square waves. These are in turn applied to zero crossing detectors which generate fast pulses to trigger the divide by two flip-flops on either positive or negative going zero crossings. The output pulse train has a pulse duration directly proportional to the phase difference. Finally, low pass filtering extracts the mean D.C. component to be applied to a meter calibrated in degrees. A design on the above lines is described by Ehret, Wood and Thompson (Reference 1). In their design, one of the input channels incorporates a switchable zero or one hundred and eighty degree phase shifting network. The instrument is so arranged that the signal presented to the flip-flops is always within the limits of 30 - 330 degrees. This ensures that the flip-flops do not operate at or near the 0 - 360 degree cross-over point. In the cross-over region, the output of the flip-flop becomes spurious. This is due to the approaching coincidence of the set and reset pulses. The degree to which these angles can be approached depends on the amount of noise present at the input, the input level detector stability and the flip-flop response time. -11A-
Rtf erence Limiting Z ero input amplifier d et ect o r
Low pass f i Iter
S i gnat Limiting Zero input " amplifier detector
Meter cali brated in degrees
BASIC ANALOGUE PHASEMETER WITH AN EXTRA FLIP-FLOP TO REMOVE THE 0°18Cf AMBIGUITY Figu re 1 -Sa —11B -
i
Channel A
C hann el B
i-e- A
—360"- 0 — B
DIAGRAM ILLUSTRATING HOW THE O^ISO0 AM B1GUI T Y
arises F i g u r e 1 - 5b 11
The inversion of the input signal is dependant on the D*C. out put voltage level* If the voltage corresponds to a phase angle of greater than one hundred and fifty degrees removed from the one hundred and eighty degree point, ie. if it is not within the bounds 30 - 330 degrees, then a one hundred and eighty degree phase shift in one input signal takes place to bring the measured phase angle back within the required bounds* This design utilizes an active filter to smooth the output of the R*S* flip-flop before being applied to the readout device, a moving coil meter* Ehret, Wood and Thompson*s design was intended primarily for the frequency range lOKHz to lOOKHz, and consequently the averag ing effect of the active filter and the meter amplifier should correct for any noise on the input signal* However, no circuits are included for the reduction of errors caused by harmonic dis tortion or D*C* offsets in the input signal* The circuit has to be temperature compensated, and this is achieved through the use of a temperature variable voltage applied to the inverting input of the active filter stage* C*J. Pauli in his paper (Reference 2) describes the way in which two flip-flops can be connected to provide for the elimin ation of the 0° , l80° uncertainty (See Figure 1*5)# Pauli then examines the problem caused by harmonically distorted signals* The zero, one hundred and eighty degree uncertainty arises from the triggering process of the phase measuring flip-flops. Assume that a negative edge triggered flip-flop is being used* The waveforms of the inputs to the flip-flop are shown in Figure l*3h* As can be seen from the diagram, two outputs are possible; one representing 0, and the other 3&0 - ©, depending on which channel "set” the flip-flop first* Returning to the definition of phase angle, it is evident that if the zero crossings are shifted in time then an error will result* The main problem in implementing the design shown in Figure 1.5 is the limiting amplifiers, as they are called on to provide a signal with an equal mark-space ratio* The error A 0 resulting from a given mark-space ratio variation is given by:-
n 0.^5 ( A m/s) -1*6 where A 0 is measured in degrees and A m/s is a small mark-space -12A-
(a) CIRCUIT DIAGRAM
AVERAGE
(b) METER CURRENT WAVEFORM
ANALOGUE PHASEMETER UTILISING BOTH FORWARD AND REVERSE ZERO CROSSINGS Figure 1-6 -12 B —
Channel A
Channel B
Phase detector output in absence of noise
r -p) Phase detector output error with noise on channel -I B 11 ;! i Phase detector output terrors with noise correction - i
Correction circuit senses error states
DIAGRAM ILLUSTRATING THE EFFECT OF INPUT NOISE ON THE PLEASE DETECTOR OUTPUT Fi gur e 1 - 7 -12- ratio error expressed in percentage, i.e., if there was a +1% uncertainty in the m/e ratio of both the amplifiers, a worst case phase reading error of 0.9° would result# To obtain this degree of m/s ratio precision requires complex feedback correct ion circuits# In order to eliminate this variation as a source of error, the arithmetic mean of the apparent phase differences as measured between both positive and negative-going zero crossings is taken# Pauli utilised a dual version of the flip-flop as shown in Figure 1*5 and fed the two signals to a current switching circuit as shown in Figure 1#6# The meter inertia is used to give the average current which is proportional to the phase angle# The Hewlett Packard model 3575A (Reference 10) works on a similar principle to that of C#J# Pauli# The Hewlett Packard design however replaces the analogue meter with a digital panel meter as well as incorporating circuitry for correcting false triggering due to noise on the input signals# This is accomplished by looking at the outputs of the two channels and considering these, together with the inputs themselves, a6 binary variables# These four binary variables have sixteen possible states, eight of which are caused only by false triggering of the phase detectors# The instrument has eight quad input gates connected to the four binary variables, so that when any one of the eight error states occurs, one of the gates gives an output# This output is used to trigger the phase detector at fault into its proper state# High speed logic is used to ensure a phase detector is only in an error state for a very small fraction of a period, as Bhown in Figure 1.7# Hence only a small error results# The stated accuracy is £0.5° for the phase measuring circuits, plus +9*2° for the panel meter readout, giving a total worst case error of j^0#8°# The Hewlett Packard instrument has four frequency ranges to help eliminate noise outside the frequency band of interest# Many designs of phasemeter utilise narrowband filters to overcome the noise and harmonics problem# The filter is usually a super heterodyne type circuit that uses IF filters# This means considerable tedium for the operator as the phasemeter has to be -13A-
Reference Zero Display & input detector counter
Flip-flop GATE
signal Limiting Zero fixed freq. inpuF amplifier detector oscillator
BLOCK DIAGRAM OF PHASEMETERS IN WHICH THE PHASE ANGLE IS MEA5UR ED DURi NG A SINGLE PERIOD Fi gure 1-6 -13- set up by frequency tuning each time the signal frequency is changed* (See also page 14 ) 1.3 DIGITAL PHASE ANGLE MEASUREMENT TECHNIQUES Digital phasemeters are finding increasingly wide applic ation in phase measurements because digital phase measuring instruments have a number of advantages in comparison to analogue devices* These include high accuracy, no subjective readout error, recording convenience, capability of feeding results to a digital computer, and the possibility of completely automating the measuring process* Digital phasemeters are basically phase shift to time inter val converters, of which there are two typesJ- (A) Phasemeters with the phase shift measurement taken over one period* Phasemeters which make the phase shift measurement during one period and do not indicate the phase difference in degrees have a fixed quantisation frequency. The general block diagram is shown in Figure 1*8* The two input signals are converted by the limiting amplifiers and zero crossing detectors into short pulses corresponding in time to the zero crossings of the input signals. These pulses are applied to a flip-flop which, when the switch is in the phase position, generates a pulse whose length is proportional to the phase shift (time shift) between the two signals. This rectangular pulse is applied to the gate circuit which then passes quantising pulses from the fixed frequency oscillator to the counter and display unit* The number of pulses (N^) is equal to N-, « sf°.f / 360F -1.7 v q where f is the quantising frequency, F« the signal frequency* q i.e* is proportional to the phase shift, 0 in degrees* If the signal frequency is not known, it is necessary to measure the number of quantising pulses N^, which occur during a full period. This is accomplished using the switch in the period mode. For this case
0° - 360.N0 1.8 Phasemeters of this type have the following faults; Hack of a direct indication of the measured phase shift in degrees, the presence of errors associated with instabilities in the signal and quantising generator frequencies, and the absence of quantising error averaging. The maximum quantising frequency error, $ increases with an increase in signal frequency.
& * 360°.F -1.9 f q There is also an additional error due to frequency instab ility of the signal A F/F and the quantising generator Af/t equal to - q q gaddnl = 0° ( A F/F + A fq/f ) -1.10
From the above, it is evident that the frequency range of phase meters of this type is limited to low frequencies, due to the increase in the quantising error with frequency. To obtain a direct reading of phase angle in degrees, the quantising frequency must be 36.10n multiplied by the input frequency. The variable quantising frequency may be obtained by a conventional multiplication of the input signal. This technique is possible as the phase difference between two waves is not affected by heterodyning both waves simultaneously with the same voltage, and rectifying to convert to a new frequency. For example, if two signals of frequency 50Hz and differing in phase by 30° are separately mixed with 1050 Hz voltages that have the same phase, then the two l,CC0Hz difference frequency waves produced by the mixers will likewise differ in phase by exactly 30°. It is necessary, however, for the two heterodyning signals to have identical phase. If they do not, then their difference will be added to, or subtracted from, the input signal phase difference. Let the quantizing frequency be represented by ASin(2rcF^t+0) where F^ is the quantizing frequency and BCos2 rf Ft is the input signal, then the amplitude modulated signal will be «A(l+raCos2 Tt Ft) (Sin2 rt F t+0) -1.11 q where m is the modulation factor. -15 B-
O b-
LU X X U to q o Ll o Z X x X CL X vD LU X Q Z > o Z 0 x > LlI < f—* X LU X X cn LU o 1 b- b- o x CD x Z cn cn o i z> X cu h- O 1— z X 3 LU OT X X LU X x CQ 3 < CO l— 5 3 CO > LU CJ CO z < X X X X a o x o x x X LU < X z UJ _J < CD b- Z CD CO o u c 0) To -+-> L- 3 c => 1 sec. gate Reference Limiting Zero amplifier detector Flip-flop Limiting Ze ro Signal 72Kh* input amplifier detect or BASIC MULTI-PERIOD DIGITAL PHASEMETER Fi gure 1- 10 -15- Expanding - A(l+mCos2 TT Ft) (Sin2 tt F t+0) q output signal * A Sin(2 Tt Ft+0) + Am Sin (2tt(F q+F) t + 0 ) +Am Sin (2 TT (F -F)t + 0) -1.12 “ n In the phase meter this output signal is filtered by a band pass filter centred on a frequency 36.1Gn times the input signal, ie. 36 x 10nF The frequency, F is automatically adjusted so that F -F = 36.10nF. q q Thus the only remaining term in equation 1.12 is Am Sin(2 n (F -F)t + 0) 1.13 5 ** which can be rewritten as K Sin(2 tt (360.10n.F)t + 0) This equation 1.13 represents a signal of frequency 36.10n times the input signal and has the same phase angle as the input signal. This type of phasemeter is shown in Figure 1.9* It is essentially wideband, but this is because the frequency of the in put signals is converted which results in additional errors assoc iated with the instability of the phase characteristics of the filtering elements. The circuitry for implementing the variable quantisation frequency generator is complex. (B) Phasemeters with the phase shift measurement taken over more than one period. Early phasemeters in this group had a constant measurement time, set by a highly stable generator. Quantising pulses were formed by a separate generator. The mode of operation of this type of phasemeter is as follows: The input signals are converted by limiting amplifiers and zero crossing detectors into a pulse train. The pulse width being proportional to the time shift between the measured signals. (Figure 1.10). A gate circuit fills these pulses with quantising pulses at, say, 72KHz. This signal train is applied to an all purpose counter through a two to one divider. The counter measures the number of pulses arriving in one second. The number of pulses received by the display counter from the quantising gener- ft-fcQp ill 1 c? A +,r»o*i y> Oyn •? a Ann r\1 4«* a 1.14 16- where is the total on time of the pulse trains* The number of pulses arriving at the counter during the measure ment time t is equal to Ft • The number of pulses arriving at the counter during the measurement time is given by N0 « yc -1.15 Substituting from 1.14 tO f jrt '0 q "meas -1.16 2.360° 3 For the example above, f * 72.10 Hz and t =1 second, p ^ Q ®®&fl therefore = 10 0 . The phase measurement has dimensions in degrees and is independent of the input frequency. This method has the following advantages: Relatively simple equipment, measurement indicated in degrees, quantisation error reduced, and frequency range expanded by averaging. One disadvant age of this phase meter is that there is an error, A 0^ due to the instability in the quantising generator frequency, the instab ility in the measurement time, and a measurement error, A 0^ associated with the arbitrary nature of the start and stop. The latter is caused by the fact that the measurement period is not an even multiple of the signal period. Now A 0 « 0 ( A f /f + A t/t ) -1.17 1 q q meas The maximum error A 0^ is equal to AfL « 90°/Ft -1.18 c. meas From equation 1.18, A 02 is a function of frequency. The fre quency range of instruments of this type is limited from below, ie. For a measurement time of 10 seconds and a desired accuracy of 0.2# the input frequency should be 50Hz or greater. If a one second measurement period and a 50Hz signal are considered, the best accuracy should be 2#. From equation 1.17 it is evident that the error associated with the instability of the quantising frequency generator and the measurement time can be eliminated if the two instabilities can be made to have equal and opposite values. This is easily accomplished by using a single generator to form both the quant ising pulses and the measurement time. The measurement time is set by dividing the quantising pulse frequency. Smirnov et al (Reference 11), postulated a ’’weighting" * (b) ] (d) DIAGRAM ILLUSTRATING SOME OF THE MEASUREMENT PERIODS DUE TO THE ARBITRARY STARTING AMD STOPPING OF THE GATE CIRCUIT Figure 1-11 17- system to reduce the problem of arbitrary start and stop. The "weight” of the given measurements obtained at the beginning and end of the measurement times is reduced. This can be achieved by reducing the repetition rate of the quantising pulses at the beginning and the end of the measurement times!. The operation of this type of phase meter is analogous to that shown in Figure 1.10, except for the fact that the quantising pulses are generated by a frequency controlled generator. The measurement period is fixed and so is the total number of pulses which are generated by the quantising pulse generator over the measurement period. This means that for the first and last periods of the input signal only 50 pulses are generated for some nominal phase shift, whereas for these pulses which occur in the middle of the measurement cycle, 500 would be generated; thus the effect of an arbitrary start is reduced considerably. The arbitrary start and stop problem can be best illustrated as follows: Consider a 1.5Hz signal with a phase difference between the two channels of 180 degrees. Figure 1.11 shows the respective signals. (a) is the input signal to the frequency counter. The counter only operates for one second and three arbitrary one second periods are shown (b), (c) and (d). In (b), pulses only reach the counter for Y> second and thus 120° would be displayed. In (d), pulses reach the counter for 2/5 second and thus 240° would be displayed. In (c), it is counting for exactly # second and the correct 180° would be displayed. A maximum error of 33V# can occur in the above case. Refer* ring back to equation 1.18 A 0? * 90°/l*5Hz 1 second SB 60° ie. 0 * 180 - 60° or a 33># error as shown above. McKinney (reference 4) describes a phasemeter which measures the average time intervals between appropriate pairs of zero crossings of the two signals over an integral number of cycles. A gate which interrupts the quantising pulses i6 controlled by the output of a flip-flop as described earlier. The output of the -18 A — MAINS LOAD TWO WIRE CIRCUIT Figur e 1 -12 WAVEFORMS FOR (a) lagging, p.f. (b) leading p.f. Figure 1—13 18- gate la connected to the numerator input of a present digital frequency ratio meter* Another device which generates a pulse for each zero crossing of one of the signals is connected to the denominator input* The frequency ratio meter displays the total number of pulses accepted by the gate for N/2 periods of the input, when N is the value of the denominator which is preset on the frequency ratio meter* To obtain the phase angle, the frequency of the input signal must be measured* The instrument is not direct reading in degrees* The preceding information relates to the development to date of digital phase meters* However phase angle and power factor are closely related* ie* power factor (p*f) * Cos# In this area it is interesting to briefly look at a digital power factor meter described by Bombi and Ciscato (reference 6). The theory of operation of their instrument is as follows: Consider the circuit shown in Figure 1*12* Under steady state conditions, voltage and current delivered to the load are v(t) « Vm Sin Ut -1.19 i(t) * Im Sin (Ut-0) -1.20 where Cos# is the load power factor* Cos# is positive if power flows to the load and negative if reactive power flows to the mains* From figure 1.13 p.f. * L) S-l -1.21 Vm where S s P2 v(t) dt 'H -1.22 and t. * J0, t as tt lagging power factor 1 W V t- « 0, t0 * tt +& leading power factor -1*23 + d U) Thus a measure of the power factor is available from eval uation of the integral of v(t) over the interval when both voltage and current signals are positive* This evaluation can be performed digitally by a voltage to frequency converter. The voltage v(t) is applied to the A-D converter during the interval t.. to tp and an output pulse occurs each time the X C. y integral of the input signal increases by a fixed amount k ref. The total number N of pulses delivered in the interval t2~t^ is the maximum integer number less than the analogue quantity n. N »/> v(t) dt = _S___ 2 kVref kVref -1.24 ie. from equation 1.21 disregarding the quantisation error p.f. » U kVref N-l -1.25 V m The dependence of the power factor on the line voltage and frequency can be avoided if V^^ is made proportional to according to V ,*hV ref * -1.26 Equation 1.25 becomes p.f. * hkN-1 -1.27 To avoid too high a pulse repetition rate of the A-D converter and to retain the same resolution it is convenient to compute the power factor over n periods. Consequently equations 1.24 and 1.27 become N « nS -1.28 hV ref p.f. a hkN - 1 -1.29 n The implementation of this design involves a voltage to frequency A-D converter which has a variable reference voltage. This reference voltage is generated by sampling the crest value of the input voltage integral with a sample and hold circuit. This instrument in common with most others has the obvious fault of incorrect readings for other than pure sine waves. Some cure can be effected by using two matched low pass filters inserted in the voltage and current signal paths. Following on from the last point above, is the difficulty of defining the phase angle for signals other than pure sine waves. In all discussions in this work the phase angle is considered to be that of the fundamental components of the two signals. 20- 2* ERRORS IN ZERO CROSSING PHASEMETERS* As ideal sine waves are never found in practice, it is important to consider the effect the various signal imperfections can have and then to design suitable circuitry to minimize their effect* The design employed is based on zero crossings and thus any variation in the zero crossing can cause an error* A signal can be considered in terms of its Fourier components* ie* A funda mental of constant frequency plus Imperfections which include D*C* offset, noise, and harmonic distortion* Obviously if the two waveforms are identical all the zero crossings will be shifted by the same amount and the basic definition of the phase angle holds* However this is usually not the case* 2.1 D*C* OFFSET D*C* offsets are usually evident due to the now usual solid state direct coupled stages* Only if a transformer input is used will there be no D.C* offset. The equation of the signal will be E » Sin wt + E^ Here we have assumed only a D*C* offset and no other imperfections for simplicity* The zero crossings are the solution to the equation E^ Sin wt ♦ EpC a 0 ie Sin wt = -Edc Now if -E^ is small then we have 0 ie. wt « *Ex)c -2L That is, for a measurement to an accuracy of 0.1$ for a one volt signal ",EDC//‘E1 « 0.1/100. ie. ^ IraV This order of offset can well occur within the instrument's input circuitry as well as in the signal being measured. It follows that it is necessary to eliminate the effect of D.C. offsets on the result. 2.2 NOISE Noise can be considered as a randomly varying D.C. offset voltage for which the integral goes to zero for large values of time. As noise is essentially random in nature its effect may be effectively cancelled by making the measurement period long in terms of the signal frequency. This is the method used in this design. In a similar manner periodic signals not harmon ically related to the signal cancel out over the long measurement period. 2.3 HARMONIC DISTORTIONS Harmonic distortion is the most usual signal distortion and also the hardest to control effectively. In general, both phase shift and attenuation are frequency dependent so that all harmon ics will be modified in such a way that effective cancellation of the zero crossing errors is impossible. McKinney (reference 4) has shown that to analyse the error due to harmonics, full information is needed about the amplitude and phase relations of the significant harmonics. Where it is impractical to obtain this information, the following simplified analysis provides a useful guide to possible errors. A periodic signal with repeat frequency w/2tc may be ex pressed in terms of its Fourier components as follows: m rt E(wt) * E. Sin wt + £e Cos mwt + ZiE Sin nwt a. Itl n with \ ^ 0 where the first term on the right of the equation is the undist orted signal. The positions of the zero crossings are given by the solutions of the following equations in which the odd and even -22 A- Distorted signal ■Harmonic components DISTORTION PHASE ERRORS Figure 2“1 22- cosine harmonics have been separated. K H E^ Sin wt + E E^ Cos(2^+l)wt ♦ E Cos 2rwt + ^ E nwt ^-\ Y z EL For small values of harmonic distortion the behaviour in the region of the positive zero crossings may be approximated as follows. Q E, wt ♦ E + A E *0 1 1*1 q r-i r The phase error is therefore r Q R -n E E + ZL E / B. —2.1 A &F * " l r< q r~ \ r_ Similarly the negative zero crossing phase error is Figure 2.1 illustrates these errors in the case of the cosine component of second harmonic distortion. Now if both zero crossings are used the errors in phase are additive, ie. The phase error is Q ^ 0F + A 0R * -2 C /Ej -2.3 which indicates that under the conditions of this evaluation only the cosine terms of odd order contribute to phase errors when all contributions of all zero crossings are considered. The cosine terms of odd order reach a peak as the funda mental goes through zero. The resultant signal zero crossing shift is determined by E_ Sin© = E Cos n© 1 n where E is the fundamental amplitude, E is the amplitude of th1 ^ the n harmonic and © is the shift in the zero crossing. For small © this equation reduces to E_ © ^ E 1 n -23' therefore 0 ^ E n radians If, for example, E^ ■ 100 E^ or the harmonic distortion is 40db below the fundamental 0 a 0.01 radians or 0*37 degrees at worst. The total harmonic distortion D,p can thus be calculated. Dm « D where D is the percent harmonic distortion T rTd n th n contributed by the n harmonic, id. A0(max) a 0.57fyp degrees. 2.4 FREQUENCY STABILITY Since the apparent phase angle is dependent on the frequency of the input signal, the frequency must be known and be stable within the desired accuracy of the phase angle during a measure ment. If the frequency variations are random an average value of the phase angle can be obtained by making the measurement over many cycles of the input signal. 24- 3* DESIGN CONSIDERATIONS %1 GENERAL From the Introduction it is clear that the zero crossing, multi-period measurement is the best basis for a digital phase meter* Accordingly the following basic criterion were laid downs- 1) Direct digital display of phase angle in degrees 2) Measurement precision of - 0.2° to - 0*3° 3) Frequency range to cover at least the power frequency range ie* 50Hz to 400Hz 4) No set up or calibration procedures to ensure easiest use of the instrument* 5) Minimum circuit complexity with due regard for accuracy* 6) Reduction to a minimum of errors due to harmonic distort ion, D.C* shifts, noise and frequency instability* 7) Physically small package* 8) Temperature range 5° to 40°C. 9) Frequency measuring capability. 10) Input range lOOmV to 300Vrms* 11) Digital throughout* The minimum complexity requirement initially ruled out any systems using variable frequency quantising pulse generators* Taking the requirement for a low frequency capability of 50Hz at - 0*2 degree and substituting this into equation 1*18, INSTRUMENT BLOCK DIAGRAM C7) cn > i- O j < -2SA- CD >. cj "7 L CT) cn L_ D 90°/Ft rneas 0.2 * 90 /50t meae ie. 10 seconds meas A measurement time of 10 seconds was chosen. A one second measurement period was also planned to provide a comparison of accuracy. The overall circuit was envisaged as follows. See Figure 3*1* 3.2 INPUT CIRCUITS The input circuit must convert and limit the amplitude of the input signals into a pulse waveform, with transitions at the zero crossings, compatible vithTTL logic. Therefore the input circuits should be amplitude independent and have fast and large output changes for small changes of the input about zero volts. The most basic circuit for this application would be a differental operational amplifier. Although this would be accurate the amplifier would go into saturation except when switching. Therefore, each time a zero crossing took place several milliseconds would be lost during the amplifier's re covery from saturation. The simplest way to prevent the amp lifier going into saturation is to use a circuit as shown in Figure 3.2. In this circuit diodes are used to provide feedback bounds. Feedback bounds are necessary to ensure that the amplifier does not go into saturation. The amplifier output is bounded by one set of diodes or the other, depending on the sign of the input voltage. In the circuit shown, the output voltage swing is limited to approximately plus or minus one volt. Within the feedback bounds the circuit operates linearly and preserves the voltage balance at the summing point. A shift of a fraction of a microampere in the input current is sufficient to cause an output transition to take place. Four diodes are used instead of the possible minimum of two. The reason for the apparent duplication is to increase the speed of the zero detector. Assume an input current of one microampere is flowing in the — 26A— 1 K 1N 914 A x 4 rfcht^hT^ Input (^~ “I 22 pF 50K to Logic Level translator (a) Circuit -1 Volt (b) Transfer characteristic Figure 3-2 ZERO CROSSING DETECTOR from zero crossing - detector LOGIC LEVEL TRANSLATOR Figure 3-3 -26- input resistor. To preserve the current null at the summing point of the operational amplifier a corresponding one microampere flows in one of the feedback diodes. However a diode with only one microampere flowing through it operates more like a logar ithmic resistor than an ideal diode, and therefore the transition is slow. This problem is overcome by the second pair of diodes and the resistor. The IK value will cause a current of 400 ju, A to flow in the second diode and therefore a very quick trans ition should take place. The transfer curve of this comparator is rhown in figure 3*2b. From this diagram the sharp transition for a very small change in input current can be seen. The limiting factor in circuit speed is the slew rate of the operational amplifier. The slew rate determines the speed with which the second diode can be turned on or off. The 301A inter- grated circuit has a slew rate of 10V/ps. For input signals below 0.5 volts peak to peak the output approaches a sine wave, as expected, as the input signal tends to zero. With the potent iometer shown, the input range is 150raVrms to 300 Vrms. The upper range is limited by the power rating of the potentiometer (2 watts). The output signal of this stage will be a sequence of pulses of approximately one volt peak to peak amplitude, but to drive the TTL logic an output of 0 to +5 volts is required. The signal is made TTL compatible using the circuit shown in Fig.3.3* Here the 3«3 volt zener diode clamps the output at OV or 4V in the low and high states respectively for TTL logic. The 301A operational amplifier was chosen rather than the more usual 710 because the 301A has a large differential input volt age and lower input currents. The 710 does have better speed capabilities, 10 ms versus 40ns for the 710 under equivalent conditions, but in this application it is not an individual devices speed which is of interest, but rather the overall signal delay differential between the input channels. Higher speed devices such as the LM36O, which has a 20ns maximum switching speed, would be a suitable replacement for the zero crossing detector as well as the logic level translator. This particular intergrated circuit has the added feature of a \ i 'a ' ~ a Channel A ------0 J . 19. .. i ■ ■ i i i i r.,J , . . : i .Channel B ZERO CROSSING DETECTOR OUTPUT Figure 3-1 Channel A Channel B SPECIAL CASE OF T HE ZE RO C R0SSIN G DETECTOR OUTPUT Figure 3-5 27 low variation, with overdrive, in switching speed, 3 ns typic ally* Overdrive is the excess input above the minimum required to cause a transition to take place* Three inputs are provided* One is permanently connected to channel A while one of the remaining two may be used for the input to channel B* This facility is provided to enable a measurement to be made not only between the two signals of in terest, but also with reference to a standard or reference input* 3.3 PHASE ANGLE TO PULSE WIDTH CONVERTER* The object of this circuit block is to obtain a pulse train such that the pulse width is directly proportional to the phase angle between the input signals* Equation 2*3 shows that if both the positive-going and negative-going zero crossings are used, the errors due to harmonic distortion are reduced to those due to odd order cosine terms* Therefore the circuit must be capable of measuring both the positive and negative-going trans itions* C.J* Pauli in his analogue phase meter (see section l*2d) used both crossings* The circuit to be described takes an arithmetic mean of the apparent phase difference as measured between both positive and negative-going zero crossings* Figure 3*^ shows the outputs of the signal and reference channels as two pulse trains A,B of equal frequency but unknown phase re lationship* The true phase difference 0^ is shown between pulse centres. A phasemeter operating only on the positive-going zero crossings would indicate a difference of 0^ and one oper ating on negative-going zero crossings would indicate 0^. Now if 2a find 2b are the pulse widths of the A and B signals res pectively then + a~b -3.1 0R s ^T + b-a -3.2 Adding 3*1 to 3.2 gives 0T = 0F + 0R -3.3 2 -2 8 A — Channel A Channel B ZERO CROSSING DETECTOR OUTPUT WITH CHANNEL B SHIFTED 18C° WITH RESPECT TO FIG. 3-5 Figure 3-6 -28 Therefore this circuit gives the true phase difference regardless of the mark space ratio of each channel after limiting. Figure 3*5 shows the special case where the B pulse occurs within the A pulse. In this case we have 0F« #T ♦ a-b -3.^ 0R« 360 - (*-0T-b) 360 - -3»5 Adding equations 3**t and 3*3 we obtain * 0H * 20t + 360 Therefore 0T * **F + " 180 -3.6 2 This implies that a 180 degree error will occur and, for this reason, a switch to inhibit the automatic averaging is in cluded. Effectively the switch converts the circuit to a single zero crossing circuit. Should the phase angle for single trigger ing be greatly different (eg. 90°) from double triggering, then one channel should be inverted and 180 degrees subtracted from the result. That this is correct can easily be proven by reference to Figure 3*6 which shows the case in question - but with the B channel shifted by l80°. In this case t * + b—a 0,JT * T * 0$ + a-b Therefore 1 ■ K * K 2 But * 0T + 180, 0F « 0F + 180 and 0^ = 0R ♦ 180 Therefore ft + 18C * + 180 °r ^T = ^F + ^R 2 2 ure A- -29 Q) U) o % CD o < o AS-** -29A- 103 i i Q4 + G4 PHASE MEASURING CIRCU1 T TIMING DIAGRAM Fi g u r e 3-8 -29- The decision whether to check the single trigger answer would depend on a knowledge of the waveforms under investigation. If they are close to symmetrical then there is no need to check the single trigger value. However, if there is any doubt about the waveform it would be wise to do the single trigger check. The circuit is shown in Figure 3*7* The operation of the circuit is best illustrated by reference to the timing diagrams Figures 3.8a and 3.8B for two incoming pulse trains. The posit* ive-going edge of signal A may be considered to initiate the logic cycle by clocking the output Ql. to the high state. Gate G1 is used to invert the channel A signal, and Gate G7 the channel B signal. The inversion is necessary as the flip*flops used (7^73's) are negative edge triggered devices. The truth table for the 7^73 device is shown in Table 1. t n ^n+1 J K Q 0 0 0 1 0 TABLE 1 1 0 1 1 1 Qn The choice of which state the inputs were in prior to the positive*going edge of signal A arriving at the flip*flop Ql is purely arbitrary, and for this circuit operation description it will be assumed that the J input has a 1 on it and the K input a zero (Figure 3.8a). The reverse case will be described later. (Figure 3.8B) When Ql goes high, on the above assumption, Q2 will also be high. Accordingly the output of G2 (Y) will go to the high state. These conditions will remain until a positive-going pulse on input B clocks Q2 low. The next positive transition of A causes Ql to go low, and the next positive-going B causes Q2 to go high again. Then the cycle is complete. The flip-flops Ql, Q2 and the gate G2 therefore measure the phase difference between positive-going zero crossings. The flip-flops Q3, Q4 and the gate G4 measure in an analogous way the phase difference between -30- negative-going zero crossings* However in this case there is no arbitrary start* The start is determined by the positive-going zero crossing detector* A feature of this circuit which will be used later (see section 3*3) is the repetition rate of the output pulses at G3 and G3« Reference to the diagram Figure 3*3A shows that a pulse proportional to the phase angle only occurs for every second cycle of the input signal* This feature of the circuit means that the quantising pulses will only amount to half the ex pected amount* For example, if the reading was 360*0 only 1800 pulses would come from the output of the gate circuit in any one measurement period* Figure 3«8B shows the timing diagram for the case when the J input of Q1 is a zero and the K input is a one* Comparison of Figure 3*8a with Figure 3»8B shows that there is no effect on the pulse widths of the output signals due to the two possible start ing states, but there is a 360 degree phase shift between the two possible signals. The arbitrary start therefore has no effect on the accuracy of the phase to pulse-width conversion. The two pulse trains must now be added and digitally divided* The method chosen was to sample the forward zero crossings for half the measurement period and the reverse zero crossings for the other half* The actual equation for this is <*T m_*T 2 2 To effect this time averaging process the 0^ and 0^ pulse trains are gated by G3 and G3 (See Figure 3*7)• G6 sums the two signals to form one - 0^* The state of G3 and G5 is controlled by the flip-flop Q5» thus ensuring only one gate is open at any one time - G3 or G5. Q5 is clocked by a symmetrical pulse train operating at twice the frequency of the measurement period, ie* In the one second measurement period mode it is clocked by a l*0Hz signal, and in the ten second mode by a 0.1Hz signal. The generation of this signal will be discussed later* The technique described above assumes that the frequency of the input signals will remain substantially constant over the full -31 A- 1or10 Sec —o to display circuit G7 £> C G9 from B E GS HZ> G 8 36MHz GATE CIRCUIT Figure 3-9 31- measurement so that both the forward and reverse phase differences will supply their correct portions to the overall result. For measurements at 50Hz, where the N.S.W. Electricity Supply System is concerned, it has been shown (Reference 12) that over a 10 second period the maximum departure from the mean frequency is less than 0.1$ during daylight hours and therefore the above assumption is valid for N.S.W. The effect of a D.C. offset in the input signal is to cause an uneven mark space ratio. The mark space ratio variation is analogous to that caused by harmonic distortion. It is evident therefore that the circuit just described eliminates most of the inherent problems of zero crossing phasemeters, ie. D.C. offset and harmonic errors (except odd order cosine terms, as shown earlier). The effect on the output of noise in the signal input will be reduced because during many parts of the cycle transitions of one signal will have uo effect because the interconnections pro vide for a fixed sequence of events to take place. 3.4 GATE CIRCUIT The function of the gate circuit is to gate the high frequ ency quantising pulses into the readout device for a fixed period of one or ten seconds. The basic circuit is shown in Figure 3*9* The use of frequencies above 10MHz precludes the use of TTL logic. In these circumstances the faster ECL logic must be used. The gates G7 and G8 are not in fact just gates, but rather logic level translators. The inputs are at TTL levels (0 to +5V) and the outputs at ECL levels (-3*2 to OV). The operation of the gate logic circuit is best explained by the following truth table:- 32 A B C D £ F Meas period Phase signal A BA B 36MHz Output H H L H L L H H L H H L HLL H LL H L LH H L L HL H L L LH L H H L L L H L L H L L H L H L There is only a high output when a measurement is being taken and the phase signal is low* This is exactly the output that is required* 36 MHz quantising pulses 3*5 QUANTISING PULSE GENERATOR The quantising pulse generator must be a stable source of pulses for the gate circuit, measurement period control and general housekeeping operations, i*e* reset and store pulses for the display circuits* As far as the measurement of phase is concerned, where the one generator supplies both the timing and the quantising pulses, it is not important to have a certain frequency or stab ility, as any variation in the quantising pulse frequency is com pensated for by an equivalent variation in the measurement period* (See section l*3b)* However, when the unit is used as a frequency meter, the frequency stability becomes very important* It is for this reason that a —33 A— BASIC MECL GATE CIRCUIT Figure 3-10 -33- Crystal oscillator was selected as the source of quantising pulses The actual frequency was determined as follows:- From the desired specification we have Accuracy 0.1° Frequency range kO to lOKHz Phase angle range 0 to 360° To be able to meet the above requirements it must be possible to discriminate intervals of time less than or equal to 0.1 360.0 = 0.1 | 360 x 10 * 28nS Therefore the quantising pulse rate must be such that its period is no greater than 28nS. Therefore Fa 1 a 36 MHz q -----35- 28x10 * This frequency is a convenient frequency for the actual instrument as it is equal to 360 multiplied by ten to the fifth power. This allows for direct division by a power of ten to obtain a suitable rate for direct display of the measured phase angle. The actual frequency chosen was 72MHz as a crystal of this frequency was read ily available and it is an even multiple of 36 MHz. As noted earlier TTL is of no use at frequencies above 10MHz so non-saturated logic was chosen. The particular type is Motorola MECL 11 MC1000 Series. The logic is non-saturating to eliminate transistor storage time as a speed limiting character istic. MECL 11 boasts a 40nS propagation delay for basic gates and a 70MHz clock frequency (max) for flip-flops. The crystal selected was an AT cut quartz plate operating in the fifth overtone mode. The circuit used comes from a Motorola application note (Reference 3)* It is based on the MC1023 OR/NOR logic gate. The gate circuit is shown in Figure 3*10. It is a differential amp lifier with emitter follower stages on either side of the amplif ier. The MECL gate may be considered as an amplifier or an invert ing amplifier, depending on which output is under consideration. -34A- O—©-{ 9--- O EQUIVALENT CIRCUIT OF A QUARTZ CRYSTAL Figure 3-11 72-MHz 5th overtone ■O to divider 9-35pF 9 -35 pF X CRYSTAL OSCILLATOR CIRCUIT Figure 3-12 The feedback network utilizes the quartz crystal in the series resonant oscillation mode* The crystal provides a low impedance path from output to input when operating at or near resonance* Figure 3*11 shows the equivalent circuit of a crystal where L,R, and C represent the analogous mechanical properties of inductance, resistance and capacitance* is the static lead capacitance* It is obvious that the crystal could oscillate in two modes - the series resonant mode of L and Cand the parallel resonant mode of L and Cq. The series mode is used in this application* (See Figure 3*12)* At resonance, L and C effectively cancel each other s leaving R and Cq in the feedback path* In the circuit and form a resonant tank circuit which is adjusted to oscillate at 72MHz* This tank circuit effectively short circuits all frequenc ies except those at or near 72MHz* This ensures that it will always operate at the correct frequency* For correct operation of the gate its input must be at or near the reference voltage of -1*2 volts* This is accomplished by the voltage divider R. and R, and the resistor R_ * C_ is a filter 3 13 capacitor for the reference supply* The capacitor loads the output of the gate in order to increase the rise and fall times* A second gate serves as a buffer and wave shaper* The output of the first gate, which is approximately a sine wave, is fed into the second gate which shapes it into a square wave with rise and fall times at approximately 2nS* was constructed of 13 turns of tinned copper wire wound on an air former of approximately diameter* This was checked by resonance on a Q meter at 72MHz and a of 23pf was found to be appropriate* The oscillator was checked on the HP5243L frequency meter and the frequency was found to be adjustable between 72,000,330 to 72,000,360 Hz using the ad justable capacitor C^. The output frequency changed 100Hz when the crystal was heated by 10°C* ie* By 0.1 in 72,000 or approximately 0.001^. The 72MHz was initially tried as the quantising frequency but due to layout and load the gate circuit previously described in section 3«*+ could not be made to function correctly* When a frequency of 36MHz was applied to the gate circuit no difficulty was found and correct operation ensued* -35A- -5.2V -5.2V 72MHz ■>- 36MHz -5.2V 72MHz DIVIDER Figure 3-13 -35B- N X CnI DIVIDER SIGNALS ,)—» |-» 1->I^ |Y.|Y TIMING |-> l~l I—i \X- -35- The 36MHz signal is obtained by dividing the 72MHz signal by 2* In this application a MC1013 J.K flip-flop was used as shown in Figure 3*13* The truth table for this circuit is shown below J K CD Si 0 0 0 0 0 1 Qn 0 1 1 1 1 0 1 0 1 1 1 n For this case the R and S inputs, and all other J*K inputs are held at the 'O' level* is obtained by connecting one J and one K input together* 0 implies either state will result in the desired output* From the truth table it is clear that the flip-flop output only changes state on positive-going transitions of the input signal and therefore divides the input signal by two* 3.6 TIMING SIGNALS DIVIDER Many signals of different frequencies are needed for house keeping eg* store pulses and reset pulses, and timing* The sig nals are obtained via appropriate logic from frequencies which are sub-multiples of the 36MHz signal. The first stage provides a frequency of 7*2MHz* This frequency was chosen as it allows a change to saturated logic* ie* TTL, which is more economical pack- agewise* To obtain a frequency of 7*2MHz requires a division by five* The circuit which is a synchronous divider is shown in Figure 3*1^ The three J*K* flip-flops are connected with feedback paths to enable five pulses instead of the usual eight pulses to cause a complete counting cycle* The 72MHz signal is used as the clock for the divider and the 36MHz is the input. The output of the last flip-flop feeds back a pulse to the first flip-flop every cycle* The output of the first feeds a pulse to the last flip-flop every cycle. The two feedback paths add a one and a two to the count and so advance the count by 1+2=3 to provide the correct overall divis ion ratio* This is two to the power three minus three ie* five* -3 6A- 'dosed open Gate '20 "t(sec) Reset Store TIMING SIGNALS Figure 3-15 36- The next step is the conversion from unsaturated logic to saturated logic* This is accomplished by an MC1018 device which can perform the logic OR or the logic NOR function* The function which is required is set by suitable interconnections of the bias supply* In this application an OR gate is required and so the internal bias supply is connected to pin 6* The frequency requirements for the control signals have been partly enumerated* Two frequencies are necessary for the gate circuit to enable measurement periods of one second and ten sec onds to be used* Together with the gate signal is the requirement for pulses to reset the display counters to zero at the beginning of each measurement period and to transfer the total count to the display devices at the end of each measurement period* The timing signals are shown in Figure 3*13* The relationship of the store, reset and gate signals is very important* The sequence of events which takes place each cycle is as follows: The operation descrip tion is commenced at the point marked X in the figure 3*13* (a) The display counter is set to all zeros* The instrument is now ready to make a measurement* (b) The gate opens allowing the pulse train from the phase to pulse-width convertor to enter the displaycounter, which total ises the number of quantising pulses for the one or ten second measurement time* (c) The gate then closes, leaving a count proportional to the phase angle in the display counter* (d) The display latch is then operated allowing the count to be transferred to the display driver as well as storing the result until the next latch signal occurs* (e) The next signal is a reset signal which initialises the counter in order that the cycle can repeat itself* No fixed relationship exists between the input signals and the design does have the arbitrary start and stop problem* How ever, as is shown in section 5«3 the effect is negligible* The store pulse must precede the reset pulse to enable the accumulated count to be transferred to the display before the counters are reset to zero. The complete divider is shown in Figure %16 and is con structed primarily of 7^90 and 7^92 integrated circuits which divide by ten and twelve respectively* These integrated cir cuits are each made up of two dividing modules, one divides by two and the other by five or six, depending on the overall div ision ratio* This type of package is very convenient as far as circuit density is concerned, but limits the counter to the asynchronous or ripple carry type* In an asynchronous counter the trigger input of each bistable circuit is derived from the output of the preceding bistable circuit. This results in a ’’ripple-through” of the count pulses, so that the last bistable circuit cannot change its state until all the preceding bistable circuits have changed state* The delay inherent in ripple carry counters is avoided in synchronous counters by supplying trigger pulses to all stages simultaneously* (See figure 3*1^)• The stages which are required to change state at particular points in the sequence have logic control inputs on which the desired conditions are set up by gating elements* In this way all those stages that are required to change state when a particular count pulse arrives will change simultaneously* The main advant age of synchronous logic is the elimination of variability due to the changing propagation delay of the individual bistable elements* Tests of the main timing pulse, ie. the one second gate, have shown that the total variation is negligible. The period ranged from 0.9999915s to 0.9999926s. The 7«2MHz signal is initially divided down in four stages of division by ten to produce a 720Hz frequency* The circuit diagram shows the inter- grated circuits in a symbolic representation. As mentioned earlier two gate^or measurement^periods are in corporated in the instrument. Therefore the reset and store pulse signals must change when the measurement period changes* The easiest way to implement thi6 frequency change is to change the frequency of the input to the gate, store and reset pulse gen erating circuits by a factor of ten. The frequencies required by the control circuit generator are therefore 7«2KHz or 720Hz. To form the gate signal a frequency of 0.5Hz or 0.05Hz is required. However, while the store and reset pulses also operate -3 8 A- Store ±1 o cj CD Q o -38- at these frequencies, they are not as long in time as the gate pulse. In order to obtain the required width pulses it is nec essary to NAND five frequencies: 72Hz, €l*| 0,2Hz, and 0,03Hz, To obtain these frequencies two ?490*s and two 7^92*s are used and connected as shown in Figure 3*18, A light emitting diode is connected via a NAND gate to the gate waveform to indicate when a measurement is in progress. The diode is mounted on the front panel and labelled 'GATE', It should be noted that there is in fact not a single pulse for the store and reset pulses, but rather a group of pulses. The net result is, however, identical to that which would be ob- rained with the more complex circuitry to produce a single pulse, A point to note is the way in which the divide by ten and the divide by twelve circuits are connected. It is possible to connect the divide by two circuit first or last because of the dual module construction. At first sight this may not appear important but if the actual internal connection of the divide by two and divide by six modules is investigated, it is found that the output waveform will not have a 1:1 mark space ratio. The only module which will provide a 1:1 mark space ratio is the divide by two module. For this reason both the 0,03Hz and 0,1Hz waveforms are derived from divide by two sections* 3.7 CONTROL SIGNAL GENERATOR Derived from the timing signals divider is a set of five fre quencies which for the ten second gate period are 72, 6, 0,2, 0,1 and 0,03Hz, These are converted into the two signals as follows:- A. Reset Pulse The reset signal, which initialises the system prior to a measurement sequence, must provide a pulse (group of pulses) at the appropriate time. The circuit (Figure 3»l6) utilises an eight input rtAND gate 7^30 and NAND's the five signals enumerated above. Due to the non-symmetrical 72Hz, 6Hz, and 0.2Hz waveforms the out put is a series of pulses each with a duration equal to the period of a 72Hz signal, B. Store Pulse The store signal is used to transfer data from the decade -39 A i-> *—> *—> ts: x x: 3-17 DIVIDER Figure DISPLAY j—> <—> f—> -X «D > ^ OJ iri -39- counters to the display. This buffer storage permits a flicker free display. This type of display is more pleasant to view than one which flickers each time a measurement cycle is completed. The circuit of the store pulse (Figure 3-16) utilises the same five signals enumerated above except that the 0.1Hz signal is inverted before the NAND operation. The store pulse is a sequence of pulses analogous to the RESET pulses but occuring before the RESET pulse. 3.8 DISPLAY DIVIDER The function of the display divider is to take the output of the gate circuit and produce a suitable signal for the display counter. This enables a direct display in degrees. Reference must now be made to Section 3*3 where the halving of quantising pulse count due to the phase measuring technique used, is discussed. It follows that to obtain a correct reading the number of pulses reaching the display must be doubled. Fortun ately this is simple to implement by reducing the overall division ratio by a factor of two. This causes an effective doubling of the number of pulses. A division ratio of ten to the power four is therefore needed. The circuit is shown in Figure 3.17. The first five integrated circuits are connected in the same configuration as the timing pulse divider described in sections 3*5 and 3*6. The following three stages are 7490 decade dividers. The first two of which are connected as decade dividers, and the third as a divide by Tive stage. 3.9 DISPLAY AND OVER RANGE CIRCUITS. The display circuits form the interface between the measuring circuit and the operator. In applications where no display is nec essary a straight BCD output could be provided. The display uses Hewlett Packard 3082-7300 series solid state numeric indicators. These devices utilise a 4x7 dot array, and this ensures better readability than the more conventional seven segment displays. In this instrument four of the 5082-7302 devices and one of the 5082-7304 devices are used. The 5082-7302 is a 0-9 display and the 5082-7304 a plus minus one display. The 5082-7302 has several advantages over other currently -40A- .X2 BCD hX8 MATRIX LATCH Store ° DECODER Decimal o- MEMORY point L.E.D. DRIVER L.E.D. MATRIX MATRIX BLOCK DIAGRAM OF THE DISPLAY DEVICE Figure 3-18 FF9 o ---- -4 0ET- DISPLAY CIRCUIT Sw2 H- ■ Store Figure 3-1S ^ Q______40- available displays. As shown in Figure 3.18 it has a built-in memory and decoder driver. The decoder has been so programmed that, unless the input signal is for a 0-9 or a minus sign, the display remains blank. (Except for a special test signal code when all the diodes are activated). The 5082-730** does not have the latch or decoder driver feature. The overall display circuit is shown in Figure 3*19« The display circuits can be used either as a readout for phase angle or for frequency. The frequency circuit will be dis cussed in section 3*11* The display can receive its input signal from two sources - one proportional to frequency and one to phase. The source is selected by SW1. When in the phase position the input to G31 is two highs and the output is therefore a low. G29 has one input low, thus ensuring that the output is always high; whereas G28 has one input high enabling the other input to change the output acc ording to the NOT of the varying input signal. G30 performs a NAND on the outputs of G28 and G29« As one of their outputs is rermanently high and the other varying, the output of G30 will again be the NOT of the varying input. The signal from G30 is fed to a string of decade counters DC12- DC15. Each measurement cycle these counters totalise the number of pulses received and convert this number into the appropriate BCD signal. The 8-4-2-1 code is used in this instrument. After each measurement cycle the counters are reset to zero. The BCD code is fed directly to the display X^-X^ which are operated in the latching mode. The display will follow changes in the logic inputs as long as the store input is held low. In this mode the device is a real time display. However, in order to elim inate a display of the counting process which would just appear as a blur of numbers the latch is only allowed to go low after a count ing cycle has finished. This means that the total count is trans ferred to the display and stored until the next count has taken place. Thus in each measurement cycle the display is updated. Should no change take place there would be none of the annoying flickering so typical of the older digital displays. The decimal point position is controlled by SW2 using resistors whose function it is to let the decimal point input remain high unless - 41A- SIGN SENSING CIRCUIT Figure 3-20 (b) (c) (d) (e) SIGN SENSING CIRCUIT WAVEFORMS Figure 3-21 41, selected by the switch* In this case the input is grounded caus ing the diode to light. The output from the last decade counter DC15 is fed to FF9 which is a flip-flop connected in the toggle mode. When its Q output goes high an overflow from DC15 has occurred ie. a digit 2 representing 10 degrees. The output signal from FF9 is fed to two gates G21~^i£2 which act as latches together with G^ and G^. only allow signals to pass when one of the inputs is high. The gate G27 is necessary as the display X -X_ latches have the 2 y opposite logic convention to G21, G^# Gi9~G20 form a Bistable flip-flop and store the information from G21~G20 when the latch signal is off. The output of ®29**G20 a transistor driver TR^ which activates the one on display X^. The signs + and - have similar driving and latch circuits to the one circuit, but the extra gates G^-G^g are also used. Their function is to remove the + and - signs when the instrument is in the frequency mode, in which case they would have no meaning. G^-G^g are the inhibiting gates, while G^-G^g invert the signal so that, as far as the output of G23*G24 and the *nPu* °f TR? and TR^ are concerned, no inversion has taken place. Gates G^-G^g are controlled by SW1 as are the signal selection circuits. 3.10 PHASE SIGN CIRCUIT. The sign circuit determines if channel A or the reference channel is leading or lagging channel B. In any phase measurement it is possible to describe one signal with reference to the other as a straight angle, ie. 0-360 degrees. However, a more common practice is to speak in terms of only 0-180 degrees. The second section 181-360 degrees is then characterised by the leading or lagging description, followed by 0-180 degrees. In other words it can be said that the phase angle is ♦ or - 180 degrees, where + represents the A channel leading B, and - represents the A channel lagging B. The circuits to be described have not to date been constructed. It is intended that they will be included in the future. The circuit is fairly simple. (See Figure 3.20.) (For a more detailed circuit, see Figure 3*19). -42 A~ sq Phase m easunn g p[3J circuit flip-flop CHANNEL INVERSION CIRCUIT Figu re 3-2 2 42 The A and B channel signals are obtained after the input squaring circuits. The A signal is inverted no as to provide an A and an inverted A signal (A). The truth table for the flip* flop used (7473) is shown below. t n tn+l J K _Q__ 0 0 0 1 0 1 0 1 1 1 As the J and K inputs of the flip-flop are connected to A and A, the relevant part of the truth table is lines two and three. The timing diagram is shown in figure 5*21. The operation of the circuit is as follows!- If A leads B, as in case (b), A will always be high before B. therefore J will be high, K low and ^(d) will then change to a high state on the first negative transition of B. From then on, until a change in the sign of the power factor, it will remain high. The alternative case is shown in (c) where A lags B. In this case the output (e) remains low. The output of the flip-flop is connected to logic driving the ♦ and * light emitting diode display. It is also connected to an Inversion circuit in the B channel input. The inverter causes an automatic 180 degree shift of the B signal at the input to the phase measuring flip-flops. The inverting circuit is shown in Figure 3.22. The sign flip-flop outputs are always <% and Therefore, only one gate of 0„ and is open at any one time. The output is either B or B . sq eq The inclusion of this circuit block will produce unequal delay times in the two channels. To partially compensate, a similar single inverting gate is added to the other channel. This will mean that for the case of overall inversion the two channels will be balanced, as there will be only one gate in each channel. How ever, in the case where there is two gates in one channel and only -43- one in the other an obvious imbalance is evident. To minimise the error a SN74HOO high speed quad input gate could be used. The standard TTL gate 7^00 has a maximum propagation delay of 22nS, typically llnS; whereas the 7^H00 high speed TTL gate has a max imum lOnS delay, typically 6nS, A 22nS delay at 1000Hz is equal to 6 x 10 x 360 degree 1 x 10-3 1 * 0,01 degree This amount of imbalance is quite acceptable, so a 7^00 gate is suitable in this application, 3.11 FREQUENCY MEASURING CIRCUITS The circuits described so far are readily connected to form a dual range frequency meter. In the instrument only three extra integrated circuit packages were necessary. The main requirement is to be able to measure the power fre quency range in direct terms rather than as a period measurement. This dictates a range of 0 to 2000,0 Hz, To obtain the tenth hertz uigit requires a ten second gate time. The one second gate time therefore gives a frequency range of 0 to 20KHz. The main section of the frequency circuits is shown in Fig ure 3.19. This shows the sign blanking and frequency mode select ion switching. The input signal is taken from channel A or the reference channel, depending on the position of SW3, after the zero crossing detector. The A signal is gated by the 0,05 or sq 0,5Hz waveform, depending on the position of the timebase switch. The operation of the circuit is reasonably simple and operates as follows: The gate opens for ten seconds or one second, and allows X pulses to reach the display counter. These pulses are totalised and transferred to the display at the end of the measurement period. Just prior to the next measurement period the display counters are reset to zero ready for the next cycle, 3.12 POWER SUPPLY There are four voltages used in this instrument: Plus five volts for the TTL integrated circuits and the display devices, minus 5,2 volts for the ECL integrated circuits and plus and minus fif teen volts for the operational amplifiers. -44 A- O +-5V O gnd + 5 VOLT SUPPLY Figure 3-23 -44- A. Plus five volt regulator* The nominal supply voltage for TTL 74 aeries integrated cir cuits is five volts with a tolerance of plus and minus 0.25 volt. The supply must have its maximum ripple less than or equal to 3%t and its regulation less than or equal to 5%. The National Semiconductor LM309K integrated circuit voltage regulator was chosen (reference 13) as it provided all the regul ation circuits in one package together with other desirable feat ures such as: Thermal limiting, short circuit proof and, as well, no external components are necessary to set the output voltage. With adequate heatsinking the device can deliver in excess on one ampere and maintain a line regulation of 0.005$/volt. The overall power supply circuit is shown in figure 3.23. The plus five power supply has an individual transformer due to space limitations and available transformer cores. The transformer provides 10 volts A.C. which is rectified by a three ampere sili con bridge assembly and smoothed by a 2500jaF oapacitor to provide an eleven volt on load, D.C. voltage to the LM309K regulator. The output of the regulator has connected across it a lOpF cap acitor to improve the transient response. This is important where logic circuits are being supplied. The power supply was tested for load regulation and the following results were obtained: Load current Output volts No load 5.04 1mA 5.04 10mA 5.03 100mA 5.03 430mA 5.00 This level of performance meets the requirements laid down earlier. The pilot light, which is a light emitting diode, is connected across the output of the plus five volt supply. This serves the dual functions of indicating the main switch status and also the status of the plus five volt supply. The plus five volt supply is decoupled every five or ten TTL ~45A~ > CnI in CD ™ > CL CL 3 3-24 in i— __i 0 > Figure CNl lo 1 -45- packages. The decoupling is necessary as the TTL circuits util ise totem pole output stages which, when they switch, give rise to a heavy current pulse from the non-conducting transistor switch ing on before the conducting transistor switches off. This pulse has a duration of the order of a nanosecond. To eliminate its effects a capacitor of O.Ol^F is needed for every five or ten packages. In practice the exact placement of these decoupling capacit ors was found to be reasonably critical to proper circuit operation. B. Minus 5»2 Volt Supply The nominal supply voltage for ECL 1000 series is minus five point two volts. At the time of designing the circuit no single package reg ulators were available for minus five point two volts. Therefore it was decided to design a suitable regulator. The criteria for the supply were: a) The incorporation of current limiting b) Minimal temperature coefficient c) Fast transient response A series control circuit incorporating a feed back regulator circuit was chosen as the most suitable for this application. (References 14 and 15) • The reference source chosen was 4.7 voltszener diode. Instead of feeding the zener from the unreg ulated supply, it is incorporated in the feedback loop of the reg ulator. This approach significantly reduces the output ripple and removes the necessity for a preregulator to supply the zener. High frequency noise generated by the zener is filtered by the 10/^F capacitor (Figure 3*24) and the 2K2 resistor. The lC^F is a tantalum capacitor, as electrolytics do not have a low imp edance to high frequencies. The 100/*. F capacitor helps improve the transient response of the regulator at the higher frequencies where the loop gain drops down. The resistor in the emitter cir cuit of the series pass transistor and the BC148 perform foldback current limiting of the supply, when the voltage across R 1 rises to such a level that TR 2 turns on. Then the base-emitter volt age of TR 1 is reduced, and so is the output volts and current. The high supply voltage rejection ratio of the 301A ( 3> 70dB) 2N 2905 -46 A- Fig ure 46- allows it to be directly connected to the unregulated supply line. This power supply was tested for regulation and the following results obtained: Load current Load volts 50 A 5.20 500 A 5.20 5mA 5.20 50m A 5.20 100m A 5.20 200m A 5.20 A LED is incorporated across the output to aid in fault finding the unit. ie. It indicates the status of the minus five point two volt supply. C. Plus and minus fifteen volt supply The supply used here is a monolithic integrated circuit MC1468 which is a dual tracking plus and minua fifteen volt reg ulator capable of 100mA. The line and load regulation is 0.06#, which is more than sufficient for this application. Referring to the circuit diagram Figure 3*25t the unregulated D.C. is der ived from a full wave bridge rectifier and centre tapped trans former. This combination produces the unregulated plus and minus 25 volt supply for the integrated circuit. Two external pass transistors are provided to give a capab ility of 500mA. The two 3*9ohm resistors provide for a maximum current of 150mA before limiting. The two 10^ F capacitors pro vide an improved transient response. k. INSTRUMENT OPERATION The operation of the instrument is very simple. Two signals are derived which correspond to the two signals to be measured. The amplitudes of these two signals are required to be between one volt and 300 volts. Care must be taken in the connection of the inputs, as one wire of each input is at ground potential. This re quires that an isolating transformer of low phase angle be used where the signals being measured are above ground potential. The resulting phase angle will then be directly indicated in degrees. In cases where the exact waveform is not known it is necessary to check that the single trigger mode provides an answer reason ably close to that given by the double trigger mode. (See Section 3*3)* The most accurate measurements are taken in the double trigger mode. However, a limitation of this mode of operation is that the phase angles must be sufficiently remote from either 0 or xr . This condition arises from the propagation delays of the flip-flops in the phase measurement circuit. When the phase angle approximates 0 orir, and when the double trigger mode is used, then the pulses at the A and B clock inputs of the flip-flops approach coincidence. This makes the outputs spurious. Under these con ditions single triggering must be used, but it must be remembered that the single trigger does not provide any correction for har monic and D.C. offset errors. 48- A phase invert or a 180 degree shift function is included for applications where the angle is at or near zero or xr and it is still desirable to use double triggering* This feature is also useful in eliminating the effects of phase reversals in instrument transformers etc* - 4 9 A- BLOCK DIAGRAM OF TEST SETUP Figure 5-1 EQUIVALENT CIRCUIT OF. TEST SETUP Figure 5-2 49- 5. PERFORMANCE OF THE PHASE ANGLE METER 5.1 MEASUREMENT METHOD The test setup is shown in figure 5*1. The frequency syn thesizer produces a stable signal of the desired frequency* This signal is then amplified and fed via an isolating transformer to a precision centre tapped inductor* A series resistor and capacitor are connected across the end termination of the centre tapped inductor* The two inputs of the phase meter under test and a Hewlett Packard time interval counter are connected from the earthed centre tap to the common point of the resistor and capaci tor and also to one end of the centre tapped inductor* The centre tapped inductor* resistor and the capacitor may be redrawn as in figure 5*2* The performance of this circuit is best illustrated by reference to the vector diagram shown in Figure 5.3. The phase angle 0 of B with reference to A is calculated as follows: Cos (2f * X a R R 2WL Therefore X = R2/2WL Similarly Sin 0 = Y * 1/WC R 2WL Therefore Y = R.. 2LCW2 Thus Tan (180 - ©) = R/21CW2 (2W2L^-R2)2WL R/WL 2 2 2 2W jL - R and Tan 0 * R/WL 2 2 2 R - 2VTIT from Pythagoras’s theorem* WL2 « R2 + 1/W2L2 Therefore 0 * Tan “1 R/WC l/W^C*- - R -50B~ o >: ; 5 o 2 >0 0 0 3 'J r' / 3 0 o 10 0 I : o ' ’ 0 o 2 p (J 0 0 /r'\ i 2 (J G 0 2 9 i ~ -.1 • ^ .j - * w — • • - 2 ;; - ?. 'to 0 G 0 i ?» p ;■ 3 0 10 0 0 i 0 4 4 1 p p /- 3 o j 0 0 0 5 p o /• 3 0 pi 'j 0 0 7 2 o V' V ■ o 0 o 0 7 7 o 2 3 J 2. ij 0 G 3 3 x 3 •J 2 ’1 to 0 0 9 3 3 O 7 ;; 3 o 2 T ~) 0 0 0 o > r 3 0 ■?. 0 0 c o G or k. ' 3 0 G 1 ;4 It -p 2 /-' 3 0 3 :5-.; r, 4 i c, 2 3 0 0 0 0 3 A *1° L 3 0 2 v> 0 o 0 5 3 .r 2 L 3 0 2 Jo o 0 5 ;; 2 t- 3 o ■- |o o 0 0 5 r 2 •• 3 0 ; j o. 9 2 9 7 4 2 /- 3 o 0 0 0 0 to r; 2 ■' 3 o 2 : ' 0 2 Q 1 Q o 2 3 i J0 o 9 9 7 4 ?. ' 3 0 2 ! 0 0 0 0 < p .. . 3 o 2 f o 0 0 ,0 3 3 o — .' ; J 2 1 0 0 0 3 3 :: 3 0 5 0 0 3 3 p o 2 j 4> o 0 0 3 3 p 3 < i 0 0 i 3 2 3 0 2 • ;j 0 0 0 i O 1 2 ; 3 o 2 f 0 0 0 0 / 2 v 3 o V t 0 0 0 9 3 ,p ; 2 U 3 V• - • 0 0 0 .7 / 2 3 0 J .1 i 0 0 5 3 ■p ; 4 » s O’ •j 0 0 5 p O 3 >j 2 ; j 0 ■) 5 ( p 7 3 0 '• i 0 0 0 o .p - ■- 2 f) 9 •? .p •• 3 0 s b 0 0 0 3 7 p. 2 3 o 0 'J 0 3 * ■’> 3 . 3 G 0 0 o ? 1 ; 4 f : 3 G Q 0 '■ 1 2 3 0 2 ] 0 0 ; 0 •3 fl 2 ;/ 3 J V I {) 26- 4—74 .J; 2 3 .) i ! 9 ./ 3 p 3 2 r-> 2 §0 ■0 7 s ■£f 4 DIGITAL RECORD OF SYNTHESISER PERIOD Figure 5-4 It is interesting to calculate the magnitude of the output voltage E OB. Eqb = (R/2W2LC)2 ♦ (WL - R2/2WL)2 = ( R2 ) + (2V2L2 - R2)2 (4l2c2w2) 4w2l2 Now (2WL)2 * R2 + 1/W2C2 Therefore E0B2 » R2/W2C2+ (R2-1/W2C2)2 ♦ R1* - R2(R2+1/W2C2) R2 ♦ 1A2C2 » R^ + 2R2/W2C2 + l/W^C** R2 ♦ 1/W2C2 « R2 ♦ 1/W2C2 a W2L2 Therefore, regardless of the value of R and C, the magnitude of Eq3 is equal to the magnitude of EQA (Obviously the source im- E * pedenoe of in will also have a bearing, but for all intents the amplitude of OB does not vary as the phase angle is varied). The object of the test was to set up a pair of stable phase shifted signals and measure the zero crossing period using a Hew lett Packard 52431* counter with a 5262A plug in interval timer unit. As shown in Figure 5*1* the power amplifier was fed from a 400Hz power source to minimise any 50Hz modulation of the measurement, signal. The specifications of the 5262A and CS201 are given in the Appendix. 5.2! SOURCES OF ERROR Sources of error in the measurement were as follows: (1) Instability in the period of Adret CS201 Frequency Synthesizer. The period of the output waveform of the synthesizer was measured using the HP5342L. A section of the records for the Eq^ and E^g voltages is shown in Figure 5*4. From this record it is evident that the period does not deviate by more than -1.5mS from the nominal 20.000mS. i.e. The maximum -51 A- r\ 0 0 0 0 ■o 1 0 9 0 0 0 r-r f -•» 0 0 0 i 9 7 0 O ! 0 A s 0 o 0 1 3 /T 0 AS 0 0 0 0 9 7 0 9 3 W 0 pc. 0 o c» p o I 0 •J 3 0 0 9 o. 7 3 c s 0 9 0 0 • 0 P 3 0 0 i 3 • o p p* p 0 A 3 0 0 1 9 3 0 p 0 0 0 ."5 0 0 ! 9 r\ /? ! 9 9 0 ;.3 0 0 9 9 p 3 0 0 o 1 3 9 0 p p 3 0 ;• s 0 0 1 9 8 r\ p 4‘ 0 s 0 0 1 3 9 o 0 o i 0 ;:3 0 1 3 3 0 o 9 3 0 .v c 0 0 1 3 0 Q r\ 0 3 0 p 3 0 1 9 o A 3 0 o 0 1 9 9 7 0 r\ Q o /- 3 0 0 0 0 0 43 ■•'1 0 A 3 0 O 0 1 0 9 /> o 4 5 5 0 A' 3 0 0 0 o 0 0 A 3 0 o 0 1 3 4 ‘0 A 3 0 0 ■0 I 7 o 5 0 pz o o o 0 0 kJ 0 0 O 3 pz o 0 ,0 1 9 3 3 f> A 3 0 o 0 0 V, 0 0 p 0 A 3 0 0 i 9 3 7 Q 0 •• 3 0 0 0 0 •0 0 0 4 Q 0 3 o 0 I 3 7 0 07 4 0 A3 0 Q 0 ! 5 4 0 A 3 0 0 0 1 9 9 8 5 0 A 3 0 0 0 3 5 0 pz 0 c 0 0 0 0 0 6 p 0 P 3 0 0 ;o 1 9 9 8 0 A 5 0 0 ■ 0 0 0 0 0 o p 0 A 3 0 0 );o I 3 0 AS o 0 •:.0 0 0 0 0 0 r> *7 0 /- 3 0 0 Jo ! 9 7 O i l 0 AS 0 ■ 0 |o •0 0 0 0 Q A 3 o 0 to I 9 3 8 0 A 3 0 0 to 1 0 3 5 4 0 3 0 0 0 O ■ S 8 0 A 3 0 0 1:0 i 9 7 9 G 0 A3 0 0 vO 0 0 0 p L' 3 0 (.0 1 3 9 O 5 r\ 0 0 0 0 A 3 o i:0 0 i 0 A3 0 0 |o 1 9 9 8 /*\ .• > 0 A3 0 0 * o 0 8 A 3 0 0 -0 i O' 3 i:. \ 4 0 A3 0 0 0 5 5 5 i y Q 9 9 9 0 A 3 0 I /!. 3 A 3 0 c 5 0 0 0 o A 3 0 :C 26--4-74 Q «.-A o • 1 7 0 A 3 V vT .9 9 0 ••'Jq r\ 0 0 0 0 0 A 3 DIGITAL RECORD OF THE TIME INTERVAL U N IT'S OUTPUT FOR A FIXED INPUT SIGNAL Figure 5- S'a — 51B — ANALOGUE RECORD OF THE TIME INTERVAL UNITS OUTPUT FOR A F\XED INPUT SIGNAL Figure 5- 5 b -51- deviation is -75x10 S>» This deviation is an order of magnitude greater than the desired measurement accuracy, so it can be deleted as a source of error* (2) Errors due to the HP5243L with 5262A plug in* The 5262A plug in unit is basically a gate, the opening of which is controlled by the zero transition of one signal, and the closing of which is controlled by the zero transition of the other signal* These two signals are called the start and stop signals. As has already been discussed, there is always an error associated with the deadband of a zero cross ing detector* To reduce this error to a minimum the atten uator of the 5262A was set to a minimum in order to ensure a maximum rate of change of the input signal at the zero cross ing and thus a minimum uncertainty* The input signal was a sine wave of 6 volts peak to peak amplitude* To obtain an uncertainty of 0.1° an input swing of 3 Sin 0.1 « 0.00525 volts ie. 5.25 mV must be capable of causing the input to change state* The performance of the time interval unit was tested by feeding a signal of fixed phase angle to the unit and taking a digital and an analogue recording of the output* The phase can be considered constant as the elements which could cause a variation were the decade resistance and capacitance boxes used to adjust the phase and these may be considered constant* Records Figure 5«5a and 5*5b show a variation of 2 0/js maximum* This represents an uncertainty of 0*1%, which is ob viously far too great if an uncertainty of 0*01 degree is desired* However, the record also reveals that this un certainty or jitter is random and it can readily be asserted that an average over eg* 100 periods, will reduce the period uncertainty by at least an order of magnitude, ie. 2)js or better* This being the case, it is possible to utilise the HP time interval unit for absolute time measurement to an accuracy of 0.01$. To set up the time interval unit it is necessary to adjust the 52 A RIKENDENSHI K. K. CHAR t OUTPUT OF THE 5243L SHOWING THE VARIATION OF THE- MEASURED PERIOD Figure 5-6 -52 D.C* voltage at which the internal voltage comparator works in order to obtain correct zero crossing information* This is accomplished by setting the D.C* level such that when the attenuator is changed from one setting to the next no var iation in indication occurs* Due to the jitter mentioned abovet and the lack of resolution on the D*C* offset control, it was found impossible to obtain a variation of less than approximately 5ps between settings* This would lead to an error of 0*025# in time interval* The errors due to the setting up procedure last detailed are the most serious as they represent 0.1 degree, which is the desired resolution. To enable a higher resolution to be obtained it is necessary to first reduce the jitter and then increase the resolution of the D.C. offset control. The jitter may be reduced by adding an averaging module to the output of the time interval unit. This means that 100 periods would be totalised. This facility is already incor porated in the unit described in this thesis. The 5243L should be able to be modified to provide this process as it already has a multi-period averaging circuit built-in which is used on straight period measurements* All that would be necessary is a connection from the time interval plug-in unit’s out put to the period measuring input* Such a modification would allow 1, 10, 100, 1000 period averaging. 5.3 EFFECT of variation of ambient temperature With the instrument connected as shown in Figure 5*1• it was placed in an air bath and tested at 5°C and 37°C# At each temperature the phase single was varied in 45° steps and both the H.P. time interval unit’s period and the phase angle indicated by the unit under test were noted. A series of thirty or more measure ments were made at each point using the time interval meter* The standard deviations were all better than 0*005# of full scale* Ten readings were taken on the digital phase meter at the same time* An analogue recording was taken of the time interval and as can be seen from Figure 5*6 the phase angle varied randomly, although in some records (Figure 5*7) it appeared to have a low 53 A RIKENDENSHI K.K. CHAR LOW FREQUENCY MODULATION OF 5243L OUTPUT Figu re 5-7 53- frequency modulation. The absolute accuracy was not under test, only the repeatability of reading with temperature changes. The results for the three temperatures are shown in Table 5.1. 5° 20° 37° HP 1 sec 10 sec HP 1 sec 10 sec HP 1 sec 10 sec 359.73 000.0 00.02 359.78 000.1 000.0 000.1 000.2 000.23 *>5.33 45.6 45.66 45.28 45.6 45.55 45.14 45.5 45.74 90.79 90.8 90.80 80.54 90.6 90.61 90.48 90.5 90.97 135.51 135.5 135.53 135.30 135.3 135.44 135.06 135.5 135.7 177.53 177.5 177.56 177.27 177.4 177.5 177.03 178.05 236.27 236.1 236.17 836.46 236.4 236.36 236.05 237.66 236.98 269.90 269.9 269.85 270.19 270.0 270.08 269.51 270.6 270.70 316.20 315.8 315.87 316.35 316.0 315.98 315.68 315.3 315.50 ♦ This reading omitted. TABL£_ £. 1. These figures were compared by taking the period as read on the time interval meter and converting this to the associated phase angle. This calculation is purely a proportional calculation. The period is known. Therefore the phase angleis equal to the measured interval divided by the known period all multiplied by 360 degrees. Then the 20°C measurement was taken as a basis and the 5°0 and 37°C readings were corrected; ie. the experimental readings were corrected by the percentage difference between the computed 20°C and the 5° or 37° C readings in order to have a common angle for comparison. This process should not have introduced any further errors as the time interval unit was not readjusted during the measurements. O The ’corrected1 figures are shown in Table 5*2. The 37 C figures show the errors that started to occur as the temperature was in creased above 40°C. At 40°C the ECL circuits ceased to function and the instrument ceased to indicate due to power supply current limiting. The 5°C and 20°C figures show the correspondence that existed over that range and also up to 35°C. The 5°C to 20°C figures show a maximum of 0.1° phase difference. 54- HP 5°c 20°C 3 7°C 359.78 000.1 600.0 600.0 000.0 600.0 600.0 45.28 45.5 45.60 45.6 45.55 45.6 45.88 90.54 90.5 90.35 90.6 90.61 90.5 91.03 35.30 135.3 135.32 135.3 135.44 135.7 135.94 177.27 177.2 177.3 177.4 177.5 m 178.29 236.46 236.3 236.36 256.4 236.36 238.1 237.39 270.19 270.2 270.14 270.0 270.08 271.3 271.38 316.75 316.9 316.02 316.0 315.98 315.9 316.17 TABLiS 5.2. Errors due to the temperature are a result of the input offset voltage temperature coefficient of the input operational amplifiers. For the operational amplifier used, LM301A, the temperature co efficient is 6-30juV/°C. For a 10 degree centigrade change the max imum change is 300pV. Therefore the Zero crossing variation in a two-volt peak to peak signal is Sin *’’*'0.0003 degrees which is equal to 0.02 degrees. 5.4 PKKFORMi+NCE AS A PHASE ANGLE METER The instrument was again set up as in Figure 3*1 at the labor atory temperature and a set of readings was taken at approximately 22.5° intervals from 0° to l80°. This was repeated for both the one second and ten second measurement periods. The results are shown in Table 5.3. The figures are again the average of thirty measurements. -5 5 A — VARIATION OF ERROR WITH PHASE ANGLE Figure 5-8 55- Kean time Calculated One second Ten second Btd. dev Error in Interval phase shift gat© gate iation of Degrees in degrees digital phase mtr. 9948 179.06 179.2 179.24 .007 + .13 rvi 0 1 8752 157. 54 157.4 157.56 .009 * 7511 135.19 135.0 135.01 .009 - *18 6271 112.87 112.5 112.56 .006 - .31 5023 90.41 90.0 90.02 .009 - *39 3758 67.6* 67.5 67.48 .006 - .16 2500 45.00 45.0 45.01 .007 .00 o © 1250 25*50 22.5 25.50 .009 . TABLE 5.3. Excellent agreement was obtained between the one oeoond and ten second sample periods - so such so that it is obvious that only the one second period Is necessary for 50H* measurement* No measurements have been taken for frequencies other than 50H&, but it is reasonableto assume that thin result will hold for frequsncies above 50Ha, but not neeesssrily for those below* This shorter time for a given accuracy wae not predicted by the theory given in section 2, but can be intuitively arrived at by considering that the chances of the extreme case occurring are relatively small and on ths average the error will be half the maximum* The one seoond gate time is obviously far better from the operator's point of view* The errors can be seen from Table 5*3 to vary from 0 to -0.39 of a degree* The standard deviation reveals that the instrument is repeat- able* However, the accuracy is not as good as sxpected* A maximum error of plus or minus 0*2 of a degree had been aimed for* The error is obviously repeatable which suggests a systematic error in either the digital phase meter or, more likely, in the calibration equipment* 5.5 PERFORMANCE AS A FREQUENCY MISTER The frequency meter portion of the circuit was checked against the Adret CS201 and HF5243L, the performance of which has already been described in Section 5.2, and the following figures obtained: Adret CS201 HP Counter Indicated frequency 10 second gate Q-20KHz 1.0 1.0 1.0 5.0 5.0 5.0 10.0 10.0 10.0 50.0 50.0 50.0 100.0 100.0 100.0 1,000.0 1,000.0 1,000.0 1,999.9 1,999.9 1,999.8 1 second gate 0-2KHz 1 1 1 10 10 10 100 100 100 1,000 1,000 1,000 10,000 10,000 9,999 19,000 19,000 13,998 The error at full scale is 2 in 20,000 or 0.01$* If it is taken into account that the specification must obviously be *1 count in the last digit, the accuracy is 0.005^. This accuracy is more than sufficient for the purpose for which it was intended. However, if it was needed, the instrument could easily be upgraded. All that is required is for the frequency of the crystal to be altered slightly to obtain the correct reading. -57A- C Control volt age l.C. LM 3900 Output VOLTAGE CON 1 ROL LED OSCILLATOR Figure 6 -1 57 6. EVALUATION OF THE INSTRUMENT DESIGN 6.i DESIGN PHILOSOPHY FOR FURTHER WORK The phase meter has one area in which further work should be done* This is with the problem of the arbitrary start and stop* In section 1* the work of Smirnov et al (Reference lU was described* To recapitulate, Smirnov et al postulated the reduction in the weight of measurements taken at the beginning and end of a measure ment period* This is accomplished by variation of the frequency of the quantising pulse generator* In the instrument just des cribed the crystal oscillator would be replaced by a voltage con* trolled oscillator operating at around 1MHz. The circuit shown in Figure 6.1 would be a good starting point as it provides a square wave output* The operation of the circuit is as follows: Cne of the amplifiers is used to integrate the D.C* input control voltage and the other is connected as a Schmitt trigger which mon itors the output of the integrator. The trigger circuit controls the clump transistor When is conducting, the input current I^, is shorted to ground. During this one half cycle the input current, I^ causes the output voltage of the generator to ramp down* At the minimum point of the triangle waveform the Schmitt circuit changes state and transistor Q_ goes OFF. The current 1^ is exactly twice the value of I1 (R^ - R-j/2) such that a charge current is drawn through the capacitor C, to provide the increasing portion of the triangular waveform. (The charge current is equal to the magnitude of the discharge current). The output frequency for a given D.C. input control voltage depends on the trip voltages of the Schmitt circuit (V^ and V^) and the components R^ and R^. -58- The output frequency is given by F * 1 x IL 6.1 T Therefore once V frequency is a linear function of 1^ (sb desired for a voltage controlled oscillator)* Another area in which work could be done is in the elimination of noise from the input signal. In removing the noise it is important that the fundamental signal is not altered in any way. If any phase shift occurs it must be balanced in the two input channels. The ideal noise elimination circuit would have a square wave output and a sine wave input. Three systems are generally used: (1) Active filters. The active filter is perhaps the oldest method for noise re moval. However, it also has the most disadvantages. The principal disadvantage is that readjustment of the pass band is necessary each time the signal frequency is changed. Some very attractive designs are now available and a good selection can be found in Reference 16, section 6. (2) Auto correlation techniques. Auto correlation techniques take the input signal, multiply it by the same signal displaced units in time, and average the product over all time. where T^ is the period of x(t). Although averages are usually numbers, rather than functions, R(?) is a function whose independent variable is displacementZ • The nett effect of this mathematical manipulation is to arrive at a signal undistorted by random noise. Harmonics however, will still be present, as they are nonrandom. At present the implementation of autocorrelation is extremely complex, but with the advances in digital integrated circuit tech nology it will probably not be long before suitable circuits are -59A- Sign al input D.C. control voltage BLOCK DIAGRAM OF A PHASE LOCKED LOOP Figur e 6-2 Signal in Signal out CIRCUIT DIAGRAM OF A PHASE LOCKED LOOP Figure 6-3 59 available with reasonable cost and size. (3) Phase locked loops. (PL^) This technique would appear to be the most viable at the present time due to relatively low circuit complexity. This circuit also has the advantage of providing an output signal which is composed solely of the fundamental input signal fre quency. The operation of a phase locked loop is relatively simple. Figure 6.2 shows a block diagram of the circuit. The input signal is compared with the signal produced by a voltage controlled oscillator (VCO), and if there is any differ ence between the phase of the two signals a D.C. voltage signal is generated which slightly alters the frequency of the VCC. In this way the VCO is forced to run at the fundamental frequency of the input signal. The circuit of a suggested phase locked loop is shown in Figure 6.3* This circuit incorporates the VCO shown in Figure 6.1. A point to note is that the output is a square wave which is ideally suited as an input to the phase to time converter. The phase looked loop has a reasonable range in which it will look onto the input signal, but it is by no means a broadband de vice. 6.2 RECOMMENDED DESIGN CHANGES. When examining an instrument, such as the phasemeter just des cribed, for production suitability, it is necessary to use as many state of the art devices as possible to minimize obsolescence. One area in which a change would be made is in the type of integ rated circuit used for the high speed logic. For the maximum frequency, which is the quantising frequency, the ?^H00 series TTL integrated circuits are more than adequate. The 7^H73 flip-flop is suitable for frequencies of 30MHz typically. As well as re ducing the number of power supply voltages by one, the package count can also be significantly reduced. The change to 7^H00 series logic should reduce the overall power consumption but increase the drain on the plus five supply. For -60 A- 600 0 300 O VOLTS Channel A CURRENT Channel B COM o SUGGESTED INPUT CIRCUIT Figure 6-4 -60- this reason an on card plus five volt supply would be used. There would be three or four on card regulators required, replac ing the single unit used at present. The two transformers would also be replaced by a single unit of suitable capacity. A larger display would be of advantage, but preferably one with a plus five volt supply rail such as the 0.6 inch high seven segment light emitting diode arrays currently available. The phasemeter during testing had a tendency to give a random reading every now and then. This was traced to spikes on the mains power supply. In order to remove this annoying feature, the incorporation of a mains line filter would be advisable. 6.3 IMPROVED INPUT FACILITIES. The deficiencies of the present input system are the high min imum voltage - approximately 200mV - and the non isolated inputs. In the area where this instrument will be used the voltage will be a power voltage ie. 63-3* 110, 240 or 415 volts and the current 1A or *>A. However, the instrument in its present form can only use two low voltage signals, each of which has one side referred to earth. It is obvious that no transformers can be used in the input circuits as they introduce waveform and phase errors. The obvious choice is therefore non-inductive resistance dividers and non-in ductive current shunts connected to high common made rejection ratio instrumentation amplifiers. The circuit of a suitable arrangement is shown in Figure 6.4. 61 7. CONCLUDING REMARKS To evaluate the performance of an absolute measuring tech- nique it is usually desirable to compare the apparent values of the quantities that the instrument is capable of measuring against the "true" values obtained from a suitable "standard"* In this usage the meaning of a "true" value is obtained from a well-estab lished standard for which the resolution is far superior to that of the prototype, in that errors generated by the standard are essentially insignificant compared with those from the prototype* The exact "true" values of a quantity are never known except for some of the more basic standards for which the values are arbit rarily selected* In this particular comparison, in which the digital phase meter was compared with a commercial time interval measuring unit, there is a distinct possibility of an unanticipated systematic error due to the similarity of the two measuring techniques* To overcome the problem of similar measuring techniques in the instrument under test and the calibration equipment, a digital method could be devised* A digital system similar to that outline^ below would provide a stable and adjustable source of calibration waveforms* The basis of the system is a sine look-up table read only memory* The memory locations are sequentially addressed and the stored information is fed to an analogue to digital converter* As the look-up table only holds one quadrant it is necessary to access the locations in an ascending and then a descending manner to obtain the positive half cycle* This is followed by the inverse of the above to obtain the negative half cycle* By utilising a second look-up table, but delaying the addressing of each location in one table with respect to the other table, two sine waves varying - 62 in phase may be obtained* The phase angle is varied by alter ing the addressing delay of one read only memory with respect to the other* The major problem is the discrete output steps* Due to the small number of steps per quadrant (32 for the National DM7598AA sine look-up table), caused by the limited storage of integrated circuit memories, each step is significant in terms of phase angle eg* A one hundred and twenty-eight location memory would have each step equal to * pQ degree * approx* 0*7 degree* The zero crossing point would be undefined by * 0*7 degree* As this is greater than the required accuracy this technique would not be suitable unless some sort of filter could be used* Filters however, introduce phase shift and therefore each channel would have to be matched for phase delay before a useful calibration could be made* Other techniques could no doubt be devised whereby digital interpolation could be made to provide many more steps in the two waveform used for calibration of digital phasemeters* This is an area where future work should be pursued* For periodic signals with the same frequency but different wave forms, there is of course, no unique definition of phase angle* The definition based on zero crossings seems appropriate for many causes but in some it may not be so* Particular care must there fore be taken when using a ’’phase angle” derived from one partic ular measurement technique* § BIBLIOGRAPHY (1) Ehret* R.L., Wood, L.E., andThompson, M.C.: "Linear Integrated Circuit Phasemeter", IEEE transactions on Instrumentation and Meas urement, IM - id, No* 3• Sept* 1969* (2) Paul, C*J*: "Phase Measuring with Increased Accuracy", Electronic Engineering, July 1971* pp52-55« (3) Kuznetskii, S.S., and Chmykh, M*K*: "Digital Methods of Measuring Phase Shift (Survey)", Pribory i Taknika Eksperimenta, No* 5* pp7-19* Sept-Oct, 1970* (4) McKinney, J.E.i "Digitized Low Frequency Phasemeter Assembled form Logic Modules", Journal of Research of the National Bureau of Standards, 71c, No* 3 July-Sept* 1967* (5) Byers, C.s "IC Crystal controlled Oscillators", Motorola Application note AN-417* (6) Bombi, F., and Ciscato, D.i "Digital Power Factor Meter Has High Order of Accuracy"., Electronic Engineering, February 1971* PP55-58 • (7) Golding, E,W., and Widdis, F.C.* "Electrical Measurements and Measuring Instruments", Fifth edition Pitman* (8) Terman, F.E., and Pettit, J*M.t "Electronic Measurements", Second edition, McGraw-Hill. (9) Smith, J*I«: "Modern Operational Circuit Design", Wiley-Inter- science* (10) Hanson, R*C*,t "Narrowband Noise Immunity in a Broadband Gain Phasemeter", Newlett Packard Journal, May 1972* (11) Smirnov, P.G., Belen’kii, B.Z* and Murashov, O.V. Byull Izobret, No*6* 1967# (12) Johnson, G*J*: "Frequency Measurements of the N*S*W* Electricity Supply System"* Proc* IREE Aust* Volume 26, No. 12* December 1965* p296. BIBLIOGRAPHY p .2. (13) MI«C. Provides On Card Regulation for Logic Circuits”, National Semiconductor Application note 42, February, 1971* (14) Dobkin, R.C.: ’’High Stability Regulators”, National Semiconductor Linear Brief 13* January, 1971« (15) Knight, R.B.D*: ’’Design Criteria for Logic Power Supplies”, Wireless World, January 1973* pp4l-43. (16) Frederickson, T.M«, Howard, W.M* and Sleeth, R*S*: ’’The LM3900- A New Current Differencing Quad of * Input Amplifiers”, National Semiconductor Application note 72, September 1972* -65- 9. APPENDIX SPECIFICATIONS OF CALIBRATION EQUIPMENT A* Adret CS2Q1 Frequency Synthesiser Frequency range - 0.1 Hz to 1, 999»999«9 Hz in 0.1 Hz steps Output 1 volt rms into g 50 ohms load Frequency stability - 5 parts in 10° day The CS201 is basically a phase locked loop. A comparator compares the frequencies F/n and f and controls the oscillator so that R/n-f and thus F-nf • If the scaler is a variable ratio divider, F varies to satisfy the above equation and has the same accuracy and stability as f. The division factor of the scaler is selected by the injection of a coded digital value which alters the capacity of the scaler. -66- 9* APPENDIX SPECIFICATIONS OF CALIBRATION EQUIPMENT B. HP5342L vith 5262A plug in module Time Interval Specification Range 1 jib - 10 second (start and stop must be spaced by 1 fis to give useful readings with 0.1 jib resolution.) Accuracy + 1 period of standard frequency counted * time base accuracy. Input 0.3 volt peak to peak minimum. Input impedance 10K ohms on X.l and X.2 multiplier positions. 100K ohms on X.3 to X.100 positions.