Isplever 5.1 Release Notes

ispLEVER 5.1 Release Notes

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ii ispLEVER 5.1 Release Notes Contents

Chapter 1 New Features and Enhancements 1 Importing Existing Projects into ispLEVER 5.1 2 New Device Support 2 Preference Flow Enhancement for FPGA Designs 3 FPGA Preference Editor 4 More Flexible Display 4 PLL Attributes Setting 5 New Option for PERIOD and FREQUENCY Preferences 5 Vref Setting Dialog Box 7 Pin Layout Report 7 New IPexpress Tool for FPGAs 8 Project Navigator 10 News Panel 10 Target Device Detection When Importing LPC Modules 11 Net Attributes Editing 11 Creating HDL Templates from Schematic Symbols 11 Map, Place & Route Performance Improvements 11 Equation Report for MachXO 14 Place & Route Report Clock Summary 15 I/O Timing Report 16 Memory Initialization 16 Retiming Option 17

ispLEVER 5.1 Release Notes iii Contents

Timing Preference Auto Generation 17 New Examples 17 MATLAB/Simulink 18 Two New Blocks 18 Simulink Support for Additional FPGAs 18 Debug - Signal Probe 18 Other ispLeverDSP Enhancements 18 Power Calculator 19 Frequency Settings Dialog Box 19 Simulators 20 NC-Verilog and VCS 20 ModelSim 6.1a 20 Synthesis 21 Synthesis Tool Upgrades 21 Properties for Synplify Synthesis Process 21 Precision RTL Synthesis Replaces LeonardoSpectrum 22 FPGA Performance Analyst 22 ispTRACY 23 IPexpress Generates ispTRACY Cores 23 Sample After Trigger Option 24 New Settings for TRST and ispEN/BSCAN Pins 24 Moving the Signal Display Left or Right 25 Logic Analysis on Multiple Devices Supported 25 ispVM System 25 Version 15.4 25 Version 15.3 26 CPLD and SPLD 28 New Modules in Module/IP Manager 28 ispMACH 4000 New Constraints 28 Slack Report in Performance Analyst 28 New Option for ispXPLD in Location Assignment Dialog Box 29 Documentation and Online Help 30 Quick Start Guide 30 New Tutorials 30 Simulating Designs for Lattice FPGA Devices 31 Enhanced Online Help, Search, and Index 31 FPGA Design Guide 32

Chapter 2 Known Issues and Solutions 33 Power Calculator 33 Standalone Power Calculator Fails to Open a New Project 33 Floorplanner/Preference Editor 34 iv ispLEVER 5.1 Release Notes Contents

Floorplanner Loses Anchor Point and BBOX 34 Floorplanner Loses LOCATE Preferences 34 Floorplanner Copies UGROUP/PGROUP from HDL to LPF 34 PIO PGROUP Dialog Box Does Not Save Bank 35 Package View Does Not Create CSV 35 Pin Layout CSV Shows VCC, GND, VCCAUX, VCCPLL in Bank 0 35 Pin Layout CSV Shows VCC, GND, VCCAUX, VCCIO as Pin Names 35 DRC in Package View Is Grayed Out 36 Floorplanner Opens With My Documents Folder 36 Stand-alone Floorplanner Does Not Open Database Design File 36 Floorplanner/Preference Editor Triggers Firewall Message 37 IPexpress and Module/IP Manager 37 Standalone Module/IP Manager Does Not Load LPC 37 Cannot Import Module/IP Manager LPC Files Generated in 4.2 or 5.0 38 ispLeverDSP 38 False Undefined Property Warning 38 RAM/ROM Blocks Cannot Support Data Greater Than 64 Bits 38 MATLAB Sees Algebraic Loop with RAM Blocks 39 Dual-Port RAM with Different Data Widths Have Same Data Rate 39 Parallel-to-Serial, Serial-to-Parallel Clock Enable from Testbench 39 Parameter Names of EBR and Distributed RAM/ROM Changed 40 Input Ports of EBR RAM/ROM and Distributed RAM/ROM Changed 40 FFT and FIR Compiler Do Not Work 40 Some DSP Elements Are Not Supported in Non-DSP FPGAs 41 Simulation Mismatch When Downsample Drives Parallel-to-Serial 41 Output of FIR Filter Incorrect for Four-Multiplier Design 41 FIR Filter Simulink Block Does Not Support Saturation Logic 41 Limit on Interpolation Factor 42 Map Design Process 42 DRC Errors for Sub-module Connectivity Problems 42 Rerunning Map Design Produces Warnings About IOBUF 42 Place and Route Design Process 43 DQS Bus Assignment Fails 43 PAR May Violate PGROUP BBOX Specifications 43 Synthesis 43 Design Fixed In a Previous Version Fails In This Version 43 Project Path with Space Causes m_att.exe Error 44 Mapping Fails with Exit Code 0002 44 Digital Line Detect Error with Synplify Synthesis 45 Attributes preserve_driver and preserve_signal Fail 45 Lattice and Actel OEM Versions of Synplify Licenses Conflict 45 I/O Assistant Flow Does Not Work with Precision RTL Synthesis 46 ispTRACY 47

ispLEVER 5.1 Release Notes v Contents

ispTRACY Core Requires Synplify Synthesis Tool 47 Unsupported VHDL and Verilog Features in ispTRACY IP Manager 47 Connecting VHDL Signals to ispTRACY Core 48 ispTRACY Requires ispVM to Run from Starter 48 Generate Bitstream Data (bitgen) 48 SPI Option for CONFIG_MODE Not Recognized 48 SPI Flash Memory Fails to Boot FPGA 49 Examples 49 FIFO and FIFO_DC Examples Fail in Functional Simulation 49 Documentation 50 Synthesis Data Flow Tutorial Place-and-Route Does Not Complete 50

vi ispLEVER 5.1 Release Notes 1

New Features and Enhancements

Version 5.1 of the ispLEVER® design tools adds several new features and a broad variety of enhancements to make designing for Lattice Semiconductor programmable devices easier than ever. The design tools also include support for the latest Lattice Semiconductor devices.

Major changes include the handling of preferences in FPGA designs. You can modify preferences at any stage of the design, using the editing tools to their fullest extent. For FPGA designs, IPexpress replaces Module/IP Manager. In addition to generating modules, IPexpress includes the infrastructure that allows you to try out ispLeverCORE products as cores supporting this flow are released. The Map Design, Place & Route Design, and I/O Placement processes have better performance. Several new properties give you more control. To provide better focused information and faster access, the online help is now organized by device type.

Some of the changes affect how you import designs from previous versions of ispLEVER. For more information, see “Importing Existing Projects into ispLEVER 5.1” on page 2.

For updates to this software and documentation, run ispUPDATE. Choose ispUPDATE from the Lattice Semiconductor program group in the Windows Start menu.

ispLEVER 5.1 Release Notes 1 Importing Existing Projects into ispLEVER 5.1 New Features and Enhancements

Importing Existing Projects into ispLEVER 5.1

Below are some important points for migrating designs from prior versions of ispLEVER into version 5.1:

Once you import a design into version 5.1 of the ispLEVER system, you cannot reopen the design in the previous version. In case you need to work with the design in the previous version, make a copy of the design before importing it.

With version 5.1, ispLEVER’s handling of preferences is greatly improved. Part of the improvement is the use of two preference files instead of one: the previous Physical Preference File (PRF) and a new Logical Preference File (LPF). For more information about the new preference flow, see “Preference Flow Enhancement for FPGA Designs” on page 3. When you open an existing project in the new Project Navigator, you see a prompt message stating that the current version of ispLEVER requires an LPF. Click Yes. The software copies the logical preferences from the existing PRF to a new LPF. It also makes a backup copy of the PRF named .pr5. Then you can continue to design and run your project in ispLEVER 5.1.

The SPI3 preference has been renamed “SPI”. Either rename the preference in both the LPF and PRF, or change the preference in the Preference Editor.

The Module/IP Manager Lattice Parameter Configuration (LPC) files generated in ispLEVER version 4.2 or 5.0 cannot be imported into ispLEVER version 5.1 because the module parameters have changed. Regenerate the module in version 5.1 with the new IPexpress (see “New IPexpress Tool for FPGAs” on page 8).

New Device Support

This release adds preliminary support for the following devices:

LatticeXP™: XP15, XP20

MachXO™: XO1200, XO2280

2 ispLEVER 5.1 Release Notes New Features and Enhancements Preference Flow Enhancement for FPGA Designs

Preference Flow Enhancement for FPGA Designs

The new ispLEVER preference flow provides much more flexibility and persistence in constraining FPGA designs. It enables you to create and edit logical preferences at any stage of the design flow, using the Preference Editor, Floorplanner, or Text Editor, and know that these preferences will be maintained as you re-map the design or re-run placement and routing.

With the new preference flow, there is less need to go back to the design to modify preferences. Logical preferences—including logical equivalents of post-map grouping preferences—are written to the logical preference file (LPF) and persist through all stages of the process flow. This allows you to return to the pre-map tools to modify logical preferences without overwriting those made in the post-map stage. The new preference flow saves you time and labor and lets you use the ispLEVER editing tools to their fullest extent.

The Logical Preference File An LPF is generated when you create a new project in the Project Navigator. This file stores all logical preferences that you create or modify in the Preference Editor, Floorplanner, or Text Editor. It also stores preferences from the design that have been modified. These modified preferences in the LPF take precedence over those in the design files.

The LPF is visible in the Process Window of the Project Navigator and is the preference file that most designers use during the course of developing and implementing the design. By using the LPF, you ensure that your preference changes are persistent.

The Physical Preference File Preferences saved in the LPF are written to the physical database and to the physical preference file (PRF) during the mapping process. The PRF is treated as a background file and is not visible in the Project Navigator Processes Window. Though the PRF can be opened from the project directory, its use for modifying preferences is no longer necessary and not recommended for ispLEVER 5.1. Manually edited PRF preferences are inconsistent with those in the LPF.

Timing Preference Auto Generation In the 5.1 release, if you do not define any timing preference for your FPGA design, the software automatically generates timing preferences for you. The auto-generated preferences are written into the Physical Preference File (*.prf). You can either accept these preferences (if a successful PAR can be reached), or use them as the starting point to set your own timing preferences.

To see the auto-generated timing preferences in the TRACE report, check the Auto Timing option in the TRACE Options dialog box of the Project Navigator. ispLEVER 5.1 Release Notes 3 FPGA Preference Editor New Features and Enhancements

FPGA Preference Editor

The Preference Editor now includes the following features.

More Flexible Display The three main sections of the Preference Editor—Preference Sheet, Package View, and Output Pane— have been re-organized as three separate windows to give you more flexibility in organizing your work space. Initially all three windows open together.

With the enhanced preference flow, the Preference Editor shares the Floorplanner’s Package View feature. Look in the Floorplanner help for information about Package View.

4 ispLEVER 5.1 Release Notes New Features and Enhancements FPGA Preference Editor

PLL Attributes Setting PLL configurations are supported by LatticeECP/EC and LatticeXP device families. After generating a PLL module, you can edit its attributes in the PLL Attributes sheet of the Pre-Map Preference Editor. The attribute values you specify in the Preference Editor take precedence over those defined during module generation.

For more information on sysCLOCK™ PLL attributes, see LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide, Technical Note TN1049.

New Option for PERIOD and FREQUENCY Preferences The PAR_ADJ keyword has been added to the PERIOD and FREQUENCY preferences. This keyword allows you to experiment more efficiently with over-constraining your design to determine your best constraint settings. The PAR_ADJ value is subtracted from the PERIOD and added to the FREQUENCY preferences during Place & Route but not during the TRACE static timing analysis. So Place & Route uses more demanding timing constraints to drive timing-driven place-and-route than the target timing preference set for TRACE timing analysis.

ispLEVER 5.1 Release Notes 5 FPGA Preference Editor New Features and Enhancements

With the PERIOD preference, PAR_ADJ does not affect the high/low duty time. If you want to adjust the high/low duty time as well, use PAR_ADJ with FREQUENCY.

For example:

PERIOD PORT "CLK2" 10.0 ns HIGH 6.0 ns PAR_ADJ 1.0 ns ; TRACE reports the required period time as 10.0 ns with a high_duty time of 6.0 ns. But a 9.0 ns (10.0 - 1.0) period time with the unchanged high_duty time drives Place & Route.

FREQUENCY NET "CLK1_c" 250.0 MHz PAR_ADJ 25 ; TRACE reports the required frequency as 250 MHz while 275 MHz (250 + 25) drives Place & Route.

You can set PAR_ADJ together with the PERIOD or FREQUENCY preferences in the PERIOD/FREQUENCY Preference dialog box of the Pre- Map Preference Editor.

6 ispLEVER 5.1 Release Notes New Features and Enhancements FPGA Preference Editor

Vref Setting Dialog Box A new dialog box—Vref Setting dialog box—has been added to the Pre-Map Preference Editor. You can use this dialog box to add VREF strings and set VREF locations.

For the detailed procedure, refer to Preference Editor Help > Procedures > Setting Preferences > Setting VREF Locations. For more information on using VREF preferences, see the LatticeECP/EC and LatticeXP sysIO Usage Guide, Technical Note TN1056.

Pin Layout Report The Preference Editor can now export a pin layout report in comma-delimited text format (*.csv). The report not only lists all the pins on the target device, but also includes detailed pin lock and pin attributes information. Pin layout reports are very helpful to define FPGA part symbols for use in a schematic editor. You can view this report in any CSV-supported program, such as Excel.

To export a pin layout report from the Preference Editor, choose File > Export > Pin Layout CSV File.

The pin layout report can be exported from both the Pre-Map Preference Editor and the Post-PAR Preference Editor.

ispLEVER 5.1 Release Notes 7 New IPexpress Tool for FPGAs New Features and Enhancements

New IPexpress Tool for FPGAs

A new tool called IPexpress allows you to access a unified library of parameterized modules for use in your designs. IPexpress replaces Module/ IP Manager for LatticeECP/EC, LatticeXP, and MachXO devices.

To run IPexpress from the ispLEVER Project Navigator, choose Tools > IPexpress.

Or, you can run IPexpress in standalone mode. From the Start menu, choose Programs > Lattice Semiconductor > Accessories > IPexpress.

A large selection of IP are pre-installed with your ispLEVER software. IPexpress allows you to try a free, no-risk evaluation for some ispLeverCORE products.

8 ispLEVER 5.1 Release Notes New Features and Enhancements New IPexpress Tool for FPGAs

You can also use IPexpress to view and download the latest IP available from the Lattice web site. User-parameterizable IP cores will become available soon. Please watch the Lattice Semiconductor web site for new IP cores.

Cores included with this release are:

Ten Gb Ethernet MAC FFT Complier

Triple Speed Media Access FIR Complier Controller Interleaver/De-interleaver Turbo Decoder NCO Turbo Encoder RS Decoder PCI Master/Target RS Encoder PCI Target DDR DSRAM Controller Parallel RapidIO DDR DSRAM Controller - Block Convolutional Encoder Pipelined

Block Viterbi Decoder DDR SDRAM Controller - Non- pipelined CIC filter FCRAM I Controller Correlator MC-DMA Controller FFT

Information on all ispLeverCORE IP Modules, including data sheets, brochures, and downloads, can be found on the Lattice Semiconductor web site at:

www.latticesemi.com/products/intellectualproperty

After reviewing the documentation, you can use the evaluation model provided in IPexpress to perform functional simulation of the IP core. The ispLeverCORE evaluation netlist can be instantiated into Verilog and VHDL top-level projects. After synthesizing the top-level design (with the core described only as a black box), the entire project is compiled into a Lattice database. Then the Place, and Route processes can be run to check the fit of the design. Finally, static timing analysis can be run on the evaluation IP using the Performance Analyst™ tool.

After the ispLeverCORE is purchased and licensed, you can continue the implementation and programming flow. You can then perform full timing simulation and generate a bitstream file for programming a Lattice device.

More information about IPexpress can be found in the IPexpress online help. ispLEVER 5.1 Release Notes 9 Project Navigator New Features and Enhancements

Project Navigator

The Project Navigator has added the following functions in this release.

News Panel An embedded Lattice web browser—the News panel—is integrated into the Project Navigator window. The panel displays the “What’s New at Lattice” web page the first time Project Navigator is opened. You can click the links or enter search keywords in this panel to browse the entire Lattice web site.

To use the News panel, you must have an Internet connection.

The News panel is by default a docked window at the bottom of the Project Navigator window. To display or hide this panel, choose View > News Panel or click on the toolbar.

10 ispLEVER 5.1 Release Notes New Features and Enhancements Project Navigator

Target Device Detection When Importing LPC Modules When you import a Lattice Parameter Configuration File (*.lpc) into a design project, the Project Navigator now checks the LPC file to see if it is targeted to the current device. If not, a message appears in the Output Panel, asking you to double-click the imported LPC file to regenerate the module.

Net Attributes Editing After adding symbols and wires to your schematic, you can use the Net Attributes Editor of the Schematic Editor to set I/O configuration and pin lock attributes for the net from or to the external signals.

Creating HDL Templates from Schematic Symbols The Symbol Editor has been improved to allow creation of a Verilog or VHDL template from an existing schematic symbol. To create a Verilog or VHDL template from a symbol, choose File > VHDL Template or Verilog Template in the Symbol Editor.

Map, Place & Route Performance Improvements The following properties have been added to the Project Navigator to improve the results of the map, place and route processes.

Map Design Process The Map Design process now includes Timing Driven Mapping, which allows you to apply timing-driven logic collapsing and optimization to further optimize the critical paths. Timing Driven Mapping reads the preference file and calculates the slacks for all constrained paths. The mapping optimizes the critical paths based on the slack distributions. Options are True and False (default).

In the map command, the syntax to set this property to True is: –tdm

Place & Route Design and I/O Placement Processes Both of these processes have several new properties:

PLC Input Limit Allows you to control the programmable logic cell (PLC) inputs to reduce the traffic to heavily congested areas. Options are Off (0, default), Low (1), Medium (2), and High (3). ispLEVER 5.1 Release Notes 11 Project Navigator New Features and Enhancements

When turned Off, there are no limits and a very high input number may be used as long as the total does not exceed the hardware limit. Off also blocks the PLC Input Neighbor Size property (described below). Low, Medium, and High settings allow an increasingly high number of inputs. If congestion is a problem in your design, try the Low setting. This typically reduces fMAX. If fMAX is then a problem, experiment with higher settings and with different settings of the PLC Input Neighbor Size property. In the par command, the syntax of this property is: -exp parPlcInLimit=0 | 1 | 2 | 3

PLC Input Neighbor Size Allows you to control the input limit to a specified region to reduce the traffic to the heavily congested area. This property sets a region size that places limitations on incoming signals on those PLCs in the region. Options are 1 PLC region (1, default) and 2X2 PLC region (2). The PLC Input Neighbor Size property is active only when the PLC Input Limit property (described above) is turned on (Low, Medium, or High setting). In the par command, the syntax of this property is: -exp parPlcInNeighborSize=1 | 2

Path-based Placement Allows you to apply path-based placement. Path-based placement gives better performance and more predictable results. Options are OFF (default) and ON. In the par command, the syntax of this property is: -exp parPathBased=OFF | ON

Auto Hold-Time Correction When this property is set to ON, the router automatically inserts extra wires to compensate for hold-time violations on registers that are directly connected to input pads. This has a negative impact on your setup time. If the setup time is more design critical, turn this property off. This property is ON by default for MachXO devices and OFF for all other FPGAs. For backwards compatibility for releases before ispLEVER 5.1, you can use the MACHXO_HOLD option. In the par command, the syntax of this property is: -exp parHold=OFF | ON

12 ispLEVER 5.1 Release Notes New Features and Enhancements Project Navigator

Clock Skew Minimization Balances routing to reduce skews for clock signals that are not assigned to the global clock tree. Options are OFF (default), 1, and 2. The 1 setting routes from driver pins to each clock load with pre-computed delay lower bound for balanced routing. This setting may help when the candidate net has a very small span (for example, the bounding box span is within 2 to 3 PLCs) and possesses small skew. The 2 setting routes a clock trunk first and then routes from the trunk to each clock load with pre-computed delay lower bound for balanced routing. This setting usually creates better results with less time and memory use. In the par command, the syntax of this property is: -exp clockSkewMin=1 | 2 To turn this property off, leave it out of the par command. (OFF is the default value.)

Using Clock Skew Minimization Clock Skew Minimization (CSM) is a very CPU- and memory-intensive application that is also sensitive to the design and the device type. Follow these steps to make the best use of CSM: 1. Try to map the design with the smallest possible device. This helps reduce cost and increase performance. It also reduces the problem complexity that CSM needs to handle. 2. Run the first pass of Place & Route and the Place & Route TRACE Report in the regular flow with the CSM property turned off. Check the timing report (.twr) for any FREQUENCY preference that has substantial skew on its driving clock net. Usually this occurs with nets that cannot be assigned to primary or secondary routing resources by default. 3. Check such nets to see if they are gated clocks. CSM has no effect on gated clocks since they create interclock domains. 4. If the candidate skewed net is a pure clock net (1 level only), add the following two preferences to the Physical Preference File (.prf): PROHIBIT PRIMARY NET ; PROHIBIT SECONDARY NET ; 5. Set the Clock Skew Minimization option to 2 (-exp clockSkewMin=2 in the par command) and rerun Place & Route. Always start CSM from strategy 2. Strategy 1 serves as an alternative only in some special cases. Most of the time, strategy 2 yields better results with less CPU time and memory use.

ispLEVER 5.1 Release Notes 13 Project Navigator New Features and Enhancements

When the candidate net has a very small span (for example, the bounding box span is within 2 to 3 PLCs) and a small skew, strategy 1 can be tried as an alternative. If it creates better results than strategy 2, use strategy 1 instead. 6. Add the following preference to the .prf file that trce uses to report timing. Apply the new preference to both regular routing and CSM routing results for skew comparison. The “-max” option must be used with the trce command for a fair maximum-skew comparison. MAXSKEW NET 1.0 ns ; // 1.0 ns can be any value Do not use the above preference with the par command since it affects regular place-and-route results. For fair QOR comparison, only use it in trce command for reporting purpose. CSM does not consider this preference during minimization. 7. In some designs CSM might not be able to finish due to very long CPU time and huge memory use. In this case, the target net usually has a very large bbox span, many fanout loads, and significant skew. Try to change placement or select a different candidate net to work on.

Equation Report for MachXO The design flow for MachXO devices includes the new Equation Report. The Equation Report lists the output signals of each slice of the mapped design along with the related input signals. It shows the Boolean equations of how the signals are processed within the slice.

The following example is part of an Equation Report. The example shows the output signals of one slice and their related equations. comp 0: SLICE_0 (FSLICE) Q_5Z0Z_0 = (~q_reg_0*(S_L_c*Q_c_7)+q_reg_0*(~S_L_c+Q_c_7)) Q_c_0.D = Q_5Z0Z_0 Q_c_0.CLK = CLK_c Q_c_0.SP = VCC Q_c_0.LSR = GND Q_5Z0Z_1 = (~q_reg_1*(S_L_c*Q_c_0)+q_reg_1*(~S_L_c+Q_c_0)) Q_c_1.D = Q_5Z0Z_1 Q_c_1.CLK = CLK_c Q_c_1.SP = VCC Q_c_1.LSR = GND

14 ispLEVER 5.1 Release Notes New Features and Enhancements Project Navigator

Place & Route Report Clock Summary The Place & Route Report (.par) file includes a Clock Summary Report in the placement report section that includes a matrix listing clock resources. This report applies to LatticeECP/EC and LatticeXP device families. The following example is an excerpt from a Clock Summary report showing global clock resource distribution and top-left (TL) quadrant clock resources: ------Clock Report ------

Global Clock Resources:

CLK_PIN : 1 out of 4 (25%)

PLL : 3 out of 4 (75%)

DCS : 8 out of 8 (37%)

Quadrant TL Clocks:

PRIMARY "clk105" from PLL_CLKOP "PLL3_R10C1.CLKOP", driver "clock_gen_i_pll_13_105_i_PllInst0", clk load = 2

PRIMARY "clk140" from PLL_CLKOP "PLL3_R40C1.CLKOP", driver "clock_gen_i_pll_23_140_i_PllInst0", clk load = 3

PRIMARY DCS "clk_int" from CLK_PIN "A14", driver "clk", clk load = 2

PRIMARY DCS "clk13" from PLL_CLKOK "PLL3_R10C1.CLKOK", driver "clock_gen_i_pll_13_105_i_PllInst0", clk load = 1

PRIMARY : 4 out of 4 (100%)

DCS : 2 out of 2 (100%)

SECONDARY: 0 out of 4 (0%) ispLEVER 5.1 Release Notes 15 Project Navigator New Features and Enhancements

I/O Timing Report The I/O Timing Report process has a new property: All Speed Grade. If you set this property to On, the I/O Timing Report provides an in-depth analysis on all available speed grades.

Memory Initialization The new Memory Initialization process allows you to assign different initial values to a component memory (such as RAM and ROM blocks) for device configuration without having to do so through synthesis, Map, or Place & Route. You initialize memories in this manner by running the Memory Initialization process in Project Navigator after the Place & Route Design process has been run. This process writes initialization values directly into your placed-and-routed physical design (.ncd) file with information from an input memory initial (.mem) file.

This feature only supports FPGA memory modules generated by IPexpress.

The process uses the following properties:

Memory Initial File Identifies the name of the input .mem file.

Memory Module File (.lpc) Identifies the name of the input Lattice Parameter Configuration file (.lpc) that is generated when you create the module using IPexpress. This file contains the configuration options set in IPexpress during module generation.

Memory Instance Name Identifies the name of the instance for the module that appears in the top- level design netlist.

Backup Design File Allows you to specify whether or not you wish to generate a backup of your physical design (.ncd) file that does not contain your memory initialization changes.

Note You must provide names for the Memory Initial File, Memory Module File, and Memory Instance Name properties before running the Memory Initialization process. Instance names of these files are case sensitive.

16 ispLEVER 5.1 Release Notes New Features and Enhancements Project Navigator

Retiming Option The NORETIME attribute, which prevents retiming, is now also available as a preference. The NORETIME preference can be added manually to the logical preference file. The syntax is: NORETIME TRUE | FALSE [(COMP )+];

Timing Preference Auto Generation If you do not define any timing preferences for your design, the software will automatically generate fMAX preferences for each clock network and write them into the PRF file during the Map Timing Checkpoint process. These timing preferences are an estimate of possible fMAX that may drive the Place & Route process to get better performance. You can either accept these preferences (if a successful PAR can be reached), or use them as the starting point to set your own timing preferences.

New Examples Several new example designs are available for FPGAs. Access the examples by selecting File > Open Example. We recommend making a copy of an example before working on it.

Distributed Memories and Counter Shows the functions of three types of distributed memories. It also shows the use of counter modules to generate address and data. Available in versions for LatticeEC™, LatticeXP, and MachXO devices, all in both Verilog and VHDL. Look under fpga\\memory\distributed.

MAC Example Shows a signed 18x18 MAC module. Two different versions show the module being inferred and instantiated. Both are available in Verilog and VHDL. Look under fpga\LatticeECP\infer\mac_18x18_signed and fpga\LatticeECP\instantiate\mac_18x18_signed.

Multiply Example Shows an unsigned 36x36 Multiply module. Two different versions show the module being inferred and instantiated. Both are available in Verilog and VHDL. Look under fpga\LatticeECP\infer\mult_36x36_unsigned and fpga\LatticeECP\instantiate\mult_36x36_unsigned.

MultAddSum Example Shows a signed 18x18 MultAddSum module. Two different versions show the module being inferred and instantiated. Both are available in Verilog and VHDL. Look under fpga\LatticeECP\infer\multaddsum_18x18_signed and fpga\LatticeECP\instantiate\multaddsum_18x18_signed.

ispLEVER 5.1 Release Notes 17 MATLAB/Simulink New Features and Enhancements

MATLAB/Simulink

Two New Blocks Two new blocks have been added to the ispLeverDSP MATLAB®/Simulink® blockset:

Subsystem Generator provides a way of specifying options at a localized scope level.

ispTRACY™ allows you to generate the JTAG module that contains ispTRACY cores that can be used with the Lattice ispTRACY Logic Analyzer.

Simulink Support for Additional FPGAs The MathWorks® Simulink now supports the LatticeEC™, LatticeXP, and MachXO device families. Only legal selections are offered for the selected family. For example, you cannot target a multiplier to a DSP block if the LatticeXP family is selected.

Debug - Signal Probe The Signal Probe block converts the input to a double value. This block has no impact on hardware and does not affect the generated testbench. The Signal Probe block is useful for examining internal signals during the simulation phase.

Other ispLeverDSP Enhancements

True dual port RAM write/normal modes support

True/pseudo mixed port width support

ROM/SP/Pseudo Distributed RAM Support

AddSub VHDL implementation change (goes through IPexpress)

DSP MAC, Multadd2, Multadd4 Sub and Dynamic AddSub modes support

Delay/Addressable shift register distributed implementation support

QOR enhancement to EBR by removing delay in rst path

QOR enhancement to all DSP blocks by removing delay in rst path

Mismatch due to asynchronous rst resolution to EBR and DSP blocks

18 ispLEVER 5.1 Release Notes New Features and Enhancements Power Calculator

PFU multiplier support

Constant multiplier VHDL implementation enhancement to use module manager VHDL implementation

Critical Sample Rate DRC Enhancements

EBR single-port RAM normal and write through mode support

EBR/Distributed RAM Disable/Enable Option for Write Enable, Read Enable, and rst ports

Power Calculator

Frequency Settings Dialog Box The new Power Calculator - Frequency Settings dialog box enables you to specify a global default frequency value for the clocks listed in the Power View and Icc View tabs in the main Power Calculator window. The default frequency can be a value you specify, or taken from the Trace Report file. If taken from the Trace Report file, you can use the preference or the trace value, or the lesser of the two. These default values appear in blue font in the Frequency (MHz) column.

To open the Power Calculator - Frequency Settings dialog box, choose Edit > Frequency Settings.

ispLEVER 5.1 Release Notes 19 Simulators New Features and Enhancements

Simulators

NC-Verilog and VCS This release adds support for two third-party simulators: Cadence® NC-Verilog® and Synopsys® VCS®. You can use these simulators, along with the ispLEVER software, to test Verilog designs.

Note Lattice Semiconductor does not supply the NC-Verilog or the VCS simulators. You must obtain them independently.

For information about running the NC-Verilog and VCS simulators, see “Simulating Designs for Lattice FPGA Devices” in the online help at FPGA and Crossover Design > Software Manuals > Software User Manuals.

NC-Verilog You can use the Cadence NC-Verilog simulator, version 5.4 or later, to simulate Verilog designs targeting most Lattice Semiconductor devices including: LatticeECP/EC, LatticeXP, MachXO, ispMACH™ 4000, ispXPLD® 5000MX, and ispGDX2™ device families.

Before simulating designs with the NC-Verilog simulator, you need to perform a few steps to set up the Lattice simulation libraries. Detailed procedures are described in the online help at CPLD and SPLD Design Help > Design Simulation > Setting Lattice Libraries for NC-Sim Simulator.

VCS You can use the Synopsys VCS simulator, version 7.2 or later, to simulate Verilog designs targeting most Lattice Semiconductor FPGAs including: LatticeECP/EC, LatticeXP, and MachXO device families.

ModelSim 6.1a This release includes version 6.1a of the Mentor Graphics® ModelSim® simulator. For more information about the 6.1a version, open ModelSim by choosing Tools > ModelSim Simulator in Project Navigator. Then, in ModelSim, choose Help > Welcome Menu.

20 ispLEVER 5.1 Release Notes New Features and Enhancements Synthesis

Synthesis

Synthesis Tool Upgrades This release includes new versions of the Synplicity® Synplify® for Lattice and Mentor Graphics Precision RTL® Synthesis tools.

New features of Synplicity Synplify 8.2c include:

Memory inference

Shift register inference

Opening up the carry chain (can pack more logic into LUT4)

Area reduction for the MachXO family

Synplify does not infer Dual Port RAM EBR in this release. Please check for a Synplify update with ispUPDATE or on the Lattice Semiconductor web site.

Synplify PRO users, please refer to the Synplify PRO user manual for new features that support Lattice Semiconductor devices.

New features of 2005B Precision OEM.63 include:

Retiming

ROM inferencing (RAM inferencing is already in 2005A.)

Properties for Synplify Synthesis Process Several new properties give more control over the Synplify Synthesize Verilog File and Synplify Synthesize VHDL File processes. To set the properties, right-click the process in the Project Navigator’s Process Window and choose Properties in the drop-down menu. The Properties dialog box opens. The new properties are:

Area Sets the Area mode for Synplify synthesis.

Fmax Frequency Specifies frequency for Synplify synthesis.

Fanout Limit When the specified fanout limit is achieved, logic is duplicated.

ispLEVER 5.1 Release Notes 21 FPGA Performance Analyst New Features and Enhancements

Disable IO Insertion Directs Synplify synthesis to insert or not insert I/O buffers in your design.

Force GSR Directs Synplify synthesis to automatically infer, always infer, or not infer Global Set/Reset in your design.

Precision RTL Synthesis Replaces LeonardoSpectrum Precision RTL Synthesis, the premier synthesis tool from Mentor Graphics, replaces LeonardoSpectrum™ as the preferred Mentor Graphics synthesis tool in ispLEVER. LeonardoSpectrum is not included in this release. Lattice will continue to support LeonardoSpectrum until December 2005 and encourages you to make the transition to Precision RTL Synthesis from LeonardoSpectrum in order to harness the new features and improved performance of this synthesis software in your Lattice device designs.

FPGA Performance Analyst

The Performance Analyst has been enhanced to include timing information for LatticeXP devices and propagation delay time (tPD) for all FPGA devices. Also, the Delay Table now includes the source and destination cells’ logical component names. This information allows you to more easily relate the cells to elements of your design. Look for columns titled “Cell Name (Net Name)” following the related Source List and Destination List columns.

22 ispLEVER 5.1 Release Notes New Features and Enhancements ispTRACY

ispTRACY

The ispTRACY tools add the following new features in this release.

IPexpress Generates ispTRACY Cores For all FPGA devices except ispXPGA®, ispTRACY logic analysis cores are now generated with the new IPexpress. Use the Jtag module found under Module > Architecture. The ispXPGA devices continue to use the ispTRACY IP Manager but only the RTL installation flow is available. The cores generated by IPexpress and the ispTRACY IP Manager are still linked to designs by the Core Linker of the ispTRACY Manager as in the previous release.

In the JTAG module, you can generate SPI programmer cores in addition to ispTRACY cores. SPI programmer cores enable you to configure the SPI

ispLEVER 5.1 Release Notes 23 ispTRACY New Features and Enhancements

Serial Flash memory with the ispVM® System and an ispDOWNLOAD® cable through a LatticeECP/EC device's JTAG ports while the FPGA is operating on a board. The SPI programmer core, also called a Soft SPI Interface, connects the JTAG interface to the SPI Serial Flash interface. You cannot program the SPI Serial Flash through the JTAG interface unless the FPGA contains the Soft SPI Interface. The Soft SPI Interface is placed into an NGO file that is instantiated into the VHDL or Verilog user code.

Sample After Trigger Option The Sample Around Trigger option in the Trace Mode section of the Trigger Setup tab is now called Sample After Trigger, but its function remains the same.

New Settings for TRST and ispEN/BSCAN Pins The Cable and I/O Port Setup dialog box activated by the Device > Connection Setup command includes two new settings for the TRST pin and the ispEN/BSCAN pin:

Set High, Then Low - Specifies that the TRST or ispEN/BSCAN pin first be set active high and then set active low.

Set Low, Then High - Specifies that the TRST or ispEN/BSCAN pin first be set active low and then set active high.

24 ispLEVER 5.1 Release Notes New Features and Enhancements ispVM System

Moving the Signal Display Left or Right You can move the signal display one time interval to the left or right of an X or O marker. To move the signal display one time interval to the:

left of the X marker, click

right of the X marker, click

left of the O marker, click

right of the O marker, click The state of each signal is displayed in the X and O column of the Signal Analysis tab.

Logic Analysis on Multiple Devices Supported You can now perform logic analysis on multiple devices by linking together the evaluation boards in a chain. The maximum number of devices in a chain is set by ispVM System. You can include devices from vendors other than Lattice Semiconductor, but you must use a scan chain configuration (XCF) file, which you can generate with ispVM System. When you perform logic analysis on multiple devices, you must turn on the Set High, Then Low or Set Low, Then High options for the TRST and ispEN/BSCAN pins in the Cable and I/O Port Setup dialog box. ispVM System

The ispVM System software has been upgraded to version 15.4. Version 15.4 includes the new features and enhancements of version 15.3, which was available as an optional upgrade. To run ispVM System, choose Tools > ispVM System from the Project Navigator.

Version 15.4 The ispVM System, version 15.4, includes the following new features and enhancements:

Universal File Writer supports Multiple Boot PROM files.

Universal File Writer supports customized bitstreams.

Supports FLASH Mode Turbo algorithm for FPGA devices.

Supports Flash EBR (FLEBR) using the MachXO 1200 and 2200, and XP10K devices.

ispLEVER 5.1 Release Notes 25 ispVM System New Features and Enhancements

Implemented a special FLASH Erasure flow for LatticeXP devices to improve programmability.

Improved FPGA Loader and SPI Flash Programming.

Supports multiple SoftIP per Density Scan Support.

Allows VME to HEX conversion through the Generate VME dialog.

Version 15.3 The ispVM System, version 15.3, includes the following new features and enhancements:

LVDS Support The LVDS support ensures the reverse value of the positive pin is shifted into the negative pin when an application-specific BSDL file is used with the Dynamic I/O setting.

TransFR Version 15.3 of ispVM System incorporates the Transparent Field Reconfiguration (TransFR™) flow for LatticeXP devices. The flow consists of two operations. The first operation targets the background programming of the flash memory, and the second controls the I/O states and governs the internal configuration transfer.

ispVM Embedded v12.0 ispVM Embedded v12.0 supports LVDS. The ispVM System software can now generate and process v12.0 VME files. The SVF Debugger was also enhanced to be able to read and convert v12.0 VME files.

SPANSION Parallel Flash Programming This release of ispVM System supports SPANSION parallel flash programming on the LatticeXP device family.

EBR and Bitstream File Merging You can read, edit, and save the Embedded Block RAM (EBR) section of the FPGA device bitstream files, and merge EBR (PROM) files into bitstreams at run time.

Configuration with sysConfig Port This release of ispVM System provides slave serial configuration mode for LatticeECP/EC and LatticeXP device families.

Status Check for SPI Flash Programming A special status checking flow has been introduced for the LatticeECP/EC device family to improve the programmability of the SPI flash module.

26 ispLEVER 5.1 Release Notes New Features and Enhancements ispVM System

Revision D SVF Revision D SVF comments out the frequency statement. You can generate a revision D SVF file by selecting Project > Generate SVF File, clicking Advanced in the Generate SVF File dialog box, and then selecting the Write Rev D Standard SVF File option.

The Universal File Writer has also been improved to provide a command line option for generating revision D SVF files.

Bitmap Changing for Different I/O State Operations The “X” bitmap now has different meaning in different I/O state operations. When the operation is Dynamic I/O, “X” is Leave Alone. When the operation is Custom, “X” is the BSDL default.

Overwrite and Save As Options in ispVM Editors The Overwrite and Save As options were added to the Write button in the following ispVM editors. They allow you to overwrite the current data file, or save the edited data file to a different location or with a different file name.

Control Register 0 Editor

Control Register 1 Editor

Embedded Block RAM Editor

Security and Persistent Fields Editor

SVF Debugger Enhancements The following enhancements have been made to the SVF Debugger.

Manual Tap Machine Operation – The SVF Debugger provides a manual Tap machine debug operation that allows you to step the state machine and toggle the programming signal. To access the operation, choose Command > Mini Step.

More Debug Information in Log File – The log file now reports state machine transitions and delay time for debug if you have selected Continue on Error in the SVF Options dialog box.

Option of Erase Part on Program Error for Flash Devices To prevent loading invalid patterns into FPGA devices, the option Erase Part on Program Error was added. This option allows you to erase the flash device when a verify error occurs.

Conversion from JEDEC to Bitstream for LatticeXP To support fast programming, the Universal File Writer is now able to convert JEDEC files to bitstreams.

ispLEVER 5.1 Release Notes 27 CPLD and SPLD New Features and Enhancements

CPLD and SPLD

The release adds the following new features to support CPLD and SPLD device design.

New Modules in Module/IP Manager The Module/IP Manager has new counter and shift register modules for ispMACH 4000 and ispXPLD 5000MX devices.

ispMACH 4000 New Constraints Two new constraints are supported by the ispMACH 4000 device family.

Adjust_input_assignment This global fitting constraint defaults to Off. When it is set to On, the software adjusts the locations of unlocked input signals more randomly. This is especially useful when your design has high GLB fanin. You can set this constraint in the Global Constraints sheet of the Constraint Editor.

OSM_ORP_bypass This constraint instructs the software to bypass the output routing pool on ispMACH 4000 during the routing process. You can set this constraint in your schematic or HDL source files, or in the Pin Attributes sheet of the Constraint Editor. For details on how to add this constraint to your design source files, refer to CPLD & SPLD Design Help > Design Constraints > OSM/ORP Bypass.

Slack Report in Performance Analyst If you set timing delay constraints for a CPLD design, the Performance Analyst's Delay Table includes a Slack column. This column reports the difference between the real delay and the required delay.

28 ispLEVER 5.1 Release Notes New Features and Enhancements CPLD and SPLD

New Option for ispXPLD in Location Assignment Dialog Box A new option—Signal Originates from—was added to the Location Assignment dialog box of the Constraint Editor for ispXPLD designs.

When you select an output signal in the Signals List and a pin in the Pin List, this option appears in the middle of the dialog box, allowing you to choose an alternate macrocell location for the signal. The option supports output signals (without OE) of regular logic, but does not support memory signals.

ispLEVER 5.1 Release Notes 29 Documentation and Online Help New Features and Enhancements

Documentation and Online Help

The release adds new documents to help you learn how to use the ispLEVER software, online help enhancements, and an expanded FPGA Design Guide.

Quick Start Guide The new “Quick Start Guide for ispLEVER Software” provides a quick and easy introduction to the design process using ispLEVER design tools. The “Quick Start Guide” is available through the online help at Software Manuals > Software User Manuals.

New Tutorials New tutorials are available. Find them through the online help at Tutorials and Examples > ispLEVER Tutorials.

ispLeverCORE IP Module Evaluation Tutorial An updated tutorial describes how to use the new IPexpress tool to download, evaluate, and purchase the IP module packages.

DSP Floating Point to Fixed Point Conversion. This tutorial covers the basic steps in taking a floating-point design in MATLAB/Simulink and converting it to a fixed-point design using the Lattice ispLeverDSP blockset for MATLAB/Simulink.

Synthesis Data Flow Tutorial This tutorial shows you how to use Mentor Graphics Precision RTL Synthesis or Synplicity Synplify with ispLEVER to synthesize a Verilog HDL design and to generate an EDIF file for a Lattice FPGA device. It is intended for the user who is using Precision RTL Synthesis or Synplify for the first time and who is looking for the basic data and process flow from HDL source code to a fully implemented FPGA.

FPGA EPIC Device Editor This tutorial shows you how to work in the EPIC environment and perform basic functions such as viewing and finding objects in the Editing Area, creating object definitions, and programming components.

30 ispLEVER 5.1 Release Notes New Features and Enhancements Documentation and Online Help

Simulating Designs for Lattice FPGA Devices This document explains how to use the Synopsys VCS and Cadence NC- Verilog software to simulate designs that target Lattice FPGAs. It shows you how to use these simulators to perform functional register-transfer-level (RTL) simulation, post-map simulation, and place-and-route gate-level simulation with and without timing simulation.

Enhanced Online Help, Search, and Index The online help is organized by device category, providing more targeted information, faster searches, and improved index and glossary.

Design Help for Each Device Category A self-contained Design Help is provided for each category of Lattice devices: FPGA and Crossover Design, CPLD and SPLD Design, and Digital Interconnect Design. This structure provides more targeted information, a more concise table of contents and faster searches. The help for each related design tool is linked in the “Design Tools” topic and in cross-references throughout the Design Help.

Targeted Design Help from the Project Navigator The Project Navigator's ispLEVER Help command automatically opens the appropriate Design Help for a targeted device. This enables you to quickly find device- appropriate information for your current design. If you have not yet targeted a device, this command opens the ispLEVER Documentation page and allows you to select the Design Help that interests you.

Gateway to Each Help: the ispLEVER Documentation Page The ispLEVER Documentation page is the gateway to the online help for all device categories. It is available from the ispLEVER Help command within each application and from the Windows Start menu. The gateway page enables you to open the appropriate Design Help for any Lattice family. Descriptions of each family are provided in the linked topic “Overview of Lattice Devices.”

Speedier and More Targeted Searches A search in any ispLEVER Design Help takes only a few seconds. The search results are more concise and appropriate to the device category.

Improved Index and Glossary The ispLEVER Help index has been enhanced with hundreds of new keywords and cross-references. The glossary has been expanded with many additional terms and abbreviations for the newer Lattice devices and technology.

ispLEVER 5.1 Release Notes 31 Documentation and Online Help New Features and Enhancements

Expanded Troubleshooting Additional troubleshooting topics were added throughout the help system to improve your ability to quickly work around issues and interpret software system error messages.

FPGA Design Guide The FPGA Design Guide has been updated for the changes of ispLEVER 5.1. Different sections of the guide have also been expanded and enhanced. Major changes include:

Digital Signal Processing This section has been expanded with the latest MATLAB/Simulink blocks, including the Lattice Reference Blockset.

Migrating Designs from Altera or Xilinx FPGAs These chapters have more tips on migrating designs from Altera® and Xilinx® devices to Lattice Semiconductor FPGAs.

Design Guidelines This section has been greatly expanded with the addition of three new chapters:

Chapter 6, “Logic Synthesis Guidelines,” provides a design flow for creating register transfer level (RTL) designs.

Chapter 8, “Attributes and Preferences for FPGA Designs,” describes use of the most common ispLEVER attributes used with RTL designs. This chapter also describes popular compiler directives, attributes, and library components for non-RTL (or non-algorithmic) code.

Chapter 9, “Synthesis Tips for Higher Performance,” provides tips on improving design performance by applying synthesis techniques for both Mentor Graphics Precision RTL Synthesis and Synplicity Synplify for Lattice synthesis software.

Strategies for Timing Closure The “Successful Placement and Routing” chapter is now called “Strategies for Timing Closure.” It describes in detail the new ispLEVER preference flow and explains how to set preferences and write them to the logical preference file (LPF) to help meet timing goals. It shows how the editing tools, such as Preference Editor and Floorplanner, maintain the persistence of preferences at any stage of the design flow. The chapter includes more extensive instructions on performing static timing analysis, including the analysis of TRACE timing reports, and it provides more details about floorplanning with the ispLEVER Floorplanner user interface.

Logic Analysis The “ispTRACY Core Generation and Logic Analysis” chapter has been expanded and updated with the use of IPexpress to generate logic analysis cores in FPGAs.

32 ispLEVER 5.1 Release Notes 2

Known Issues and Solutions

Following are issues and solutions known at the time of this release. If you do not see your issue here, check the Lattice Semiconductor web site for a more recent version of the release notes. Issues and solutions discovered after the release are documented there.

Power Calculator

Standalone Power Calculator Fails to Open a New Project Standalone Power Calculator cannot open a new project. When you click Finish in the Power Calculator - New Project dialog box, nothing happens.

Devices affected: All

Call Power Calculator from Project Navigator. Then open a new project.

ispLEVER 5.1 Release Notes 33 Floorplanner/Preference Editor Known Issues and Solutions

Floorplanner/Preference Editor

Floorplanner Loses Anchor Point and BBOX After assigning anchor point or BBOX for the UGROUPs or PGROUPs in the pre-map or post-map Floorplanner, if you reopen pre-map or post-map Floorplanner, make edits and then save, the previously assigned anchor point and BBOX preferences for some of the UGROUPS are removed from the logical preference file.

Devices affected: All FPGA devices

Double-click Edit Preferences (ASCII) in the Processes Window and make sure that UGROUPs that contain multiple logical components have the proper anchor and bbox set.

Floorplanner Loses LOCATE Preferences LOCATE preferences on blocks in the logical preference file are lost when a PGROUP is edited in the pre-map or post-map Floorplanner.

Devices affected: All FPGA devices

Double-click Edit Preferences (ASCII) in the Processes Window and manually add the LOCATE preferences again before running MAP.

Floorplanner Copies UGROUP/PGROUP from HDL to LPF When you save changes made in the pre-map or post-map Floorplanner, UGROUPs and PGROUPs defined in the HDL get written to the logical preference file.

Devices affected: All FPGA devices

Double-click Edit Preferences (ASCII) in the Processes Window and manually remove these UGROUPs and PGROUPs.

34 ispLEVER 5.1 Release Notes Known Issues and Solutions Floorplanner/Preference Editor

PIO PGROUP Dialog Box Does Not Save Bank Bank assignments added using the PIO PGROUP Dialog Box in the pre-map Preference Editor are not saved in the logical preference file.

Devices affected: All FPGA devices

In the Preference Editor, assign a Bank for each of the ports in the PGROUP using the Bank Column of the spreadsheet. You can also double-click Edit Preferences (ASCII) in the Processes Window and manually add a Bank preference to the PIO PGROUP. For example: LOCATE PGROUP "test" BANK 2 ;

Package View Does Not Create CSV The Preference Editor’s Package View fails to create CSV files.

Devices affected: ORCA® 4, LatticeECP/EC, LatticeXP, MachXO

Use the Preference Editor’s Spreadsheet Viewer to create CSV files. In the Spreadsheet Viewer, choose File > Export and then choose the type of file.

Pin Layout CSV Shows VCC, GND, VCCAUX, VCCPLL in Bank 0 In the pin layout CSV file, VCC, GND, VCCAUX, and VCCPLL pins are incorrectly associated with Bank 0.

Devices affected: LatticeECP/EC, LatticeXP, MachXO

You can edit the CSV file to delete the bank value.

Pin Layout CSV Shows VCC, GND, VCCAUX, VCCIO as Pin Names The pin layout CSV file may show VCC, GND, VCCAUX, and VCCIO as pin names.

Devices affected: LatticeXP, MachXO

You can edit the CSV file to delete the affected row.

ispLEVER 5.1 Release Notes 35 Floorplanner/Preference Editor Known Issues and Solutions

DRC in Package View Is Grayed Out The Design Rule Check (DRC) in the Package View is grayed out and unavailable.

Devices affected: All

Run DRC from the Floorplanner or the Preference Editor.

Floorplanner Opens With My Documents Folder When you click the Floorplanner button in the Project Navigator toolbar, the My Documents folder opens instead of the current project folder.

Devices affected: ORCA 4, ispXPGA, LatticeECP/EC, LatticeXP, MachXO

Open the Floorplanner from the Project Navigator's Processes pane by double-clicking one of the Floorplanner processes, such as Post-PAR Design Floorplan.

Stand-alone Floorplanner Does Not Open Database Design File The stand-alone Floorplanner does not open a pre-map database design file (.ngd).

Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO

There are two work-arounds for this issue:

Create the project in Project Navigator, import the source files, and then run the Pre-Map Logical Design Floorplan process.

Type the following command at the command prompt: flmainapp -inp ".ngd" -dir "" -prj "" -a -p -t -lpf ".lpf" -msg "Pre-Map Design Floorplan"

36 ispLEVER 5.1 Release Notes Known Issues and Solutions IPexpress and Module/IP Manager

Floorplanner/Preference Editor Triggers Firewall Message If you have a local software firewall on your machine and you try to invoke the Floorplanner or Preference Editor, you see a message stating that this program is attempting to access the Internet. This message is caused by the IPC (inter-process communication) function used in these applications and the way the local software firewall is configured.

Devices affected: LatticeECP/EC, LatticeXP, MachXO

Configure the firewall so that the following executables are granted access automatically: flmainapp.exe, flmainappw.exe, flmain_la.exe, prfEdit.exe, javaw.exe.

IPexpress and Module/IP Manager

Standalone Module/IP Manager Does Not Load LPC When Module/IP Manager is run in standalone mode (that is, without Project Navigator), it sometimes refuses to load an LPC, incorrectly giving the error message: You are loading a parameter file which targets a device family other than the current one. Program will not be able to load the parameter file.

Devices affected:ORCA 4, ispXPGA, all CPLD, ispGDX2

Run Module/IP Manager from the ispLEVER Project Navigator. Choose Tools > Module/IP Manager or click the Module/IP Manager button in the Project Navigator toolbar. In the Module/IP Manager window, choose File > Load LPC.

ispLEVER 5.1 Release Notes 37 ispLeverDSP Known Issues and Solutions

Cannot Import Module/IP Manager LPC Files Generated in 4.2 or 5.0 The Module/IP Manager Lattice Parameter Configuration (LPC) files generated in ispLEVER version 4.2 or 5.0 cannot be imported into ispLEVER 5.1 because the module parameters have changed.

Devices affected: LatticeECP/EC, LatticeXP, MachXO

Regenerate the module in ispLEVER 5.1 IPexpress. ispLeverDSP

False Undefined Property Warning If a preference is assigned to a DSP component, either in the preference file or RTL code, map may issue a spurious warning message: WARNING - map: :property is undefined and will be ignored.

Map still writes the preference to the .prf file and par honors the constraint.