ispLEVER 5.1 Release Notes Technical Support Line 1-800-LATTICE (528-8423) or 503-268-8001 Web Update To view the most current version of this document, go to www.latticesemi.com/software. November 2005 Copyright Copyright © 2005 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation. 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LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. ii ispLEVER 5.1 Release Notes Contents Chapter 1 New Features and Enhancements 1 Importing Existing Projects into ispLEVER 5.1 2 New Device Support 2 Preference Flow Enhancement for FPGA Designs 3 FPGA Preference Editor 4 More Flexible Display 4 PLL Attributes Setting 5 New Option for PERIOD and FREQUENCY Preferences 5 Vref Setting Dialog Box 7 Pin Layout Report 7 New IPexpress Tool for FPGAs 8 Project Navigator 10 News Panel 10 Target Device Detection When Importing LPC Modules 11 Net Attributes Editing 11 Creating HDL Templates from Schematic Symbols 11 Map, Place & Route Performance Improvements 11 Equation Report for MachXO 14 Place & Route Report Clock Summary 15 I/O Timing Report 16 Memory Initialization 16 Retiming Option 17 ispLEVER 5.1 Release Notes iii Contents Timing Preference Auto Generation 17 New Examples 17 MATLAB/Simulink 18 Two New Blocks 18 Simulink Support for Additional FPGAs 18 Debug - Signal Probe 18 Other ispLeverDSP Enhancements 18 Power Calculator 19 Frequency Settings Dialog Box 19 Simulators 20 NC-Verilog and VCS 20 ModelSim 6.1a 20 Synthesis 21 Synthesis Tool Upgrades 21 Properties for Synplify Synthesis Process 21 Precision RTL Synthesis Replaces LeonardoSpectrum 22 FPGA Performance Analyst 22 ispTRACY 23 IPexpress Generates ispTRACY Cores 23 Sample After Trigger Option 24 New Settings for TRST and ispEN/BSCAN Pins 24 Moving the Signal Display Left or Right 25 Logic Analysis on Multiple Devices Supported 25 ispVM System 25 Version 15.4 25 Version 15.3 26 CPLD and SPLD 28 New Modules in Module/IP Manager 28 ispMACH 4000 New Constraints 28 Slack Report in Performance Analyst 28 New Option for ispXPLD in Location Assignment Dialog Box 29 Documentation and Online Help 30 Quick Start Guide 30 New Tutorials 30 Simulating Designs for Lattice FPGA Devices 31 Enhanced Online Help, Search, and Index 31 FPGA Design Guide 32 Chapter 2 Known Issues and Solutions 33 Power Calculator 33 Standalone Power Calculator Fails to Open a New Project 33 Floorplanner/Preference Editor 34 iv ispLEVER 5.1 Release Notes Contents Floorplanner Loses Anchor Point and BBOX 34 Floorplanner Loses LOCATE Preferences 34 Floorplanner Copies UGROUP/PGROUP from HDL to LPF 34 PIO PGROUP Dialog Box Does Not Save Bank 35 Package View Does Not Create CSV 35 Pin Layout CSV Shows VCC, GND, VCCAUX, VCCPLL in Bank 0 35 Pin Layout CSV Shows VCC, GND, VCCAUX, VCCIO as Pin Names 35 DRC in Package View Is Grayed Out 36 Floorplanner Opens With My Documents Folder 36 Stand-alone Floorplanner Does Not Open Database Design File 36 Floorplanner/Preference Editor Triggers Firewall Message 37 IPexpress and Module/IP Manager 37 Standalone Module/IP Manager Does Not Load LPC 37 Cannot Import Module/IP Manager LPC Files Generated in 4.2 or 5.0 38 ispLeverDSP 38 False Undefined Property Warning 38 RAM/ROM Blocks Cannot Support Data Greater Than 64 Bits 38 MATLAB Sees Algebraic Loop with RAM Blocks 39 Dual-Port RAM with Different Data Widths Have Same Data Rate 39 Parallel-to-Serial, Serial-to-Parallel Clock Enable from Testbench 39 Parameter Names of EBR and Distributed RAM/ROM Changed 40 Input Ports of EBR RAM/ROM and Distributed RAM/ROM Changed 40 FFT and FIR Compiler Do Not Work 40 Some DSP Elements Are Not Supported in Non-DSP FPGAs 41 Simulation Mismatch When Downsample Drives Parallel-to-Serial 41 Output of FIR Filter Incorrect for Four-Multiplier Design 41 FIR Filter Simulink Block Does Not Support Saturation Logic 41 Limit on Interpolation Factor 42 Map Design Process 42 DRC Errors for Sub-module Connectivity Problems 42 Rerunning Map Design Produces Warnings About IOBUF 42 Place and Route Design Process 43 DQS Bus Assignment Fails 43 PAR May Violate PGROUP BBOX Specifications 43 Synthesis 43 Design Fixed In a Previous Version Fails In This Version 43 Project Path with Space Causes m_att.exe Error 44 Mapping Fails with Exit Code 0002 44 Digital Line Detect Error with Synplify Synthesis 45 Attributes preserve_driver and preserve_signal Fail 45 Lattice and Actel OEM Versions of Synplify Licenses Conflict 45 I/O Assistant Flow Does Not Work with Precision RTL Synthesis 46 ispTRACY 47 ispLEVER 5.1 Release Notes v Contents ispTRACY Core Requires Synplify Synthesis Tool 47 Unsupported VHDL and Verilog Features in ispTRACY IP Manager 47 Connecting VHDL Signals to ispTRACY Core 48 ispTRACY Requires ispVM to Run from Starter 48 Generate Bitstream Data (bitgen) 48 SPI Option for CONFIG_MODE Not Recognized 48 SPI Flash Memory Fails to Boot FPGA 49 Examples 49 FIFO and FIFO_DC Examples Fail in Functional Simulation 49 Documentation 50 Synthesis Data Flow Tutorial Place-and-Route Does Not Complete 50 vi ispLEVER 5.1 Release Notes 1 New Features and Enhancements Version 5.1 of the ispLEVER® design tools adds several new features and a broad variety of enhancements to make designing for Lattice Semiconductor programmable devices easier than ever. The design tools also include support for the latest Lattice Semiconductor devices. Major changes include the handling of preferences in FPGA designs. You can modify preferences at any stage of the design, using the editing tools to their fullest extent. For FPGA designs, IPexpress replaces Module/IP Manager. In addition to generating modules, IPexpress includes the infrastructure that allows you to try out ispLeverCORE products as cores supporting this flow are released. The Map Design, Place & Route Design, and I/O Placement processes have better performance. Several new properties give you more control. To provide better focused information and faster access, the online help is now organized by device type. Some of the changes affect how you import designs from previous versions of ispLEVER. For more information, see “Importing Existing Projects into ispLEVER 5.1” on page 2. For updates to this software and documentation, run ispUPDATE. Choose ispUPDATE from the Lattice Semiconductor program group in the Windows Start menu. ispLEVER 5.1 Release Notes 1 Importing Existing Projects into ispLEVER 5.1 New Features and Enhancements Importing Existing Projects into ispLEVER 5.1 Below are some important points for migrating designs from prior versions of ispLEVER into version 5.1: Once you import a design into version 5.1 of the ispLEVER system, you cannot reopen the design in the previous version. In case you need to work with the design in the previous version, make a copy of the design before importing it. With version 5.1, ispLEVER’s handling of preferences is greatly improved. Part of the improvement is the use of two preference files instead of one: the previous Physical Preference File (PRF) and a new Logical Preference File (LPF). For more information about the new preference flow, see “Preference Flow Enhancement for FPGA Designs” on page 3. When you open an existing project in the new Project Navigator, you see a prompt message stating that the current version of ispLEVER requires an LPF. Click Yes. The software copies the logical preferences from the existing PRF to a new LPF. It also makes a backup copy of the PRF named <project>.pr5. Then you can continue to design and run your project in ispLEVER 5.1.