Downconverter for the Meteosat Satellite System

Faculdade de Engenharia da Universidade do Porto EEC5170 – Electronics of Telecommunications

Design, Implementation and Test of the Low-noise Amplifier

Submitted by: Pedro Filipe Pereira Correia Pinto Pedro Manuel Martins Marques Rui Lopes Campos

July 2002 2

Contents

CONTENTS...... 2 LIST OF FIGURES ...... 3 LIST OF TABLES ...... 4 ABSTRACT ...... 5 1. INTRODUCTION...... 5 2. AMPLIFICATION STAGES AND DC BIASING CIRCUIT ...... 6 2.1 THEORY...... 6 2.1.1 Stability...... 6 2.1.2 Amplifier design (gain and noise figure)...... 8 2.1.2.1 Design for maximum gain...... 8 2.1.2.2 Design for specific gain...... 10 2.1.2.3 Design for specific noise figure ...... 10 2.2 DESIGN SPECIFICATIONS...... 11 2.2.1 General specifications...... 11 2.2.2 First stage...... 11 2.2.3 Second and third stages...... 12 2.2.4 PCB microwave laminates ...... 12 2.3 DESCRIPTION OF THE DESIGN PROCESS ...... 12 2.3.1 Stability analysis ...... 14 2.3.1.1 K-∆ test...... 14 2.3.1.2 Test using the µ-parameter...... 14 2.3.2 First attempt: design for maximum gain...... 15 2.3.3 Second attempt: design for minimum noise figure...... 17 2.3.4 Third attempt: design using lumped elements...... 18 2.4 DC BIASING CIRCUIT ...... 21 2.5 ELECTRICAL CIRCUIT DESCRIPTION ...... 22 3. BANDPASS FILTER...... 23 3.1 PROTOTYPE DESIGN...... 25 3.2 PROTOTYPE CIRCUIT...... 27 3.3 MICROSTRIP IMPLEMENTATION ...... 30 3.4 COUPLED LINE EQUIVALENT CIRCUIT ...... 31 3.5 EM SIMULATION...... 35 3.6 HAIRPIN DESIGN ...... 38 3.7 PCB FILTER TESTS...... 44 3.7.1 Why the differences? ...... 45 4. THE PCB LAYOUT ...... 46 4.1 THE PCB LAMINATE...... 46 4.2 COMPONENT PLACING AND LAYOUT DETAILS...... 46 4.2.1 Low-noise GaAs FET ...... 47 4.2.2 Monolithic amplifiers ...... 47 4.2.3 Bandpass filter...... 47 4.2.4 DC biasing circuit ...... 47 5. LNA ASSEMBLY, TEST AND MODIFICATION ...... 48 3

6. NETWORK ANALYSER MEASUREMENTS ...... 48 7. CONCLUSIONS...... 50 REFERENCES...... 51 APPENDIX A - LNA ELECTRICAL CIRCUIT SCHEMATICS...... 52 APPENDIX B - PCB LAYOUT SCHEMATICS ...... 54 APPENDIX C - COMPLETE LIST OF LNA COMPONENTS ...... 56 APPENDIX D - LNA PHOTOS...... 57

List of Figures

FIGURE 1 - CONCEPTUAL STRUCTURE OF THE LNA...... 5 FIGURE 2 - BLOCK DIAGRAM OF THE TRANSISTOR AMPLIFIER...... 7 FIGURE 3 - RF CIRCUIT (DESIGN FOR MAXIMUM GAIN)...... 16 FIGURE 4 - RF CIRCUIT (DESIGN FOR MINIMUM NOISE FIGURE)...... 18 FIGURE 5 - RF CIRCUIT (DESIGN USING LUMPED ELEMENTS)...... 19 FIGURE 6 - S-PARAMETERS FOR THE CIRCUIT OF FIGURE 7, OBTAINED WITH VIPEC...... 19 FIGURE 8 - DRAIN BIAS CIRCUIT...... 21 FIGURE 9 - DOWNCONVERTER OPERATION WITHOUT FILTERING...... 23 FIGURE 10 - DOWNCONVERTER OPERATION, WITH RF FILTERING...... 24 FIGURE 11 - LOW NOISE AMPLIFIER WITH INTEGRATED BANDPASS FILTER...... 24 FIGURE 12 - FILTER DESIGN BY THE INSERTION LOSS METHOD...... 25 FIGURE 13 - ATTENUATION CHARACTERISTICS FOR THE CHEBYSHEV FILTER: A) 0.5DB RIPPLE; B) 3DB RIPPLE...... 26 FIGURE 14 - LADDER CIRCUIT FOR LOW PASS PROTOTYPE DESIGN...... 27 FIGURE 15 - SIMULATED FREQUENCY RESPONSE FOR THE BANDPASS LC NETWORK...... 29 FIGURE 16 - SIMULATED LC NETWORK...... 30 FIGURE 17 - EQUIVALENT CIRCUIT FOR THE SERIES-PARALLEL LC NETWORK...... 31 FIGURE 18 - COUPLED LINE EQUIVALENT CIRCUIT...... 31 FIGURE 19 - EQUIVALENT CIRCUIT OF THE LC RESONATOR NETWORK OF FIGURE 16...... 31 FIGURE 20 - PARALLEL COUPLED LINE...... 32 FIGURE 21 - BANDPASS FILTER, WITH EDGE-COUPLED RESONATORS (N=3)...... 33 FIGURE 22 - SIMULATED FREQUENCY RESPONSE FOR THE PARALLEL COUPLED BANDPASS FILTER...... 34 FIGURE 23 - COUPLED LINE WIDTH AND SEPARATION CURVES, AS A FUNCTION OF THE IMMITANCE INVERTERS NORMALIZED ADMITTANCE (J'). J’ IS PROPORTIONAL TO ∆, AND CONSEQUENTLY, TO THE BANDWIDTH. FROM THIS FIGURE WE CONCLUDE THAT TO INCREASE THE BANDWIDTH WE MUST REDUCE W AND S, INCREASING THE COUPLING BETWEEN LINES. WE ALSO SEE THAT A DECREASE IN W MUST BE ACCOMPANIED BY A DECREASE IN S AND VICE-VERSA...... 35 FIGURE 24 - 2D MODELLER FILTER LAYOUT...... 36 FIGURE 25 - SCATTERING PARAMETERS EM SIMULATION RESULT FOR THE COUPLED LINE FILTER...... 36 FIGURE 26 - VSWR EM SIMULATION RESULT FOR THE COUPLED LINE FILTER...... 37 FIGURE 27 - ANSOFT SERENADE SCHEMATIC OF THE FILTER...... 37 FIGURE 28 - ANSOFT SERENADE SIMULATION RESULT...... 38 FIGURE 29 - GENERIC EDGE (PARALLEL) COUPLED FILTER...... 39 FIGURE 30 - PARALLEL COUPLED FILTER AFTER INTRODUCING A SLIDING FACTOR...... 39 4

FIGURE 31 - MATLAB SCRIPT FOR FILTER CALCULATIONS...... 39 FIGURE 32 - HAIRPIN RESONATOR STRUCTURE...... 40 FIGURE 33 - HAIRPIN RESONATOR FILTER WITH MATCHING STUB...... 40 FIGURE 34 - 2D MODELLER HAIRPIN BANDPASS FILTER LAYOUT, WITH ADDED DIMENSIONS. ... 42 FIGURE 35 - SIMULATED FREQUENCY RESPONSE OF THE PROJECTED HAIRPIN FILTER...... 42 FIGURE 36 - SMITH CHART RESPONSE OF S11. WE SHOULD NOTICE THE NON-SIMETRY OF THE RESPONSE IN RELATION TO THE AXES...... 43 FIGURE 37 - HAIRPIN FILTER CHARACTERISTICS MEASURED FROM THE EM SIMULATED RESPONSES...... 43 FIGURE 38 - FREQUENCY RESPONSE OF FABRICATED FILTER (FOR A DIFFERENT DIELECTRIC → H = 0.381MM)...... 44 FIGURE 39 - HAIRPIN FILTER CHARACTERISTICS MEASURED FROM THE NETWORK ANALYSER (DIFFERENT PCB → H = 0.381MM)...... 45 FIGURE 40 – LAYOUT FOR MICROSTRIP IMPLEMENTATION OF THE LNA (NOT IN ACTUAL SIZE).46 FIGURE 41 – THE S-PARAMETERS OF THE LNA AS A FUNCTION OF FREQUENCY, OBTAINED WITH THE NETWORK ANALYSER...... 49 FIGURE 42 – DATA FOR OVERALL NOISE FIGURE CALCULATION. THE NOISE FIGURES OF THE MONOLITHIC AMPLIFIERS WERE TAKEN FROM THEIR DATASHEETS. THE GAINS OF 16DB (FIRST AMP) AND 15DB (SECOND AMP) ARE LOWER THAN THOSE FOUND ON THEIR DATASHEETS (19DB FOR BOTH), DUE TO IMPEDANCE MISMATCHES...... 50 FIGURE 43 – ELECTRICAL CIRCUIT OF THE LNA (INITIAL VERSION)...... 52 FIGURE 44 – ELECTRICAL CIRCUIT OF THE LNA (FINAL VERSION, AFTER THE LAST-HOUR MODIFICATIONS)...... 53 FIGURE 45 – LAYOUT FOR MICROSTRIP IMPLEMENTATION OF THE LNA (INITIAL VERSION, 200% SCALE)...... 54 FIGURE 46 – LAYOUT FOR MICROSTRIP IMPLEMENTATION OF THE LNA, AFTER THE LAST-HOUR MODIFICATIONS (200% SCALE). THE INTERMMEDIATE REGULATOR HAS BEEN REMOVED. THE LAYOUTS FOR THE FET STAGE, DC/DC CONVERTER AND LAST MONOLITHIC AMPLIFIER REMAIN, BUT ARE NOT USED (OR, AT LEAST, IN THE WAY THEY WERE INTENDED TO…). THIS AVOIDED THE FABRICATION OF A NEW PCB, AND ALLOWED US TO REUSE THE ONE IN FIGURE 45...... 55 FIGURE 47 – THE LNA INSIDE ITS METAL BOX...... 57 FIGURE 48 – MEASUREMENTS USING THE NETWORK ANALYSER...... 57

List of Tables

TABLE 1 - GENERAL SPECIFICATIONS FOR LNA...... 11 TABLE 2 - AVAILABLE GAAS FET TRANSISTORS...... 11 TABLE 3 - AVAILABLE MMIC AMPLIFIERS...... 12 TABLE 4 - AVAILABLE LAMINATES...... 12 TABLE 5 - ATF-36077 TYPICAL S-PARAMETERS. THE SELECTED BIAS POINT IS

VDS = 1.5V, IDS = 10MA AND VGS =–0.2 V...... 13 TABLE 6 - ATF-36077 TYPICAL NOISE PARAMETERS...... 16

TABLE 7 - RECOMMENDED BIAS RESISTOR VALUES FOR ID = 80MA...... 22 TABLE 8 - ELEMENT VALUES FOR THE EQUAL-RIPPLE LOWPASS FILTER PROTOTYPE...... 28 TABLE 9 - LOWPASS → BANDPASS FILTER ELEMENT VALUES CONVERSIONS...... 29 TABLE 10 - EVEN AND ODD MODE IMPEDANCES FOR THE 3RD ORDER PARALLEL COUPLED FILTER...... 34 TABLE 11 - WIDTH AND SEPARATION VALUES FOR ELECTROMAGNETIC SIMULATION...... 35

Abstract The following technical report presents the work done on the design, simulation and test of a 1.7 GHz low-noise amplifier (LNA), which is intended to be the first stage of a Meteosat System downconverter.

1. Introduction

The purpose of this LNA is to amplify (and filter) the 1.691 GHz signal received from the Meteosat, while minimizing the amount of noise introduced by the several components. The LNA can be subdivided into the following blocks:

• a low-noise GaAs FET transistor in a common source configuration, with the associated matching circuits; • 2 monolithic amplifiers, with a bandpass filter in-between; • the DC biasing circuit.

This subdivision is illustrated in Figure 1.

Figure 1 - Conceptual structure of the LNA.

As a guideline to the design of the LNA, several specifications (concerning bandwidth, noise figure, input return loss, output return loss, and others) were taken into account. These specifications will be presented later in some detail. The first stage (low-noise FET) was designed using S-parameter techniques exclusively. It required the analysis of transistor stability and proper selection of the matching networks, in order to obtain a stable, low-noise performance, while ensuring an acceptable power gain. The critical parameter of this stage is precisely the noise figure. In fact, if the gain of the FET is large, the noise figure of the whole LNA (or even of the whole downconverter) is mainly determined by the transistor stage, since the contributions of the other devices to the overall noise figure are divided by the gain of the previous stages. It is also due to noise considerations that the LNA is to be mounted directly on the antenna horn feed, before the coaxial cable. If we had chosen to place the coaxial cable before the LNA, its loss would directly add to the overall noise figure of the system, thereby making the “low-noise” property of the amplifier useless. A list of two different low-noise transistors was considered, from which the GaAs FET ATF-36077 was selected (the other choice would be ATF-34143). The reasons that support this choice will be presented later.

The several attempts we made to successfully design the transistor stage are explained in the following sections. In each of these attempts, a simple and rough analysis was first made to provide a starting point for the design; this was then followed by a more accurate analysis performed using adequate simulation software (ViPEC and Serenade). These CAD packages allowed a better approximation to the real operation of the LNA, and sometimes gave results quite different from those that we were expecting based on “pencil and paper” calculations. After the first stage was designed, we proceeded onto the next stages, which were based on two monolithic amplifiers (MMIC). These devices were directly inserted into the RF path with adequate biasing, and required no matching circuitry. The monolithic amplifiers were chosen from a list of three different ones. After some analysis, our choice was the SGA- 6586, because of its desirable characteristics at the operating frequency, mainly in terms of gain and output return loss. All DC power was provided to the LNA via output coaxial line, using a bias-T configuration. Between monolithic amplifiers, a bandpass filter was inserted. This filter has a narrowband characteristic because its goal is to eliminate signals at all frequencies other than the operating frequency (specially the undesired signals at the image frequency). All the design steps and theory behind filter implementation are fully explained in later sections. Once implemented using microstrip technology, the individual components and the overall LNA system were tested using microwave measurement techniques. More specifically, S-parameter measurements were made using a vector network analyser. Due to some reasons explained further ahead, a few “last-hour” changes had to be made to the LNA, namely, the GaAs FET transistor was replaced by an SGA-4586 monolithic amplifier, and the two SGA-6586 monolithic amplifiers were replaced by two ERA-3SM. In the following sections of this report, the design steps of all the blocks depicted in Figure 1 will be presented. Furthermore, simulation results obtained with CAD software are included when appropriate. These results are also compared with those obtained from test measurements with the network analyser.

2. Amplification stages and DC biasing circuit

2.1 Theory

The first step in the design of a low-noise amplifier involves the analysis of the transistor in use. The selection of an appropriate operating bias point has a significant influence on the performance of the transistor amplifier. For the GaAs FET that we used, minimum noise figure is obtained at low drain current. In the transistor datasheets, the S-parameters are only given at one operating bias point (ID = 10 mA; VDS = 1.5 V), which we shall use throughout the rest of the design procedure.

2.1.1 Stability

Once a bias point is selected, S-parameters can be measured or obtained from the device’s datasheets, and used to analyse the stability of the transistor, which is a very important consideration in the design practice. The S-parameters of the device, the matching networks and the associated reflection coefficients are all used to determine the stability. Figure 2 shows a block diagram of a general amplifier circuit.

ГS Гin Гout ГL Figure 2 - Block diagram of the transistor amplifier.

The input and output reflection coefficients can be determined from:

S 21.S12.ΓL Γin = S11 + (2.1) 1− S 22.ΓL

S 21.S12.ΓS Γout = S 22 + (2.2) 1− S11.ΓS

In a two-port network, oscillations are possible when whether one or both ports present a negative resistance. This occurs when

| Γin |> 1 or | Γout |> 1 (2.3)

Since both Гin and Гout depend on the source and load matching circuits, the stability of the amplifier depends on ГS and ГL. We can distinguish between two different kinds of stability:

• Unconditional stability: the network is unconditionally stable if

S 21.S12.ΓL | Гin | = S11 + < 1 (2.4) 1− S 22.ΓL

S 21.S12.ΓS | Гout | = S 22 + < 1 (2.5) 1− S11.ΓS

for all passive values of ГL and ГS or, in other words, for

| ГS | < 1 (2.6)

| ГL | < 1 (2.7)

• Conditional stability: the network is conditionally stable if |Гin| and |Гout|<1 only for certain values of ГL and ГS.

It is important to note that the stability condition is frequency dependent. Thus, a transistor can be stable at a certain frequency, but it may be unstable at another one. Our purpose here is to verify whether the transistor in use is unconditionally stable or not, at the operating frequency. To accomplish this, we can use two tests: one is the K-∆ test and the other one is based on a single parameter – µ.

Tests for unconditional stability

The transistor will be unconditionally stable if both conditions (2.8) and (2.9) are satisfied: 2 2 2 1− S11 − S 22 + ∆ K = > 1 (2.8) 2.S12.S 21

∆ = S11.S 22 − S12.S 21 < 1 (2.9)

The other method involves only a single parameter, µ, defined as

2 1− S11 µ = > 1 (2.10) S 22 − ∆.S11 + S12.S 21

Thereby, the device is unconditionally stable if, and only if, µ> 1. Furthermore, larger values of µ imply greater stability. If a transistor is potentially unstable at the design frequency, resistive loading may be used to make it unconditionally stable.

2.1.2 Amplifier design (gain and noise figure)

Desired gain and noise performance may be achieved by the proper selection of the reflection coefficients for the input and output matching networks (depicted in Figure 2). As it is usually the case, it is impossible to simultaneously design the amplifier for maximum gain and minimum noise figure. Therefore, some sort of compromise must be made between these two parameters. This process is greatly simplified if we use the concept of constant gain circles and constant noise figure circles. Then, an appropriate combination of ГS and ГL can be chosen to satisfy the requirements in the best possible way.

2.1.2.1 Design for maximum gain

With the proper selection of ГS and ГL, it is possible to achieve maximum gain. Maximum power transfer from the input matching section to the transistor will occur when the following condition is satisfied:

Γin = ΓS (2.11)

, where Z is used to denote complex conjugation. The maximum power transfer from the transistor to the output matching section will occur if

Γout = ΓL (2.12)

If these two conditions are satisfied, the resulting transducer gain is 9

2 1 2 1− ΓL T max 21 G = 2 S 2 (2.13) 1− ΓS 1− S 22.ΓL

Hence, in this case, the following formulae can be used to relate ГS and ГL:

S12.S 21.ΓL ΓS = S11 + (2.14) 1− S 22.ΓL

S12.S 21.ΓS ΓL = S 22 + (2.15) 1− S11.ΓS

After some mathematical manipulation of (2.14) and (2.15), two equations which allow the computation of ГS and ГL can be derived:

2 2 B1 ± B1 − 4.C1 ΓS = (2.16) 2.C1

2 2 B2 ± B2 − 4.C2 (2.17) ΓL = 2.C2

, where B1, C1, B2 and C2 are defined as

2 2 2 B1 = 1+ S11 − S 22 − ∆

2 2 2 B2 = 1+ S 22 − S11 − ∆ (2.18) C1 = S11 − ∆.S 22

C 2 = S 22 − ∆.S11

S12 is often small enough to be ignored and the equations above become as simple as

ΓS = S11 (2.19)

ΓL = S 22 and the corresponding transducer gain is given by

1 2 1 TU max 21 G = 2 S 2 (2.20) 1− S11 1− S 22

Solutions to (2.16) and (2.17) are only possible if the quantity inside the square root is positive, which is equivalent to require that K > 1 (from the stability criteria presented previously). Therefore, unconditionally stable devices can always be designed for maximum gain, and potentially unstable devices may be conjugately matched only if K > 1.

2.1.2.2 Design for specific gain

The design for a specific gain increases the bandwidth, which is an advantage for some applications. It is also useful when a different gain other than the maximum is desired. This reduction of the overall gain is done by introducing impedance mismatches into the input and output ports. The design procedure is accomplished by plotting constant gain circles on the Smith Chart, representing loci of ГS and ГL that give fixed values of gain for the input and output sections (GS and GL). In several practical cases, S12 is so small that it can be neglected and the device can be considered unilateral. The error introduced by this approximation may be calculated by the ratio GT /GTU . This ratio is bounded by

1 GT 1 2 < < 2 (2.21) ()1+U GTU ()1−U

, where U is the unilateral figure of merit and is defined as

S11 S12 S 21 S 22 U = 2 2 (2.22) ()1− S11 .()1− S 22

Usually, an error of a few tenths of dB or less justifies the unilateral assumption. Design for a specific gain is not further developed here, since it was not used anyway in this project. It was only mentioned here because, as was said before, it may be useful for some applications to sacrifice the overall gain or noise figure of the amplifier to improve bandwidth. For a detailed explanation of this subject, see [1].

2.1.2.3 Design for specific noise figure

Besides stability and gain, another important design consideration is the noise figure. As mentioned, we usually have to use constant gain circles and circles of constant noise figure to select a usable trade-off between noise figure and gain. The noise figure of a two-port network is given by

RN 2 F = F min+ YS − Yopt (2.23) GS

The noise figure can also be written in terms of the reflection coefficients as

2 RN ΓS − Γopt min F = F + 4. 2 2 (2.24) Z 0 ()1− ΓS .1+ Γopt

, where the minimum noise figure is obtained when

ΓS = Γopt (2.25)

The quantities Fmin, Гopt, and RN are called the noise parameters of the transistor and are given in the device’s datasheet. 11

Formulae for the circles of constant noise figure are not included here, since they were not necessary to our work (see [1]). In fact, our main purpose is to have minimum noise figure for the first stage, not some other specific noise figure. The power gain is not so critical when compared to the noise figure, since the gain required by the design specifications is not difficult to get. The overall performance of a low-noise transistor amplifier may be evaluated through the computation of the transducer gain GT, noise figure F, and input and output return loss. The equations that govern these values were already given. However, pencil and paper calculations using these equations can become quite tedious. It is then useful to have some type of tool that performs rapid calculations and displays results graphically, in a simple way. With this purpose, ViPEC was used. It may not be the best tool available to accomplish the task of amplifier design, but it gives accurate values of most of the amplifier’s parameters with minimum effort. The use of this CAD tool certainly makes the design process less painful and increases the probability of success.

2.2 Design specifications

2.2.1 General specifications

Parameter Symbol Value Units min. typ. max. Frequency range [fL , fU] 1690 1696 - Gain G 27 30 dB Gain flatness ∆G - - 0.5 dB Input impedance Zin - 50 - Ω Output Zout - 50 - Ω impedance Input VSWR VSWR(in) - 1.2:1 - - Output VSWR VSWR(out) - 1.2:1 - - Noise figure - 0.7 1 dB RF connectors SMA or N(female) Supply voltage VDC 6 - 14 V Supply current IDC - 100 mA Estimated cost - 50 - Euro Table 1 - General specifications for LNA.

2.2.2 First stage

• Based on a low-noise GaAs FET transistor in a common source configuration. • A variable negative gate bias supply should be provided. • This stage should have no less than 10 dB of gain.

Manufacturer Model Type Cost Factor Agilent ATF-36077 GaAs Pseudomorphic HEMT 2.0 Agilent ATF-34143 GaAs Pseudomorphic HEMT 1.8 Table 2 - Available GaAs FET transistors. 12

2.2.3 Second and third stages

• Each one based on a monolithic amplifier integrated circuit (MMIC).

Manufacturer Model Process Cost Factor Sirenza SGA-4586 SiGe 2.7 Sirenza SGA-6586 SiGe 2.7 Mini-circuits ERA-3SM GaAs HJ Bipolar 1.3 Table 3 - Available MMIC amplifiers.

2.2.4 PCB microwave laminates

Specifications of the PCB laminate should be carefully chosen towards low dissipation factors substrates and low dielectric thickness (to minimize ground inductances).

Manufacturer Material εr Thickness tan(δ) Cost factor Rogers Corp. RT/Duroid 2.33 0.031’’ 0.0012 1.0 Rogers Corp. RT/Duroid 2.2 0.031’’ 0.0009 4.0 Rogers Corp. RT/Duroid 2.2 0.015’’ 0.0009 2.7 Table 4 - Available laminates.

2.3 Description of the design process

We can divide the several attempts to successfully design input and output matching sections that satisfy the specifications into two groups:

• Design using the methods already presented in section 2.1. Figure 2 is the starting point - in this schematic, the transistor is represented by its S-parameters, which are provided by the manufacturer or can be measured using the network analyser. Then, the S-parameters are used to compute ГL and ГS according to some specified criteria (desired gain or noise figure). Finally, transmission line sections and stubs of adequate length are used so that the transistor “sees” the calculated ГL and ГS. As will be shown, this design method proved itself to be unsuccessful, which lead us to another approach…

• Design using lumped elements, together with microstrip line sections, as matching devices. The values of the several components were iteratively adjusted using CAD software, until satisfying results were achieved.

This section deals mainly with the first stage (FET), since the other two amplification stages were based on MMIC amplifiers, which were put in the RF path (with the necessary biasing circuit) in order to increase the overall gain, without any further design complications. As mentioned, the ATF-36077 was chosen for the first stage (from the list of available transistors presented in Table 2), due to the very low-noise figure and good performance in terms of gain. Since our aim is to have minimum noise figure and reasonable gain, this transistor should provide us with means to satisfy the design specifications. Another desirable 13

property of this transistor is that S11 ≈ Γopt . This means, as we shall see, that we can simultaneously design for near-maximum gain and near-minimum noise figure. The S-parameters for (ID = 10 mA; VDS = 1.5 V) were taken directly from the device’s datasheet and examined. Table 5 presents the transistor S-parameters at the operating frequencies of 1 and 2 GHz. Making a linear interpolation between the values given in the table, it was possible to compute the S-parameters at the design frequency.

Common Source, Z0 = 50, VDS=1.5 V, ID=10 mA Freq. S11 S21 S12 S22 GHz Mag. Ang. Mag. Ang. Mag. Ang. Mag. Ang. 1.0 0.99 -17 5.010 163 0.016 78 0.60 -14 2.0 0.97 -33 4.904 147 0.030 66 0.59 -28 Table 5 - ATF-36077 typical S-parameters. The selected bias point is VDS = 1.5V, IDS = 10mA and VGS =–0.2 V.

S-parameters at the design frequency

By applying linear interpolation to the values given in Table 5, we can derive the following formulae for the S-parameters of the transistor, as a function of the operating frequency f (in GHz):

S11 = −0.02 f +1.01

∠S11 = −16 f −1°

S 21 = −0.106 f + 5.116

∠S 21 = −16 f +179 °

S12 = 0.014 f + 0.002

∠S12 = −12 f + 90 °

S 22 = −0.01f + 0.61

∠S12 = −14 f °

The signal to be received is centred at 1.691 GHz. Nevertheless, since the design specifications require a frequency range of [1.690, 1.696] GHz, a midway frequency of 1.693 GHz was chosen to perform the calculations. The above formulae with f = 1.693 GHz thus yields the desired S-parameters at the operating frequency:

S11 = 0.97∠ − 28.09°

S 21 = 4.94∠151.91°

S12 = 0.026∠69.68°

S 22 = 0.59∠ − 23.7°

2.3.1 Stability analysis

Before proceeding onto the design of the matching sections, some calculation was performed to determine the stability characteristics of the transistor in use. This is a very important step in the amplifier design.

2.3.1.1 K-∆ test

Using the formulae given in section 2.1.1:

2 2 2 1− S11 − S 22 + ∆ K = > 1 2.S12.S 21

∆ = S11.S 22 − S12.S 21 < 1

, we conclude that

1− 0.97 2 − 0.592 + 0.5792 K = ⇔ K = 0.18 2.()()4.94∠151.91° . 0.026∠69.68°

∆ = ()0.97∠ − 28.09° .(0.59∠ − 23.70°)− (4.94∠151.91°).(0.026∠69.68°) ⇔ ∆ = 0.579

2.3.1.2 Test using the µ-parameter

Using the other method presented before, with

2 1− S11 µ = SSSS22−∆.. 11 + 12 21

, we obtain

1 − 0.97 2 µ = ()()()0.59∠ − 23.70° − 0.579∠ − 39° . 0.97∠28.09° + ()()0.026∠69.68° . 4.94∠151.91° ⇔ µ = 0.228

Both the stability tests indicate that the ATF-36077 transistor is conditionally stable at the operating frequency. Furthermore, the value obtained for the µ parameter (well below unity) suggests that this transistor is also far from unconditionally stability. This is not a major problem, because resistive loading can be used to avoid instability at design frequency.

2.3.2 First attempt: design for maximum gain

As seen in section 2.1, two conditions must be satisfied in this case:

Γin = ΓS

Γout = ΓL

, where ΓS and ΓL are given by

S12.S 21.ΓL ΓS = S11 + 1− S 22.ΓL

S12.S 21.ΓS ΓL = S 22 + 1− S11.ΓS

For the unilateral case (S12 = 0), we have

ΓS = S11

ΓL = S 22

The error in transducer gain due to this approximation can then be calculated:

S11 S12 S 21 S 22 U= 2 2 = 1.908 ()1− S11 .()1− S 22

1 GT 1 2 < < 2 ()1+U GTU ()1−U

GT ⇔ 0.118 < < 1.213 GTU

GT ⇔ −9.3dB < < 0.839dB GTU

We therefore conclude that the unilateral approximation is not very accurate in this particular situation. Nevertheless, for simplicity of design, the unilateral case was assumed (the validity of this assumption could later be confirmed using CAD software). Thus, we have:

ΓS = S11 = 0.97∠28.09°

ΓL = S 22 = 0.59∠23.70°

Using microstrip lines as matching networks, the following lengths for input and output matching stubs were obtained from the Smith Chart:

Input matching circuit

Line section length = 0.268λ - 0.038λ = 0.23λ Stub length = 0.232λ (open-circuited stub)

Output matching circuit

Line section length = 0.324λ - 0.033λ = 0.291λ Stub length = 0.156λ (open-circuited stub)

To obtain the values presented above, ΓS and ΓL for input and output sections were represented on the Smith Chart. After converting them to admittances, a rotation was made toward the load until it intercepted the unit circle. At this point, the stub susceptance (and therefore its length) could be read in the chart, as well as the line section length. Figure 3 shows the resulting RF circuit, with the values next to the stubs representing fractions of the wavelength.

Figure 3 - RF circuit (design for maximum gain).

The expected transducer gain, assuming S12 = 0 (unilateral approximation), is

1 2 1 TU max 21 G = 2 S 2 = 633.41≈ 28dB 1− S11 1− S 22

To obtain Fmin, Гopt, and RN at the design frequency, linear interpolation was also used. Table 6 (taken from the datasheet of the device) shows the values for these parameters, but only at f = 1.0 and 2.0 GHz.

Freq. Fmin Γopt RN / Z0 GHz dB Mag. Ang. 1.0 0.30 0.95 12 0.40 2.0 0.30 0.90 25 0.20 Table 6 - ATF-36077 typical noise parameters.

For f = 1.693 GHz, it was found that

RN = 0.26 Z 0

F min = 1.072

Γopt = 0.915∠21°

Equation (2.24) can be used to determine the noise figure of the two-port network:

F = 1.154

F = 10log(1.154) ≈ 0.62dB

With this design approach, it was possible to have maximum gain and achieve an excellent noise figure, below the typical value of 0.7dB referred in the design specifications. Although these values obtained with “pencil and paper” calculations were apparently quite satisfactory, the simulation results given by ViPEC were not so good – some crucial parameters such as the input and output return loss were unacceptable. Some fine-tuning was then made, but we were not able to make significant improvements in the amplifier performance. Due to these bad simulation results, we then tried the design for minimum noise figure before taking any conclusions…

2.3.3 Second attempt: design for minimum noise figure

To achieve minimum noise figure, the following condition must be met:

ΓS = Γopt

For f = 1.693 GHz,

Γopt = 0.915∠21°

So, ΓS = 0.915∠21°

Using the Smith Chart and following the same procedure described in the previous section, we calculated the stub and line section lengths for the input matching circuit:

Line section length = 0.25λ Stub length = 0.218λ (open-circuited stub)

The ΓL of the output matching section was selected to yield maximum power transfer:

Γout = ΓL

S12.S 21.ΓS ΓL = S 22 + 1− S11.ΓS 18

Assuming unilateral amplifier (i.e. S12 = 0),

ΓL = S 22 = 0.59∠23.7°

Then, for the output matching circuit, we have:

Line section length = 0.188λ Stub length = 0.139λ (open-circuited stub)

Figure 4 shows the resulting RF circuit, with the values next to the stubs representing fractions of the wavelength.

Figure 4 - RF circuit (design for minimum noise figure).

The expected value for the transducer gain, considering S12 = 0 (unilateral assumption), is a few dBs below the maximum achievable gain of 28dB:

22 11−ΓSL2 −Γ TU 21 GS==≈22232.06 24 dB 11−ΓSS11SL −Γ 22

Since in this case we designed for minimum noise figure, the noise figure is given by:

F = F min = 1.072 ≈ 0.3dB

In this second design attempt, it was possible to obtain minimum noise figure (0.3dB). The resulting gain is not significantly lower than the maximum transducer gain, mainly because S11 ≈ Γopt at the operating frequency (this was, in fact, one of the reasons for choosing this specific transistor). However, as already happened previously with the first design attempt, unacceptable values for the input and output return loss were obtained using ViPEC. This is in fact a problem with the design method itself – the method described in section 2.1 (taken from [1]) allows us to set the noise figure and gain, but doesn’t give us any control over the input and output reflection coefficients (seen from the 50 Ω ports). The solution we found was to use lumped elements and stubs as matching networks, as described next…

2.3.4 Third attempt: design using lumped elements

Since the previous attempts were not successful, we exploited a different design method based on the introduction of lumped elements into the matching networks. To use this method 19 correctly, we analysed some related projects that used a similar technique to obtain good results (see [8]). As Figure 5 shows, the first difference between this and previous designs is the placement of a resistive load in the output matching network, in series with the drain. This has the advantage of solving all the stability problems. A disadvantage is the decreased power gain, due to the loss of output power in the resistive load. Another disadvantage could be the introduction of thermal noise by the resistive load, but its contribution to the overall noise figure is negligible (since it is divided by the gain of the first stage). Besides the use of a resistance, microstrip line sections that were present in previous designs were replaced by lumped elements (inductances), which revealed themselves very useful to achieve good performance in the overall system. A parallel open-circuited stub placed at the output port was also found to be beneficial. To adjust the values of all the matching components, CAD tools (ViPEC and Serenade) were used. The initial values of the inductances and drain resistance were chosen based on typical values used in some other related LNA projects. Beyond this point, adjustments were made until an acceptable power gain was obtained (from port 1 to 2 in Figure 5), together with the lowest possible input and output reflection coefficients (seen from port 1 and 2, respectively). The final circuit is depicted in Figure 5, where stub lengths are expressed as fractions of the wavelength.

Figure 5 - RF circuit (design using lumped elements).

Figure 6 shows the frequency dependence of all the four S-parameters of the above circuit. These were obtained with ViPEC, between the 50 Ω ports (1 and 2).

Figure 6 - S-parameters for the circuit of Figure 7, obtained with ViPEC. 20

At f = 1.693 GHz, we have (from Figure 6):

S11 = −14.7dB

S 22 = −4.0dB

S 21 =18.4dB

S12 = −27.0dB

These S-parameters are quite satisfactory, and do not violate any of the design specifications concerning gain and input return loss. The noise figure of the circuit can be calculated as follows.

Noise figure (estimate for the circuit presented in Figure 5):

2 RN ΓS − Γopt min F = F + 4 2 2 Z 0 ()1− ΓS .1+ Γopt

ZS − Z 0 Γ=S ZS + Z 0

ZS =+ZjL0 ω

, where

L = 14.95nH ω = 2π ×1.693GHz ≈ 10.64×109 rad / s

Thus, ZjS =+50 159( Ω )

ΓS is given by

50 + j159 − 50 ΓS = = 0.846∠32° 50 + j159 + 50

and Γopt is given by

Γopt = 0.915∠21°

Having found ΓS and Γopt, it is possible to estimate the noise figure for first stage (FET), which is approximately equal to the noise figure of the overall LNA:

0.846∠32° − 0.915∠21° 2 F = 1.072 + 0.26× 4 = 1.106 ()1− 0.8462 .1+ 0.915∠21° 2

F = 10log(1.106) ≈ 0.44dB 21

From this value, we conclude that the noise performance of this stage is excellent and fully satisfies the design specifications. Due to its good input return loss, power gain and noise figure characteristics, this circuit was adopted to be the final one, and is used throughout the following sections. An important thing to be noted is that the value for the output return loss (or equivalently, the S22) is actually not that good. However, this doesn’t influence the overall performance, because the value to be guaranteed is the output return loss of the overall amplifier, and not the output return loss of the first stage.

2.4 DC biasing circuit

The chosen DC bias circuit should exhibit stable thermal performance and ensure a small size for the overall LNA. The following devices were selected to make part of the DC biasing circuit:

• a low dropout regulator (LM2940), used to stabilize the output voltage provided to other bias stages. It accepts +12V at its input (supplied via the output port of the LNA) and produces +9V at its output;

• an intermediate regulator, which accepts +9V and produces +5V at its output. This additional regulator is not essential at all, but improves voltage regulation for the subsequent devices;

• a DC/DC converter (MAX 840), which provides a negative voltage to the gate of the transistor. It converts the +5V coming out of the intermediate voltage regulator to –2V.

The complete electrical circuit of the LNA, with the biasing circuit included, is given in Appendix A (Figure 43). To have –0.2 V applied to the transistor gate, a voltage divider was placed after the DC/DC converter. This divider consists of a resistor and a potentiometer, which allows gate voltage adjustments; typical values were chosen for these two components (see electrical circuit schematic).

100 1.5 V V

+5V

Figure 8 - Drain bias circuit. 22

The drain of the transistor was biased with ID=10mA and VDS=1.5V, using the configuration illustrated in Figure 8. Since the drain current is fixed by the gate voltage, the values for resistors R4 and R5 can be determined as follows:

V = 1.5 +100.10mA = 2.5V

(R4 + R5).10mA = 2.5V ⇒ R4 + R5 = 250Ω

We may therefore choose:

R4 = 100Ω

R5 = 150Ω

For the two monolithic amplifiers, bias resistor values were determined from the recommendations given in the device’s datasheets. Table 7 presents some supply voltages and the corresponding bias resistor values:

Supply voltage (V) 6V 8V 10V 12V RBIAS 13Ω 39Ω 62Ω 91Ω

Table 7 - Recommended bias resistor values for ID = 80mA.

Since the two monolithic amplifiers are fed with +9V, we can use the resistor values given for 8V and 10V to make a linear interpolation and thus calculate the bias resistor value corresponding to a 9V power supply:

RBIAS = 50.5Ω ≈ 51Ω

In the actual LNA circuit, this resistance value is obtained by associating two series resistances. Finally, it is important to refer that the supply voltage (+12V) is provided directly via the coaxial line connected to the output of the LNA. For this purpose, the bias-T configuration depicted in the right side of the circuit schematic is used. A bias-T consists of two lumped elements – an inductance and a capacitor – which allow isolation between RF and DC signals. The RF signal passes through the capacitor and is blocked by the inductance, while the DC signal passes through the inductance and is blocked by the capacitor. Hence, this is a very flexible way of feeding the whole circuit, avoiding the inconvenience of having a dedicated power source for the purpose placed nearby the LNA. Some other components with important functions in the system are also part of the LNA electrical circuit. Next, they are described in some detail.

2.5 Electrical circuit description

The capacitors used with MAX840 and LM2940 are essential for proper performance of these components. Their values were chosen based on those suggested by the device’s datasheets. Some capacitors were also placed where appropriate in the RF path to block DC, thus avoiding possible damage of the monolithic amplifiers.

Also note the use of λ / 4 microstrip line sections to bias all the amplification stages. These lines present a high impedance to the RF circuit, by transforming a short-circuit into an open-circuit at the operating frequency. Hence, they provide isolation between DC bias circuit and RF path. To ensure a perfect short-circuit at the end of these lines, two capacitors connected to the ground plane where used; their values were chosen based on the ones found in other related projects. At the RF input, a λ / 4 microstrip line section was connected directly to the ground plane. It allows deviation (to the ground) of the out-of-band signals that could saturate the input transistor. At the design frequency, this line section presents a high impedance to the RF path and therefore has no influence in circuit performance. Finally, a LED was employed to indicate whether the LNA is ON or OFF.

3. Bandpass filter

The Meteosat 7 Satellite transmits Wefax data on two channels: 1691MHz and 1694.5MHz. After the RF signal has been captured by the antenna and conveniently amplified by both the Low Noise HEMT and one Monolithic Amplifier, the signal should be fed to the downconverter. The downconverter will then output the desired high frequency band in a low frequency band (IF band – 137MHz), ready to be supplied to a local demodulator (the VHF receiver). The problem that arises is that besides producing harmonics, the downconverter (mixer), outputs the superposition of two high frequency bands: the RF band and the Image frequency band. This is shown on Figure 9.

Figure 9 - Downconverter operation without filtering.

This kind of behaviour is not allowable because the RF signal would be damaged by the Image signal. To avoid this we can implement a system that rejects the Image frequency, accepting and outputting only the RF frequency: a bandpass filter. The result is shown on Figure 10.

Figure 10 - Downconverter operation, with RF filtering.

This type of filtering is called ideal because it perfectly selects the desired band, not allowing any more frequency components to travel to the output and providing no attenuation to the selected band. Of course, this is physically impossible to obtain, especially if we want a filtering process with high selectivity (e.g. high RF frequency and narrow bandwidths). For the time being we can establish our goals for the filter characteristics:

a. Centre frequency: f0 = 1693MHz ; b. 3dB Bandwidth: B ≈ 80MHz ; c. Attenuation at f : A > 50dB ; Im fIm d. Attenuation at f : A < 2dB ; 0 f0

The block diagram of the LNA should now look something similar to the one shown on Figure 11.

Figure 11 - Low noise amplifier with integrated bandpass filter.

As already mentioned, the filter is not perfect. It has a positive Insertion Loss (IL) (and not infinite Return Loss) in the passband and a positive Return Loss (RL) (and not infinite Insertion Loss) out of the passband. In addition to amplifying the RF signal, the first Monolithic Amplifier acts somewhat like an isolator, rejecting the signal reflected from the filter. The second one compensates for the positive IL on the passband. 25

The first amplification stage (HEMT + Amp.) also greatly reduces the poor noise figure characteristic of the Bandpass filter. Assuming that the system is operating at temperature T0 = 290K, the noise figure of the filter equals its passband attenuation: FALG == = 1/ . The overall system noise figure will then be given filt f0 filt filt approximately by:

LFfilt−11 amp − Fmixer −1 FFoverall=+ HEMT+ amp + + (3.1) GGGGGGHEMT++ amp HEMT amp filt HEMT + amp filt amp

As GHEMT+ amp is significantly large, the attenuation introduced by the filter is meaningless, so the noise figure of the global system doesn’t deteriorate and becomes:

FFoverall≈ HEMT+ amp (3.2)

There are many technologies available for the implementation of RF and microwave filters in the frequency range from 800MHz to about 4GHz. These include filters made with dielectric resonators, quartz crystals or even surface acoustic waves (SAW). These types of filters have a very high Q and small size, but are often more expensive. For wireless systems without stringent requirements, bandpass filters are often made with simple LC networks, transmission lines or parallel coupled lines, but require relatively small bandwidths (<20%).

3.1 Prototype design

There are several techniques for filter design, but possibly the preferred one is the insertion loss method. This process is shown on Figure 12.

Figure 12 - Filter design by the insertion loss method.

There are various low-pass prototypes defined, including Maximally Flat (Butterworth), Equal-ripple (Chebyshev), Elliptic, etc. These filters are completely defined by a polynomial that describes the power loss ratio variation with frequency, or in other words, the attenuation in the frequency domain. For example, for the Chebyshev filter the power loss ratio is given by:

22ω PkTLR=+1 N , where TxN ( ) is a Chebyshev polynomial of order N ωc

Many characteristics like the above are already depicted, and it is up to us (the designer) to choose the one that suites our needs. These characteristics can help us decide the order of the filter.

Figure 13 - Attenuation characteristics for the Chebyshev filter: a) 0.5dB Ripple; b) 3dB Ripple.

The Chebyshev characteristics for various orders are shown on Figure 13. The 3dB passband Ripple characteristics provide sharper cutoffs, but reveal a significantly large Insertion Loss at low frequencies (the passband ones), which is a serious drawback for the filter. 27

For our design we want a low-pass cutoff frequency ωc = 40MHz and we would like to have a fair attenuation at the image frequency (AfIM > 50dB ). The image frequency is

2×137MHz away from the filter centre frequency f0 . So:

ω 2× 137 −=1 −= 1 5.85 ω 40 c

Looking at Figure 13 a), we conclude that a 3rd order filter complies with our requirements. Using a filter with higher order is not interesting because the size of the filter is also incremented and we want as much integration as we can get. We could also broad our number of alternatives to the Maximally Flat filter characteristics, but they didn’t turn out to be appealing because the attenuation characteristics were not enough sharp beyond the cutoff frequency. In short, we decided to use as a prototype filter the 0.5dB Equal Ripple (Chebyshev) filter of order 3. The power loss ratio is then:

22ω 3 2 PkTTLR =+133 , and (ω ) = 4ωω − 3 (3.3) ωc

2 For ω = ωc , PkLR =+1 ← passband ripple . One of the peculiarities of this filter (or any Equal-ripple 3rd order filter) is P = 1, which LR ω=0 means that ideally the filter will have a null insertion loss at centre frequency. Naturally, this is not achievable with a practical filter, but is a good indicator for the project.

3.2 Prototype circuit

The problem than now takes place is to find some physical circuit that synthesizes the power loss ratio function of the filter. The most general circuits used for low-pass filter design are LC ladder circuits with element definitions (which means, elements normalized to the load and generator impedances to which the circuit is connected). A generic circuit is shown on Figure 14.

Figure 14 - Ladder circuit for low pass prototype design.

It should be noted that the out-of-band attenuation between the source and load is due to the reflection of the input signal back to the source. A low-pass filter that has an inductance as the first reactive element (as is the case of Figure 14) will present a high input impedance above the passband.

The power loss ratio of this circuit is given by:

1 PLR = 1− Γ 2

So, the task now is to determine the element values g1, g2, g3, … , gN+1 that satisfy equation (3.3). This could be done with simple, classical circuit analysis, but there is no interest to do it because the calculations have already been made and are thoroughly spread through technical books and literature. From Table 8 we can obtain the element values for the 3rd order filter. The last element, g4, represents the load impedance, and for generic microwave applications it will be approximately 50 Ω, and this is why it has unity value. Although this analysis completes the low-pass prototype design, what we really want is to design a bandpass filter. To accomplish this we must use the frequency substitution of equation (3.4).

0.5dB Ripple N g1 g2 g3 g4 g5 1 0.6976 1.0000 2 1.4029 0.7071 1.9841 3 1.5963 1.0967 1.5963 1.0000 4 1.6703 1.1926 2.3661 0.8419 1.9841 … … … … … … Table 8 - Element values for the Equal-ripple lowpass filter prototype.

ω ωω12 ωω ωω− ω ω ←−=−∆==00 021, c (3.4) ω210−∆ωω ω ω 0 ω ω 0 ω 0

This frequency substitution scales the normalized prototype filter cutoff frequency

ωc = 1 to the desired value, and shifts the filter’s frequency domain attenuation characteristic to the centre frequency ω0 . Instead of making this substitution to equation (3.3), we can substitute it directly in the element values of Figure 14. The inductive elements impedance has the form Z = jgω i , and to a bandpass filter their impedance changes to:

11ωω0 Zj=−=− gii jgjω ' ∆ ωω0 ωgi ''

gi ∆ ggii'== and '' in series (3.5) ∆ωω00gi

The capacitive elements impedance also changes, and the new elements are given by:

∆ gi ggii'== and '' in parallel (3.6) ω00gi ∆ω

Table 9 clearly shows the needed substitutions for a low-pass → bandpass conversion. The inductances and capacitances are converted to series and parallel LC resonators, respectively. 29

Low-pass Bandpass

Table 9 - Lowpass → Bandpass filter element values conversions.

The several LC resonator component values were calculated for our desired filter parameters, and the LC network was simulated using ViPEC. The frequency response is shown on Figure 15. Recalling that the image frequency is located at 1419MHz, we notice on Figure 15 an attenuation of 55dB, well above our specifications. The centre frequency is exactly 1693MHz and the 0.5dB bandwidth is approximately 81MHz. Also, the reflection coefficient S11 is below -30dB around 1693MHz, showing that at least for now, we’re in good conditions for a successful design.

Figure 15 - Simulated frequency response for the bandpass LC network. 30

Figure 16 shows the simulated circuit. Capacitances are in pF and inductances are in nH.

Figure 16 - Simulated LC network.

The LNA and the bandpass filter are to be assembled as a whole in a PCB laminate, using the well known microstrip line technology. The lumped elements filter here discussed generally works well at low frequencies, but as we get close to microwave frequencies some problems arise:

• Lumped elements are only available for a limited range of values; • Lumped elements are difficult to implement at high frequencies; • They require short-circuits at these frequencies, and we know by practice that short-circuits should be avoided; • The electrical distance between filter components is not negligible at high frequencies.

3.3 Microstrip implementation

Hence, to avoid the problems of lumped elements, we must address another way of implementing the filter. There are techniques to conceive the filter directly by means of microstrip lines, mainly because there are several ways to “emulate” the LC resonator through transmission lines. There are three basic forms of coupled-resonator bandpass filters in microstrip line:

• Quarter-wave coupled quarter-wave resonators; • Capacitively coupled quarter-wave resonators; • Edge or Parallel coupled filters;

The one that interests us is the 3rd one, because it allows the smallest length possible, has the best spurious response, and furthermore because it allows larger gaps between lines, providing larger bandwidths. Now we turn our attention to the design of the parallel coupled filter. A series connected half-wave transmission line is equivalent (under some constraints) to a parallel LC resonator. Another example is a quarter-wave, short-circuited transmission line stub, but it has the drawback of requiring very low characteristic impedances, and so the first example should be used when possible. We have just found a way of creating parallel LC resonators with transmission lines. What about the series resonators? Well, one way to solve this is to use intercalated immitance inverters. This means that a generic circuit like the one of Figure 16 can be replaced with the one of Figure 17, where only parallel resonators exist.

Figure 17 - Equivalent circuit for the series-parallel LC network.

What the immitance inverter does is to transform an admittance or impedance to its reciprocal. For example, if the load admittance is YL the input admittance (transformed) will 2 be YJYin= / L . Thus, an immitance inverter, inserted in front of a series-resonant circuit, transforms it into a parallel-resonant circuit and vice-versa. The easiest way to create an immitance inverter is to use a quarter-wave transmission line, or a line with an odd multiple of λ /4. Unfortunately it turns out that the simple λ /4 transformer is not adequate in most cases, due to the limited range of characteristic impedances available in practical microstrip lines. Although this seems like a dead-end, a more thorough knowledge of transmission line properties will help us find a solution.

3.4 Coupled line equivalent circuit

Consider the circuit of Figure 18, where an immitance inverter is adjacent to two quarter wavelength transmission lines.

Figure 18 - Coupled line equivalent circuit.

Four of these circuits connected together, will form a circuit that is equivalent to the circuit of Figure 17. The λ /4 lines connect to each other creating a λ /2 line, this line being responsible for emulating the LC resonators.

Figure 19 - Equivalent circuit of the LC resonator network of Figure 16.

Two circuits are equivalent if the following two properties are satisfied:

• They have equal image impedances Zi at some well defined frequency; • They have equal propagation constants β at some well defined frequency;

VV V Zi =×12, cos β = 1 II21 V2 VI22=00= I2 =0

V1 2 V2 2 For the circuit of Figure 18 it can be shown that = jJZ0 , =−jJZ0 and I2 I1 V2 =0 I2 =0 the image impedance then becomes:

2 ZiJZ= 0 (3.7) Also, 1 cosβθθ=+JZ0 cos , is the electric length of the lines JZ0 (3.8) which depends on the frequency

Let’s now turn our attention to the coupled line description. A coupled line consists of two transmission lines located parallel and near to each other, resulting in some significant electromagnetic coupling between the two. There are many possible coupling mechanisms, but the one that interests us is the one provided by the circuit of Figure 20. It possesses a directional coupling mechanism, and acts like a bandpass filter (at very high frequencies and at low frequencies it acts like an open circuit, and between these frequency values it exhibits a passband – a finite impedance).

Figure 20 - Parallel coupled line.

A regular transmission line is described by its characteristic impedance Z0 . Coupled line theory shows that a coupled transmission line may be described with not one but two characteristic impedances Z0e and Z0o , the even and odd mode impedances. The image impedance of a λ /4 long line section is:

1 ZiZZ=−() (3.9) 2 00eo

And the propagation constant is:

ZZ+ cosβ = 00eo cosθ (3.10) ZZ00eo−

Now we can equate equation (3.9) with (3.7) and equation (3.10) with (3.8), obtaining the equivalence conditions for the coupled line (Figure 20) and the circuit of Figure 18. These are: Z=++ Z[1 JZ() JZ 2 ] 00e 0 0 2 (3.11) ZZ00o =−+[1 JZJZ 0() 0 ] 33

The parallel coupled filter will look similar to the one drawn on Figure 21.

Figure 21 - Bandpass filter, with edge-coupled resonators (N=3).

We must relate the circuit of Figure 16 with the circuit of Figure 17, finding J1, J2, J3 and J4. Then we may use equations (3.11) to find the even and odd mode characteristic impedances of the coupled line. Finally we can use a program like Ansoft Serenade to calculate the microstrip line dimensions (and separations) associated with Z0e and Z0o . Equating the input impedances of the circuits of Figure 16 and Figure 17, we are able to prove that they are equivalent if the following conditions are met:

1'Cg1 22 = (3.12) J10ZL g 1'' 22 J10ZC gi ' 2 = (3.13) JiiLg'' 232 JZJNN−+10 1 2 = Z0 (3.14) J N

Where,

2Z0 π LC== , , gii ' and g '' are the frequency scaled element values. πω0002Z ω

Finally, substituting gii ' and g '' by the values shown on the right column of Table 9 (multiplied by Z0 for impedance scaling), the results are the needed equations for the Jis' of the immitance inverters:

π∆ J1 = 2 (3.15) 21Z0 g π∆ J i ==, iN 2,3,..., (3.16) 2Zgg01ii− π∆ J N +1 = 2 (3.17) 2Z01ggNN+

Now that we have all the munitions to design the parallel coupled filter, we must simulate it to check that everything is working as planned. Substituting equations (3.15), (3.16) and (3.17) into (3.11) for N=3, we obtain the following values for the even and odd mode impedances:

Z01e = 63.1 Ohm Z02e = 52.96 Ohm Z03e = 52.96 Ohm Z04e = 63.1 Ohm

Z01o = 41.5 Ohm Z02o = 47.4 Ohm Z03o = 47.4 Ohm Z04o = 41.5 Ohm Table 10 - Even and odd mode impedances for the 3rd order parallel coupled filter.

This design was simulated again in ViPEC, and Figure 22 shows the gain of the scattering parameters S11 and S21. The attenuation at the image frequency is approximately 53dB, clearly conforming to specifications. The 0.5dB bandwidth is about 82MHz and the centre frequency is exactly 1693MHz. The reflection coefficient is still keeping very low around the centre frequency. Furthermore, we should notice the resemblance of Figure 22 with Figure 15, showing that our assumptions were correct and that the parallel coupled filter is in good conditions to work. ViPEC only simulates generic transmission lines, and so, although this simulation worked fine, we don’t know what will happen when a microstrip line is used to fabricate the filter, specially because there are important parameters to be considered like metal thickness and conductivity, dielectric thickness, dielectric loss, microstrip fringing effects and so on… this means that we will be forced to use an Electromagnetic Simulation Package (Software) to be more confident on the results.

Figure 22 - Simulated frequency response for the parallel coupled bandpass filter. 35

3.5 EM Simulation

To simulate the filter using Electromagnetic Simulation (EM), we will use Ansoft Ensemble. First we must obtain the coupled lines width and separation, which is related to the 4 even and odd mode impedance pairs. We could use the tool TRL from Serenade to calculate these values, but for this first design we will resort to Figure 23 taken from literature. The normalized admittance J’ is equal to the various Jis' that we have been referencing on.

g1 = 1.5963 g2 = 1.0967 g3 = 1.0967 g4 = 1.5963

J1 = 0.0043 J0.00112 = J0.00113 = J4 = 0.0043 ww1== 4 1.04 mm; s1==smm 4 0.147 ww231.15= = mms230.873==smm

Table 11 - Width and separation values for electromagnetic simulation.

Figure 23 - Coupled line width and separation curves, as a function of the immitance inverters normalized admittance (J'). J’ is proportional to ∆, and consequently, to the bandwidth. From this figure we conclude that to increase the bandwidth we must reduce w and s, increasing the coupling between lines. We also see that a decrease in w must be accompanied by a decrease in s and vice-versa. 36

(50) Table 11 values were evaluated for ε r = 2.2 , hmm= 0.381 and wmm= 1.16 . Ansoft 2D Modeller was used to create the layout of the filter as it will appear on the final PCB. Figure 24 depicts the result.

Figure 24 - 2D Modeller filter layout.

After that, 2 simulation ports were introduced at the first and last coupled line, and Ansoft Ensemble solver was used to find the scattering parameters of the filter (as if it was a two port network). Figure 25 presents the magnitude of the scattering matrix. As we might already be expecting, the EM result differs from the ideal transmission line simulation using ViPEC. The gain of the filter at the passband is well below 0dB (-1.7dB), S11 is much higher which means that the passband Insertion Loss is higher, and finally, the bandwidth is now smaller. Considering from now on the -3dB bandwidth, we witness a reduction to B = 70MHz. We will be able to compensate these deficiencies later on the project.

Figure 25 - Scattering parameters EM simulation result for the coupled line filter.

We also show a plot of the simulated VSWR on Figure 26. Near the 1693MHz frequency, VSWR ≈ 1.57 , which leads us to the conclusion that the filter is significantly adapted to the input and output 50Ω ports, and consequently let’s the RF signal circulate from one port to the other, providing a low Insertion Loss. One thing we don’t understand is why the VSWR is much higher below the passband than above the passband. It was expected that 37 they were going to be similar, but the fact is that this didn’t happen. Fortunately, this characteristic clearly benefits us because we want VSWR as higher as we can get at the image frequency. We will be able to show that better results are possible.

Figure 26 - VSWR EM simulation result for the coupled line filter.

Just as a matter of curiosity we also simulated the projected parallel coupled filter, using Ansoft Serenade. It doesn’t use EM simulation, but allows us to specify the type of transmission line and more PCB parameters, among others. The schematic was the one of Figure 27.

Figure 27 - Ansoft Serenade schematic of the filter. 38

The result of the simulation is shown on Figure 28. We have to notice a greater accuracy when compared with the ViPEC simulation. We establish the EM simulation as a point of reference, because it is the most accurate of all of them. We must conclude that although ViPEC network analyser is a good starting point, it cannot be used to simulate projects that require a high level of exactness, or we could end up with a project that once put into the PCB, didn’t abide by the specifications we were aiming for. We have been developing the filter carefully, and everything seems to work fine, but we are forgetting something. What is the size of the filter? The size is 4× (λ / 4) = λ , or in other words, 13cm, which is clearly out of question if we want a compact LNA design.

Figure 28 - Ansoft Serenade simulation result.

3.6 Hairpin design

The question that we now put to ourselves is how to reduce the size of our parallel coupled bandpass filter. One of the most frequently used practical design techniques for microwave microstrip filters is the hairpin resonator model. It does not require a large real size as the parallel coupled filter, and also doesn’t require critical grounding thus making manufacturing easier. There is very few literature that discusses the design of this filter and normally Electronic Design Automation (EDA) software is employed to synthesize and optimize the design for the desired specifications (for example, Microwave Office). Nevertheless, we will not use this type of software because our design will be based on the project we have been making and simulating until now. Let’s first consider the generic design of the filter shown on Figure 29. 39

Figure 29 - Generic edge (parallel) coupled filter.

The hairpin filter is a variant of the parallel coupled bandpass filter. A sliding factor is introduced to allow for bending, thus making the design more compact. Figure 30 shows the filter after the sliding factor has been introduced.

Figure 30 - Parallel coupled filter after introducing a sliding factor.

We should remark that the length of the resonators is still λ /2 and so the centre frequency (frequency of resonance) remains the same. On the other hand, the coupling between the resonators decreases, because the sliding of the resonators reduced the coupling regions between the coupled lines. This results in a considerable reduction of the filter bandwidth, making it impossible to conform to the specifications. To solve this problem, we will have to make the project of the parallel coupled filter again, this time increasing the bandwidth (∆), so that when we convert the filter to hairpin, it shall have a bandwidth approximately equal to the specifications. To avoid always making the calculations again, we have made a small Matlab script to automate it:

z0 = 50; delta = 130/1693; w0 = 2*pi*1.693; g1 = 1.5963; g2 = 1.0967; g3 = 1.5963; g4 = 1;

J1 = sqrt(pi*delta/(2*g1*z0^2)) J2 = pi*delta/(2*z0*sqrt(g1*g2)) J3 = pi*delta/(2*z0*sqrt(g2*g3)) J4 = sqrt(pi*delta/(2*z0^2*g3*g4))

z0e_1 = z0*(1+J1*z0+(J1*z0)^2) z0o_1 = z0*(1-J1*z0+(J1*z0)^2) z0e_2 = z0*(1+J2*z0+(J2*z0)^2) z0o_2 = z0*(1-J2*z0+(J2*z0)^2) z0e_3 = z0*(1+J3*z0+(J3*z0)^2) z0o_3 = z0*(1-J3*z0+(J3*z0)^2) z0e_4 = z0*(1+J4*z0+(J4*z0)^2) z0o_4 = z0*(1-J4*z0+(J4*z0)^2)

Figure 31 - Matlab script for filter calculations. 40

In the above script example, we used a bandwidth of 130MHz, and as we will see, it will do just fine. The several even and odd mode impedances obtained are then used to calculate the coupled lines width (w) and separation (s) (using Serenade’s TRL). Now, to “shrink” the filter on Figure 30, we must bend the λ /2 resonators 180º around their centre, keeping the coupling sections unmodified. The result of the modification is depicted in Figure 32. The bending points are cut to minimize the fringing effects that will occur between the edges of the coupled lines. Also, the length of the resonators should remain the same, which means: λ abc+ += 2

The sliding factor b affects the Insertion Loss, the centre frequency and the possibility of re-entrant frequencies.

Figure 32 - Hairpin resonator structure.

Decreasing b lowers the Insertion Loss, as more signal power is concentrated on the coupling structures instead of being attenuated along a transmission line path. However, if b is decreased without holding the total resonator length constant, then a frequency shift occurs. Additionally, decreasing b drastically may introduce resonator self-coupling, which produces re-entrant frequencies. Some tests also showed that decreasing the coupled line separation (s) results in a filter response with a wider bandwidth. This conclusion is somewhat intuitive because we know that decreasing the separation, more coupling will occur, and consequently more power is transferred between the lines. Reducing too much the separation can also increase ripple effects. The hairpin structure reduces drastically the size of the filter, but once again it brings a problem: large Insertion Loss and poor Return Loss. A tapped hairpin resonator filter has a smaller Insertion Loss and better Return Loss. The tapped hairpin resonator is characterized by the addition of a matching stub at both ends (see Figure 33), which allows to adapt the filter to the 50Ω lines. To adapt the filter we can use the conventional method of load matching using stubs, but first we need to know the input reflection coefficient of the filter, without the stubs and taps. This can only be done using the results of an EM simulation.

Figure 33 - Hairpin resonator filter with matching stub.

Let’s apply this method to our filter…

Running the Matlab script of Figure 31, we obtain the following results for the even and odd mode impedances of the coupled lines:

Z = 67.662 Z = 55.0445 Z = 55.0445 Z = 67.662 01e 02e 03e 04e Z01o = 39.9935 Z02o = 45.8085 Z03o = 45.8085 Z04o = 39.9935

Introducing these values in Serenade TRL calculator, we find the widths and separations:

ω = 2mm ω = 2.3mm ω = 2.3mm ω = 2mm 1 2 3 4 s1 = 0.2mm s2 = 1.1mm s3 = 1.1mm s4 = 0.2mm

The widths and separations are calculated for a PCB with ε r = 2.2 and hmm= 0.7874 . The metal layer is copper with a thickness of 0.034mm. The original size of each line is λ / 4= 32.4mm , and so the total resonator length is 64.8mm . The λ /2 resonators were bent at the following points: 29.1mm and (29.1+6.6) = 35.7mm. After this the following steps were taken:

1. the sides of the bending edges were cut; 2. the length of all the resonators was adjusted to λ /2 (this has to be done because the width of the coupled lines is different); 3. The layout was made using Ansoft 2D Modeller and the shape of the filter was the one of Figure 32; 4. The value of S11 was determined at f = 1693MHz (this is the input reflection

coefficient Γin ); 5. A Smith Chart was used combined with the matching stubs technique to adapt the input and output of the filter. The parameters obtained were: a. the length of the line before the stub and tap; b. the length of the stub; 6. The position of the tap and the length of the stub were adjusted and several simulations were done to adjust the filter response.

The taps and stubs width is 2.4mm, matching the width of the 50Ω microstrip line for the dielectric chosen. Figure 34 shows the final filter layout with added line dimensions. The model was simulated using Ansoft Ensemble, which produced the response shown on Figure 35. As we can see by that figure, we were able to achieve a very low reflection coefficient at the passband, and this was only possible with several tap adjustments and simulations. The negative peak of S11 occurs exactly at 1693MHz, and this was achievable only by analyzing the Smith Chart behaviour of the scattering parameters, and comparing it to effect of stub length and tap position. The final Smith Chart response is plotted on Figure 36. The centre of the chart is at 1693MHz.

Figure 34 - 2D Modeller hairpin bandpass filter layout, with added dimensions.

Figure 35 - Simulated frequency response of the projected hairpin filter. 43

Figure 36 - Smith Chart response of S11. We should notice the non-simetry of the response in relation to the axes.

We now set a breakpoint here, and characterize the simulated hairpin filter response:

0.5dB I.L. at Centre Selectivity Bandwidth / 0.5dB Ripple (dB Max. VSWR frequency dB min @ 3dB passband max.) in 0.5dB BW (GHz) MHz Bandwidth (dB max.) B0.5dB = 41.7 @ 1.7 62MHz 1.69 No ripple 1.4 ( f0 − 200) B3dB = 95MHz Figure 37 - Hairpin filter characteristics measured from the EM simulated responses.

A relevant fact is the complete absence of ripple in the passband, which does not agree with the fact that this filter is based on a Chebyshev prototype, inherently having some ripple. The ripple is usually the price to pay if we want a sharper cutoff, which means, higher selectivity. Also, the Insertion Loss is degraded in this type of filter. Fortunately for us, after all the modifications and “manoeuvres” that we have done to the original filter, we end up with a response with a very sharp cutoff (for a 3rd order filter), and also no ripple at all, and consequently, a very soft passband frequency response along with a very low Insertion Loss. The filter is evidently better than what we were expecting and fulfils all the specifications. Will it work when fabricated?...

3.7 PCB filter tests

Earlier on this project we were making all the calculations to a PCB dielectric of height 0.381mm (instead of 0.7874mm). The method was nothing more, nothing less than the above described, but for a different dielectric. The filter was fabricated on a PCB and simulated on a network analyser. The S parameters were extracted and are plotted on Figure 38.

Figure 38 - Frequency response of fabricated filter (for a different dielectric → h = 0.381mm).

In the previous figure we can also see a plot of the filter’s simulated response. Even though very similar, we emphasize that this is not the simulated response of Figure 35, but the response of the filter with the calculations made for a different PCB. Comparing the simulated and measured responses we witness a very similar passband response, including analogous 3dB bandwidths and centre frequencies almost exactly the same (the Insertion Loss is also very low). Unfortunately, the measured cutoff response is not as sharp as the simulated counterpart, and we have a lower selectivity, but this should not come as an alarm because the difference is not much. In what concerns to the Image Rejection, we can also observe a worst performance for the measured data (more or less a 6dB difference). This different behaviour differs from the initial objectives for the filter, mainly because we were expecting to get a minimum of 50dB attenuation at the Image Frequency. One possible way to improve this situation is starting with a new filter design with some “margin of error” degree, but this would possibly lead us to a higher order filter, or even a different type of filter. Higher accuracies could also be achieved with more expensive filters (we must remember that using a transmission line to emulate a resonator is not the best way through, especially if we want very stringent frequency responses). 45

Again, the Return Loss is not as good as we were expecting, and we can watch that a frequency drift to the right has occurred inside the passband. We should also remember that we will be using the filter near the 1693MHz frequency, for which we measure a 17dB Return Loss. This is not as good as the simulated measurements (35dB), but it’s fairly good as well. The measured filter properties are summarized in Figure 39 (once again, not to be compared with Figure 37):

0.5dB I.L. at Centre Selectivity Bandwidth / 0.5dB Ripple (dB Max. VSWR frequency dB min @ 3dB passband max.) in 0.5dB BW (GHz) MHz Bandwidth (dB max.) B = 36.6 @ 1.71 3dB 1.54 No ripple 1.34 110MHz ( f0 − 200)

Figure 39 - Hairpin filter characteristics measured from the network analyser (different PCB → h = 0.381mm).

Comparing this test results to our initial aiming, we have a frequency shift of 17MHz, a 3dB bandwidth 30MHz larger (almost flat passband), an Insertion Loss 0.46dB better but also a worst selectivity (≈ 6dB worst).

3.7.1 Why the differences?

The different behaviour of the filter after the design, simulation and implementation is related to the following aspects (and possibly others): o First of all, the design was made using techniques based on ideal transmission line theory, which disregards some physical aspects like fringing effects, dielectric loss, inductive and capacitive marginal effects that only appear when working with real transmission lines; o The design was made for a regular transmission line, not a specific one (like microstrip), not taking into account the almost purely empirical mathematical description of microstrip lines; o The EM simulation, though accurate, is not exact; o The PCB dielectric constant (εr) and dimensions are probably slightly different from the specified ones; o The PCB fabrication process is not entirely accurate. The process has a 100µm optimistic precision. We must remember that the frequency response of the coupled lines is very sensitive to the widths and separations of the strips.

Noise Figure: An acceptable approximation of the filter’s noise figure is its maximum passband attenuation. Looking at Figure 39 we realize that Fmax ≈ 1.54dB. As already pointed out, the noise figure of the filter is of minor importance because of the relatively high gain stage preceding the filter. This concludes the analysis of the bandpass filter.

4. The PCB layout

The complete layout of the LNA is included in Appendix B and repeated here for a matter of convenience (Figure 40).

Figure 40 – Layout for microstrip implementation of the LNA (not in actual size).

4.1 The PCB laminate

From the list of available laminates (Table 4), the RT/Duroid 2.2 – 0.031” was selected due to the following reasons:

• It has the lowest tan(δ ) and, therefore, the lowest dissipation due to substrate losses; • It has a low dielectric thickness, which is important to minimize ground inductances. • The 0.015” laminate was too thin for our purposes, since the PCB has a relatively large area and it could become quite fragile.

An obvious disadvantage is its cost factor.

4.2 Component placing and layout details

The layout of Figure 40 was entirely designed with Xfig. Since it is not the purpose of this report to describe in detail all the techniques associated with PCB layout design, only the most relevant aspects will be focused. Throughout the layout design process, we had a few general concerns in mind:

• Minimize the total PCB area, not only due to its cost, but also because we were restricted to the dimensions and shape of the enclosing metal box.

• Avoid closely spaced lines/components, since the fabrication process has a finite precision and imposes a minimum spacing between metal lines. Also, lines with significant length placed side-by-side may give rise to undesired coupling effects. 47

• Avoid placing components too close to the bandpass filter, since it is quite sensitive to perturbations introduced nearby (let’s not forget that, in ultimate analysis, the same dielectric is shared by all the components on the PCB).

• Place enough number of ground connections where appropriate, to avoid voltage gradients and minimize the effects of dielectric noise.

We will now analyse the layout details of each LNA block separately.

4.2.1 Low-noise GaAs FET

The source of the transistor is connected to a metal strip with several ground holes along its length. This allows the introduction of a variable source inductance and can be used, if necessary, to create feedback in the transistor circuit, thereby improving the input VSWR. However, source feedback increases the noise figure and reduces the transistor gain. Note that the open-circuit stub in the transistor’s output matching section includes additional length of line, which can be soldered to the end of the stub in order to allow small length adjustments. Also note the inclusion of a λ / 4 short-circuited parallel stub just after the input RF connector. This stub represents an open-circuit at the operating frequency and is used to eliminate strong UHF signals picked up by the antenna, which could saturate the transistor.

4.2.2 Monolithic amplifiers

The layout for the 2 monolithic amplifiers is based on the one suggested in the device’s datasheet. Several ground holes are provided to ensure a good ground connection. Also note that both devices are biased through the output port, with similar biasing configurations.

4.2.3 Bandpass filter

The filter layout is the same as the one already presented in Figure 34, using the hairpin technique.

4.2.4 DC biasing circuit

All amplification stages are biased with λ / 4 lines, in a typical configuration also found in [8]. The length of these lines was determined using ViPEC’s microstrip calculator - in fact, ViPEC was used to design all the transmission lines in the LNA, including the 50Ω RF lines, the low frequency trap stub and the transistor matching stub. Note that we have some freedom in selecting the widths of the lines used in DC biasing. However, the following factors should be taken into account:

• A very wide λ / 4 bias transmission line can adversely affect the RF signal path. Therefore, we designed them with the smallest width allowed by the fabrication process.

• The bias lines connecting the voltage regulator and DC/DC converters should be quite wide, since they are expected to conduct larger DC currents.

The layouts for the voltage regulator and DC/DC converters are similar to the ones found in their respective datasheets and required no special care. The layout for the lumped components, such as resistances, capacitors and potentiometer, were also taken from their datasheets (see Appendix C for a complete list of all the components that were used).

5. LNA assembly, test and modification

After the PCB was fabricated, all the components were soldered and individually tested. The biasing devices (DC/DC converter and voltage regulator) were perfectly functional, as well as the bandpass filter and the two monolithic amplifiers, which had the expected behaviour. However, we came across the following problems:

• The FET could not be properly biased, due to significant instability in the drain and gate voltages, which often varied in an abrupt way without any apparent reason. We were unable to find a solution to the problem, even after biasing the same FET in a separate board, using the configuration suggested in its datasheet. Our decision was to replace the transistor stage (and the associated matching circuits) by a monolithic amplifier, the SGA-4586. This device required no matching circuit and had significant gain (typically, 19dB), although exhibiting a larger noise figure (approximately 2dB).

• Although it was not absolutely necessary (since they were working fine), the two monolithic amplifiers were replaced by two ERA-3SM. These devices had gain and noise figure characteristics not very different from their SGA-6586 counterparts, but the advantage that they could be biased using +5V (instead of the previous +9V) and had less power consumption. The intermediate voltage regulator and DC/DC converter were also removed from the PCB, since they were not needed anymore.

• With the above modifications, the LNA worked properly. However, after placing the PCB inside the metal box, it exhibited oscillations due to cavity resonance effects. These oscillations were not eliminated by isolating the interior of the box with an electromagnetic-absorbing material. The solution we adopted was to remove the monolithic amplifier just after the bandpass filter. This overall gain reduction solved all instability problems (probably by eliminating some kind of positive feedback of electromagnetic nature, that took place inside the metal box).

The resulting LNA circuit schematic is given in Appendix A (Figure 44), and the corresponding PCB layout is also given in Appendix B (Figure 46).

6. Network analyser measurements

After all the necessary modifications, the S-parameters of the LNA were obtained using the network analyser. These are displayed in Figure 41. 49

Figure 41 – The S-parameters of the LNA as a function of frequency, obtained with the network analyser.

From Figure 41, we can determine the S-parameters of the final LNA, measured at the operating frequency (f = 1.693 GHz):

SdB11 =−11.3

SdB22 =−2.1

SdB21 = 29.2

SdB12 =−40.6

The information given in Figure 42 can be used in the following way to calculate the overall noise figure of the LNA:

FF23−11− FF=+1 + GGG112 2.24−− 1 1.6 1 =+1.51 + 39.8 39.8× 31.6 =+1.51 0.031 + 5.10−4 ≈=1.55 1.9dB 50

As expected, the first stage is the one with the greatest influence in the overall noise figure.

G≈16dB G≈15dB L=1.6dB F=1.8dB F=3.5dB F=1.6dB

Figure 42 – Data for overall noise figure calculation. The noise figures of the monolithic amplifiers were taken from their datasheets. The gains of 16dB (first amp) and 15dB (second amp) are lower than those found on their datasheets (19dB for both), due to impedance mismatches.

7. Conclusions

To finish this report, a comparison between the initial LNA specifications (Table 1) and the actual LNA characteristics can be made. Thus, the following specifications were fully satisfied:

• Gain − the 30dB of gain were achieved with only two amplification stages (the specifications required 30dB and assumed three amplification stages); • Supply voltage and current − the final LNA has VVDC =12 and ImADC =100 ; • Estimated cost − see Appendix C; • Gain flatness − ± 0.5dB was required and ± 0.4dB was achieved.

However, the following specifications were not met:

• Noise figure − a 1dB noise figure was required, but only 1.9dB were achieved. This degradation is due to the replacement of the FET stage by a monolithic amplifier. • Input and output VSWR − the specifications required an overall S11 and S22 of –21dB (or, in other words, a VSWR of 1.2). Although the datasheet for the SGA-4586 presented 18dB as the typical input return loss, only 11dB were achieved, due to possible impedance mismatches. Also, only an output return loss of 2dB was achieved (this is not critical, since it can be compensated by the other stages of the downconverter following the LNA).

Although these two specifications were not satisfied, they virtually had no impact whatsoever on the overall downconverter performance.

References

[1] Pozar, David M., Microwave and RF Design of Wireless Systems, Wiley, New York, 2001.

[2] Datasheets for all the components.

[3] Agilent Technologies, AN 1076: Using the ATF-10236 in low noise amplifier applications in the UHF through 1.7 GHz frequency range.

[4] Agilent Technologies, AN 1128: L Band Amplifier using the ATF-36077 Low Noise PHEMT.

[5] Agilent Technologies, AN 1129: Low Noise Amplifier for 2.3 GHz using ATF-36077 Low Noise PHEMT.

[6] Agilent Technologies, AN 1097: L and S Band Amplifiers Using the ATF-36163 Low Noise PHEMT.

[7] A downconverter for Meteosat, http://www.qsl.net/ok2xdx/DK/DKEN.html

[8] An L-Band PHEMT LNA, http://www.applet.cz/~ulcak/lna.htm

[9] The Meteosat System, http://www.eumetsat.de/

[10] Meteosat WEFAX Dissemination, http://www.eumetsat.de/

[11] Pozar, David M., Microwave Engineering, J. Wiley, 2nd Ed.1998

[12] E.H. Fooks, R.A. Zakarevicius, Microwave Engineering using Microstrip Circuits, Prentice Hall, 1990

[13] Toledo, Nikholas G., Practical techniques for designing microstrip tapped hairpin resonator filters.

APPENDIX A - LNA electrical circuit schematics

Figure 43 – Electrical circuit of the LNA (initial version). 53

Figure 44 – Electrical circuit of the LNA (final version, after the last-hour modifications). APPENDIX B - PCB layout schematics

P 2

U 0

E 0

F 2

n I

Figure 45 – Layout for microstrip implementation of the LNA (initial version, 200% scale). 55

n I

Figure 46 – Layout for microstrip implementation of the LNA, after the last-hour modifications (200% scale). The intermmediate regulator has been removed. The layouts for the FET stage, DC/DC converter and last monolithic amplifier remain, but are not used (or, at least, in the way they were intended to…). This avoided the fabrication of a new PCB, and allowed us to reuse the one in Figure 45.

APPENDIX C - Complete list of LNA components

Component Value Quantity Price (each, euro)

RF connectors - 2 7 Capacitor 22pF 1 0.06 Capacitor 68pF 2 0.06 Capacitor 100pF 3 0.06 Capacitor 100nF 1 0.15 Capacitor 10nF 2 0.06 Capacitor 22uF 1 0.8 Capacitor 0.47uF 1 0.7 Inductor(RF) 100nH 1 0.8 Inductor(Bias circuit) 100nH 1 0.03 Resistor 27 3 0.03 Resistor 18 2 0.03 Resistor 330 1 0.03 LED - 1 0.2

LM2940 - 1 1.8 SGA-4586 - 1 4.0 ERA3-SM - 1 1.8

Total approximate cost = 25 euro

APPENDIX D - LNA Photos

Figure 47 – The LNA inside its metal box.

Figure 48 – Measurements using the network analyser.