66--1111 Design of a Half Adder

• The design process for a AB SC half adder is similar, but um out there is no carry in so 00 00 there w ill be on ly 2 inpu t bits, A and B, Two outputs 01 10 Sum and Carry. 10 10

• HA only operates on two 11 01 inputs, an example would be the addition of the LSB position of two binary Sum = AB + AB = A + B numbers with no carry. Cout = AB • A full Adder can be Sum implemented from two HA A as shown, verify that this B HA HA configuration operates as Carry In Full Adder? Cout

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66--55 Multiplication of Binary Numbers

• This is similar to multiplication of decimal numbers. • Each bit in the multiplier is multiplied by the multiplicand. • The results are shifted as we move from LSB to MSB in the multiplier. • All of the results are added to obtain the final product. • If numbers are in 2’s complement, represent it in true binary and perform multiplication as follows: – If both are negative, take the 2’s complement and perform multiplication, the result should be positive. – If both have different sign, represent the negative number in true binary, perform multiplication, represent the product in 2’s complement since it should be negative.

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1 66--66 Binary Division

• This is similar to decimal long division. • It is simpler because only 1 or 0 are possible. • The subtraction part of the operation is done using 2’s complement subtraction. • If the signs of the dividend and divisor are the same the answer will be positive. • If the signs of the dividend and divisor are different the answer will be negative. • Perform the same procedure used for multiplication when dealing with signed numbers.

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Binary Multiplication/Division - Example

Multiplication: 1001 (9)10 - multiplicand

1011 (11)10 - multiplier 1001 1001 0000 1001

1100011 (99)10

0011 Division : 11 1001 - Dividend 011 0011 11 0

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2 66--1313 Carry Propagation

• Parallel adder speed is limited by carry propagation (also called carry ripple). • Carry propagation results from having to wait for the carry bits to “ripple” through the device.

•S4 out of the last FA depends on C1 out of the first FA, C1 must pass thru 4 FA before it produces S4 • If each FA has 40 ns delay, then S4 will not reach its correct level until 160 ns after C1 is generated • Additional bits will introduce more delay. • Various techniqqpues have been developed to reduce the delay. The look-ahead carry scheme is commonly used in high speed devices. For example: design a logic circuit with B3, B2, B1, B0, and A3, A2, A1, A0 as inputs and C4 as an output, which will have a shorter delay. Cons: Extra logic.

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66--1414 Integrated Circuit Parallel Adder

• The most common parallel adder is a 4 bit device with 4 interconnected FAs and look- ahead Carry circuits. • The The A and B lines each represent 4 bit

numbers to be added. The C0 is the carry in, the C4 is the carry out, and the Σ lines are the sum of the 2 numbers.

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3 66--1414 Integrated Circuit Parallel Adder

• Parallel adders may be cascaded together as shown to add larger numbers, in this case two 8 bit numbers. A<7:0> and B<7:0>

•C8 is the carry out of MSB

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66--1515 2’s Complement System

• Addition of negative and positive numbers using adders is done by placing the negative number into 2’s complement form and performing normal addition. • Subtraction is done by converting the number to be subtracted (subtrahend) to 2’s complement and adding to the minuend. • An adder can be used to perform addition and subtraction by designing a way to take the 2’s complement for subtraction as described in next slide.

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4 Parallel adder used to add and subtract numbers in 2’s2’s--complementcomplement system.

• Addition: -3 is represented in 2’s complement (1101) and +6 is represented as (0110), Sum=0011 which represents +3, C4 is 1 but it is ignored. • Subtraction: taking the 2’s complement of the number to be subtracted (subtrahend) can be done by complementing each bit (1’s complement) and add 1 to LSB.

Slide - 151

Parallel adder used to perform subtraction (A - B) using the 2’s-2’s-complementcomplement system.

• Subtraction: The bits of the subtrahend (B) are inverted, and C0=1to0 = 1 to produce the 2’s complement • The output represents the results of the subtraction, Σ3 represents the sign bit, and C4 is ignored • 4(0100)4(0100)--6(0110)6(0110) is done by compltilementing subtra hen d

(1001) 1 • The adder adds (0100) and +4 0100 (1001) with C0=1, results in -6 1001 (1110) in 2’s complement 1110

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5 Parallel adder/subtractor using the 2’s2’s-- complement system (Adder/Subtractor)

• A complete circuit that performs both addition & subtraction. • The Adder/Subtractor is controlled by two signals ADD and SUB. When ADD is high, the circuit performs addition of numbers in [A] & [B]. When SUB is high, the circuit subtracts [B] from [A]. • ADD=1 and SUB=0, AND gates 2,4,6,8 are disabled, AND gates 131,3,5,7 are enabled allowing [B] to feed the Circuit and C0=0. • ADD=0, and SUB=1, does the reverse, allowing [B] to feed the circuit and C0=1.

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66--1616 ALU Integrated Circuits

• ALUs can perform different arithmetic and logic functions as determined by a binary code on the function select inputs. • There are many different devices. The 74LS382 (TTL) and HC382 (CMOS) is a typical device with: – 20 pins device operates on 2 4-bit inputs A<3:0>, B<3:0> and produces 4 outputs F<3:0> – 8 possible functions (3 function select inputs)

• Clear: when S2S1S0=000, ALU clears all of the output bits. • ADD: when S2S1S0=011, A<3:0>+B<3:0>= F<3:0>, CN is LSB carry in, and CN+4 is the MSB carry out. OVER: detects if overflow happened. • Subtract: when S2S1S0=001, B<3:0>-A<3:0>= F<3:0>, when S2S1S0=010, A<3:0>-B<3:0>= F<3:0>, with CN=1 • XOR: when S2S1S0=100, A<3:0> B<3:0>= F<3:0> bitwise (bit-by-bit) • OR: when S2S1S0=101, A<3:0> OR B<3:0>= F<3:0> bitwise (bit-by-bit) • AND: when S2S1S0=110, A<3:0> AND B<3:0>= F<3:0> bitwise (bit-by-bit) • Preset: when S2S1S0=11, ALU sets all of the output bits, F<3:0> = 1111

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6 66--1616 ALU Integrated Circuits

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Expanding ALU –8– 8--bitbit ALU

•What is The operation performed with this setup? •What needs to be changed to perform A – B ?

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