Zhejiang University Prof. Yan, Xiaolang Introduction of Zhejiang University

• Established in 1897 in the beautiful city Hangzhou, which is the capital of Zhejiang Province and Marco Polo’s favorite city, 120 miles away from Shanghai. Introduction of Zhejiang University • The largest university in China. • One of the most prestigious universities in China, one of the best engineering schools in China. • Over 33,000 students, including 26,450 undergraduates, 4,550 postgraduates working for master's degrees and 2,070 Ph.D. candidates. • Total area of 287 hectares and a floor space of 1, 600,000 square meters. Introduction of Zhejiang University

• Over 800 full professors and 2,200 associate professors. • Over 10,000 staff members and workers. • There are also nearly 24,000 students taking courses in degree and non-degree programs of continuing education. • IC design and software development are the concerning emphases of Zhejiang University and Hangzhou municipal government. Professor Yan, Xiaolang • Tenure Professor of Zhejiang University and HIEE (Hangzhou Institute of Electronic Engineering). • Dean of the College of Electrical Engineering of Zhejiang University. • Director of Expert Committee of VLSI Design of China State Hi-Tech R&D Plan (863 Projects). • Email address: [email protected] Introduction of Center of VLSI Design • People – Faculty: 2 professors, 3 associated professors and 5 assistant professors and researchers – Students: more than 40 Ph.D. candidates and postgraduates for master degree • Research and Development Fields – IC-CAD Algorithm and Tools – ASIC(SOC) Design • Supported by Zhejiang Province Government Previous Work (1)

• PLA Design Automation Subsystem of Chinese National Second ICCAD System

• Place & Route Subsystem of Panda ICCAD System Previous Work (2)

• Channel-Oriented BBL Placement & Routing Algorithm Research and Tool Development – Placement based on min-cut – Global routing – Detailed routing Previous Work (3)

• Logic Synthesis Algorithm Research – Description language capture – State optimization – State assignment – Logic minimization Current Projects (1)

• Timing-Driven BBL and Standard-cell Placement – BBL placement based on non-slicing model BSG, Sequence-Pair, etc. – Area minimization under path-delay constraints – Considering routability – Considering heat-distribution uniformity Current Projects (2)

• Multi-layer Area Detailed Routing – allowing reserved layer mode or unreserved layer mode – allowing pre-routed nets and obstacles – supporting stacked via – simultaneously optimizing total wire length and the number of vias – critical nets being prior to be routed – crosstalk being taken into consideration Current Projects (3)

• Clock Net Routing – Algorithm of topology generation for clock tree and its embedding approach based on balanced partition – Buffer insertion and placement algorithm to optimize clock tree topology generation – Wire sizing algorithm to optimize delay, area and clock skew Current Projects (4)

• Cell characterization tool – Timing parameters – Input capacitance – Power consumption – DC characteristics – Easy-to-use automatic interface to simulators such as HSPICE and Verilog- XL. Current Projects (5)

• Simulation Engine for Optical Proximity Correction (OPC) – Fast photolithography simulation. – Lithography process characterization. – Also could be used in full-chip layout verification, and timing parameters extraction. Plan for large scale application chip design

• 3G wireless communication chip set. – IS95 – Cdma2000-1x • System design already done (FPGA) • Next step is to implement it to SOC

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