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HP Enterprise Business Template Angle Light 4:3 Purple Intel Itanium Processor Technology and Roadmap Update th 27 April 2011 OpenVMS 2011, Bad Homburg Dr. Feixiong Liu Senior Staff Engineer Technical Account Manager for HP Servers Intel EMEA [email protected] Legal Disclaimer • INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. • Intel may make changes to specifications and product descriptions at any time, without notice. • Intel does not control or audit the design or implementation of third party benchmarks or Web sites referenced in this document. Intel encourages all of its customers to visit the referenced Web sites or others where similar performance benchmarks are reported and confirm whether the referenced benchmarks are accurate and reflect performance of systems available for purchase. • Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. • Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. • Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and applications enabled for virtualization technology. Functionality, performance or other virtualization technology benefits will vary depending on hardware and software configurations. Virtualization technology-enabled BIOS and VMM applications are currently in development. • Intel Turbo Boost Technology requires a system with Intel® Turbo Boost Technology capability. Consult your PC manufacturer. Performance varies depending on hardware, software and system configuration. For more information, visit http://www.intel.com/technology/turboboost • 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. • Intel, Intel Xeon, Intel Core microarchitecture, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Itanium® and the Mission Critical Biz Update Source: IDC Q1’11 Worldwide Server Tracker (May’11) (1) Source: HP 2010 2002 2010 Itanium® Itanium® $102M $3.7B RISC/ Total: $49.3B Intel x86 Intel x86 mainframes Total: $53.6B IA share: 39% $19.2B RISC/ $31.7B $15.3B IA share: 66% mainframes $29.6B AMD AMD $330M $2.9B (1) More than 80% top Global 100 companies running Itanium Predictable Tick-Tock Model Sustained Server Microprocessor Leadership Tock Tock Tock Tukwila Poulson Kittson Tick Tock Tick Tock Tick Tock Penryn Nehalem Westmere Sandybridge Ivybridge Haswell All timeframes, products and dates are subject to change without further notification. Moore’s Law: Alive and Well at Intel Continuing Moore’s Law Transistor each new process technology Performance allows up to: +20% Switching Power -30% 180 n m 1999 13 0 n m 2001 90 nm 2003 Production 65 nm 2005 Development 45 nm On Track Research 200732 nm 15nm 200922 nm Potential future options, no indication of 2 0 11 actual product orAll development, Intel products subject to change benefit without from notice. Intel’s deep investment in advanced silicon manufacturing technologies 2.3 Billion Transistors on the Intel Xeon 7500 CPU Each Transistor is 5x smaller than an Influenza Virus 100 nm L = 20 nm 100nm Influenza virus 20 nm gate length (LG=20) So u r ce : CD C Intel Transistor They all have to work! Complete Line of Mission Critical Offerings connected by the Common Platform Strategy Common Ingredients: Chipset | Interconnects | Buffers | Memory OpenVMS NonStop Flexibility and Choice for a new Era in Mission Critical Computing 7 Family of Mission Critical Processors Choice of Architecture Based Itanium 9300 Series on: Architected for Hardened Mission Critical UNIX Operating with mainframe resiliency System and scalability Application Availability Xeon E7 Series OEM System Capability Architected for scalable Windows and Linux OEM Service & performance with Support advanced reliability Two Server Platforms to meet a wide range of Mission Critical Requirements 8 Intel® Itanium® Platform Roadmap 2009 2010 2011 2012 Future Dual-core, 667 Front Side Quad-core, 30MB cache, 6 8-Core, 32nm, 54MB cache, Bus, Demand Based Intel QPI links, VT-i, Integrated new 12-issue architecture, Switching, Core Level memory controllers, Advanced Instruction Replay, New Lockstep RAS Instructions QPI ® Itanium ® 9100 Series Itanium 9300 Series Poulson* Kittson 870 / OEM Intel® 7500 Chipset / OEM Chipsets Chipsets PCIe Boxboro-MC Platform 2.0 In planning QPI speed up to Scalable Memory Socket Compatible with 6.4GT/s, VT-d, Buffer (DDR3- Itanium® 9300 and DDR3 PCIe Gen2 RDIMMs) Memory Support • Poulson program on track and silicon is going through early post-silicon characterization • Product availability is targeted for 2012 * Product availability targeted for 2012 9 Poulson: Advances Itanium® Architecture Key Highlights • New Micro-architecture, 2x the cores, 2x instructions throughput • Socket and Binary Compatible with Itanium® 9300 processors (Tukwila) • 3.1 Billion Transistors on 32nm process • Total 54MB on-die memory • Intel® Instruction Replay Technology • Intel® Hyper-Threading Technology, enhanced with dual-domain multi-threading support • Intel® Itanium New Instructions Poulson: the most sophisticated Intel® processor to date The Poulson-MC Processor Architecture Overview • Up to 8 cores per socket Poulson-MC Processor • Up to 32 MB shared Last Level Cache (LLC) • 2 integrated memory controllers supporting Intel® Core Core SMI* running at 6.4 GT/s Core Shared Core LLC 45 GB/s Memeory Bandwidth/Socket Core Core • 4-full and 2-half width Intel QuickPath® Core Core Interconnects running at 6.4 GT/s Memory Link Controllers Controllers 128 GB/s Communication Bandwidth/Socket • 2 Directory caches • Supports enhanced Hyper-threading 4 SMI* 4 Full + 2 Half • Supports new RAS features Channels Width Intel QPI Links • Power/thermal variants targeting: • 170W, 155W, 130W Poulson Platform vs. Tukwila Platfrom 2010 2012* New Micro-Architecture CPU (Poulson) Itanium Itanium Poulson Poulson 9300 9300 New Scalable memeory buffer (Mill Brook2) QPI @ 4.8 QPI @ 6.4 • Low Voltage DIMM and Itanium Itanium Poulson Poulson 1066 MHz support 9300 9300 Faster QPI speed(CPU-CPU, CPU-IOH) QPI@ 4.8 QPI@ QPI@ 6.4 QPI@ SMI @ SMI 4.8 • 6.4 GT/s vs. 4.8 GT/s SMI @SMI 6.4 Intel 7500 Faster SMI speed Scalable Intel 7500 Mill Brook Intel 7500 Memory Chipset 2 Chipset • 6.4 GT/s vs. 4.8 GT/s Buffer ICH10 ICH10 DDR3@ 800 DDR3@1067 * DDR3-1066 DIMM * DDR3-1066 RDIMM or DIMM DIMM LVDIMM *Platform availability Poulson Processors Poulson Package Poulson in a system 1 Next Generation Micro-Architecture Front-End Back-End Instruction Buffer Key New Features • Instruction Replay automatically recovers from severe errors to improve resiliency • Enhanced Hyperthreading enables concurrent operations on different threads and improves performance New architecture brings a leap in performance and process resilience Exploiting Parallelism on All Levels Multi-core Parallelism/Multi-socket Parallelism Thread Parallelism Instruction Level Parallelism Memory Parallelism Multi-level parallelism exposed to software control Multi-core and Multi-socket Parallelism 700GB/s (aggregate) Core 3 LLC LLC Core 4 Core 2 LLC LLC Core 5 128GB/s QPIx6 10 port QPI Router HAx2 45GB/s MCx2 SMI Core 1 LLC LLC Core 6 Core 0 LLC LLC Core 7 New bi-directional high-bandwidth ring interconnect Example 8-Socket Topology Full Intel® QPI ® I/O I/O Half Intel QPI Memory Hub Memory Memory Hub Memory Intel® SMI Poulson Poulson Poulson Poulson Poulson Poulson Poulson Poulson Memory I/O Memory Memory I/O Memory Hub Hub Hyper-Threading Technology Improvements Front-End Back-End • Dual-domain multi-threading N combines elements of B F IPG FET FDC REN DEC REG EXE DET WRB WB2 SOEMT (Switch-on-event) IBD A and SMT (Simultaneous) Replay Path I Replay Path M multi-threading Flush Path • Front-end and back-end can operate on different threads • IBD stores 96 instructions per thread (96x2 queue entries) • Maximizes efficiency of concurrent threads to drive 12-wide issue • Front-end and back-end can switch threads on different conditions Dual-Domain Multi-Threading support enhances MT performance Instruction Parallelism Front-end Back-end MLD IPG FET FDC REN MQ Memory OZQ … 32B – 6 Instructions IQ Integer Compilers precisely AQ ALU control instruction dispersal FQ Floating Point BQ Branch NopQ NOP 12 -wide issue under software control Instruction Parallelism and memory parallelism
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