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Power management
Power Management 24
Power Management Using FPGA Architectural Features Abu Eghan, Principal Engineer Xilinx Inc
Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice
Computer Architecture Techniques for Power-Efficiency
Dynamic Voltage/Frequency Scaling and Power-Gating of Network-On-Chip with Machine Learning
Power Reduction Techniques for Microprocessor Systems
Happy: Hyperthread-Aware Power Profiling Dynamically
Learning-Directed Dynamic Voltage and Frequency Scaling Scheme with Adjustable Performance for Single-Core and Multi-Core Embedded and Mobile Systems †
Optimization of Clock Gating Logic for Low Power LSI Design
White Paper | ADVANCED POWER MANAGEMENT HELPS BRING
Mutual Impact Between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
Dynamic Voltage and Frequency Scaling : the Laws of Diminishing Returns Authors Etienne Le Sueur and Gernot Heiser
Power Management and Dynamic Voltage Scaling: Myths and Facts