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Power Management of Low-Power Design 2 POWER MANAGEMENT OF LOW-POWER DESIGN_2 G.C.MANJUNATHA Associate prof., PDIT, HOSPET Email:[email protected] Abstract multi voltage, power gating with or without state Elevated temperatures are a major retention, dynamic voltage and frequency scaling contributor to lower semiconductor and substrate biasing. reliability. If heat is not removed at a rate The use of any of these techniques comes at a and equal to or greater than its rate of generation, their benefit varies depending on the technique junction temperatures will rise. Higher used. In shot they introduce rise to the product junction temperatures re-duce mean time to development schedule and impact all aspects of failure for the devices. Device reliability has a ASIC and SoC development, including design, direct impact on the overall system reliability. implementation, and verification. Each Removing heat from these devices is thus a technique used must be considered with the rest major task facing design engineers of modern of the system requirements. electronic power maintenance systems For example, designers will have to choose concerned with improving reliability. between power gating with or without state Understanding the effect of heat on the retention. Power gating with retention achieves reliability of electronic products and the faster wakeup times and preserves state integrity of manufacturing processes is information, but it requires more silicon real critical if problems are to be avoided. This estate as well retention flops must be powered up means the need to understand power when the rest of the domain gating is the most management techniques and the need for effective in reducing leakage power. However it comprehensive data has never been greater. is also the technique with the most impact to With passive cooling methods, the chip current design and verification flows and temperature is determined by the efficacy of methodologies. heat transfer out of the device. Power gating state retention involves switching off an area of a design when its functionality is INTRODUCTION not required then restoring power when it is. The The increasing demand for high performance, areas created by gating are called power blocks battery-operated, SoC (system —on-chips in .power gating requires the use of retention communication and computing has shifted the memory elements to prevent data from being lost focus from traditional constraints such as area, in a specific power domain during power down. performance, cost and reliability to power Retention strategies such as retention flops and consumption. Just as important, through not so latches save information before a power domain obvious, is the need to power consumption for switching off and restore it when the power non-portable systems, such as base stations, domain is turned back on. As well .Restore where heat dissipation and energy consumption protocols must be used to ensure that the power are critical concerns. domain returns to a known good state when There are techniques that have been developed powered up. Finally, each power domain must be over the past decade to address the continuously isolated from the rest of. when powered down so aggressive power reduction requirement of most that it does not corrupt downstream logic. ASIC AND SoC designs. They include clock Gate level verification poses many issues such gating, multi-switching threshold transistors, as: ISSN (PRINT): 2393-8374, (ONLINE): 2394-0697, VOLUME-4, ISSUE-2, 2017 29 INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR) Time: gate level simulation are slow. As the power management techniques employ Debug: debugging at gate level is difficult as the turning off aid various segments of a design, user defined RTL specification has been these designs are divided into different power transformed into implementation through blocks, based on areas of functionality that synthesis. support common operations or tasks. In other Problem rectification: it takes longer and words a requires more resources to resolve function problems uncovered at the gate level compared RETENTION MEMORY ELEMENTS: to RTL To maintain the state of registers and latches For these reasons waiting to perform power during sleep mode, retention elements are aware design verification at gate level is too employed that can retain heir data when in sleep costly in terms of resources and design cycles. mode alternatively, voltage threshold scaling This paper describes the basic elements of low may be used for retention without requiring a power design verification and implementation. bubble latch to hold the retained value. RFFs and Designers have developed various low power RLAs are affected by the power signals that techniques to reduce leakage power control the RTL region to which they belong. consumption. These techniques make use of The registers are corrupted when the power is some of sleep operation. Placing power gating switched off. Corruption is typically represented structures is a well known technique for reducing by unknown. the register valve is restored after power leakage during stand mode, while power up if the value was saved successfully maintaining high speeds in active mode. During before power down and the restore protocol stand by one or more portions of the circuit are executed successfully. Otherwise, the register switched off and the passage from the source to value remains unknown until) it is set ,reset, or a ground is blocked, eliminating leakage in those new value latched into it. These elements will areas. One side effect of power gating is that data behave as normal memory elements when the in storage elements can be lost. As a result, power is switched on and the power control designers use retention memory elements to signals are not asserted. The retention flip flop is retain key state data during the sleep .Mode so a clock low retention FF. These types of FFs that it can be restored correctly upon power up have one control signal known as ret. A clock this is retention sleep mode. low retention FF requires that the clock be gated some designs use a conventional sleep operation low during the save and restore operation and in which the power supply of the entire design is most likely during retention as well. When ret is cut off when the circuit is not in use such designs asserted and the clock is low,the restore option is do not require data in the registers/latches used performed. They behave as normal FFs when ret in the design. Power down in book computers is is low. an example of such asleep mode. However, even with the conventional sleep operation, function MOVING LOW POWER SPECIFICATION verification of the design is required to ensure TO THE RTL: that the awake portion of the design function Power gating requires early verification. Waiting properly while other parts are sleeping and that for the gate Izvel netlist is too costly for a number the system will operate correctly when power is of reasons, rincluding slow simulation time and to the sleeping logic blocks. more difficult power domain constitutes a With retain sleep mode, the operation of a logic collection of functionality that can be turned off circuit is stopped only if that specific work is not as a whole, and it runs at the same operating in use. Low power devices in portable equipment voltage level, having a single set of power use retention sleep mode during intermittent control signals. Power control signals are used to operations. These devices preserve the dead control sequential retention cell, isolation cells during sleep. The sequential cell are blown as and the switches that serve as gatekeepers to a retention flip flops .to implement sleep power blocks power supply. Management techniques, will defined power In addition , every power aware design has at management block must be created with specific least one primary domain , which is always on. power control signals and power domains. This is known as either the wake-up . debugging POWER MANAGEMENT DESIGN and problem resolution. In addition, information STRUCTURE: at the RTL to validate that low power techniques ISSN (PRINT): 2393-8374, (ONLINE): 2394-0697, VOLUME-4, ISSUE-2, 2017 30 INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR) are implemented correctly in the early as well as stages of the design flow. LOW POWER STANDARD FORMAT: Low power specification are need at each step of POWER INFORMATION CAN INPUT AT the design flow so that correct power THE RIL IN TWO WAYS: management components can be implemented at 1 .Directly specified in the RT code the RTL ,correctly during synthesis and placed 2. Indirectly specified in the file. and routed efficiently and accurately in physical By directly integrating the power information in design. This requires a single power format RTL, the corresponding power information is accepted by all tools in the flow at any given packaged together with the RTL.. Most resister abstraction level. A single power format case and latches in a RTL design are inferred and not implementation and validation and helps meet explicitly coded as part of the HDL there is no design schedules. It must also address guarantee that the retention cells will be reusability, allow early and thorough validation functionally the new technology library. and have built extensibility. Similarly power control signal to retention cells and the installation of isolation cell and level DEFINE SYSTEM POWER STATES AND shifters within the RTL code create an THE SUPPLY NETWORK: unnecessarily tight coupling between the design When designing the low power aspects of an functionality and low power design intent. electronic system should start by defining the Finally as significant aspects of the low power system power states.. for ex. A system power design intent is related to the technology states may be such that the modem is in sentinel implementation, it is usually modified often than mode, waiting for an incoming call.
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