A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

applied sciences

Review A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

Andrea Ballo * , Michele Bottaro and Alﬁo Dario Grasso

Department of Electrical, Electronic and Computer Engineering, University of Catania, Viale A. Doria, 6, 95125 Catania, Italy; [email protected] (M.B.); alﬁ[email protected] (A.D.G.) * Correspondence: [email protected]

Abstract: This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building block since it maximizes the power extracted from the piezoelectric devices and delivers it to the other building blocks of the implanted device. Since the power budget is strongly constrained by the dimension of the piezoelectric energy harvester, complexity of topologies have been increased bit by bit in order to achieve improved power efficiency also in difficult operative conditions. With this in mind, the introduced work consists of a comprehensive presentation of the main blocks of a generic power management unit for ultrasound-based energy harvesting and its operative principles, a review of the prior art and a comparative study of the performance achieved by the considered solutions. Finally, design guidelines are provided, allowing the designer to choose the best topology according to the given design specifications and technology adopted.

Citation: Ballo, A.; Bottaro, M.; Keywords: energy harvester; AC–DC converter; implanted medical devices; battery-less systems; Grasso, A.D. A Review of Power power management integrated circuit Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices. Appl. Sci. 2021, 11, 2487. https:// doi.org/10.3390/app11062487 1. Introduction Battery-powered electronics systems, such as wearable and mobile devices, wireless Academic Editor: Eyad H. Abed sensors, and medical devices are widely used during the everyday life. Implantable medical devices (IMDs) represent a category of electronic systems which have an increasing Received: 1 February 2021 impact in the improvement of quality of life since they enable monitoring or replacing of Accepted: 6 March 2021 sensory functions. The idea of using an IMD to assist patients originates since 1950s when Published: 10 March 2021 the appearance of transistors opened the possibility of implementing a fully implantable pacemakers [1]. From that, various devices have been developed such as heart rate moni- Publisher’s Note: MDPI stays neutral tors, cochlear implants, retinal implants and brain-computer interfaces. All these devices with regard to jurisdictional claims in have a similar architecture which is summarized in Figure1. published maps and institutional afﬁl- iations.

Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Figure 1. General block diagram of an implantable device with battery. Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ It comprises circuital blocks for sensing/actuation, signal processing, communication 4.0/). (transmitter device), and energy management as well as for energy storage (usually imple-

Appl. Sci. 2021, 11, 2487. https://doi.org/10.3390/app11062487 https://www.mdpi.com/journal/applsci Appl. Sci. 2021, 11, 2487 2 of 21

mented by a battery). Although the power required by an IMD is contained, the methods to provide energy to these kind of electronic devices represent the bottleneck of their diffusion. Indeed, the technological progress of batteries does not have a similar trend of the semiconductor transistors scaling, therefore devices are much smaller than the battery needed for their operation, limiting the minimum volume of the implanted device. The pacemakers, for instance, clearly demonstrate such limitation considering that their total volume, dominated by the battery, has hardly changed over decades of evolution. Thus, for implantable devices, the battery is not suitable for its invasive dimensions and its limited lifetime. Moreover, batteries require a new surgery operation for replacement or need to be recharged by wireless system [1,2]. To solve these issues, the idea of recovering energy from the environment is adopted. A system exploiting this technique, usually referred to in the literature as energy harvesting, is shown in Figure2. The energy recovered from light, vibrations or temperature gradients, allows extending the system lifetime by reducing the battery capacity or even eliminating it [3–10]. Battery-less systems allows longer and potentially unlimited lifetime, reduced size, improved bio-compatibility and better eco-friendliness. However, an IMD based on energy harvesting still requires an energy storage device to be used to enable the systems working even when no energy can be collected from the energy harvester. In this case, direct connection between the energy harvester and the energy storage device is usually not possible and the energy management unit is in charge of handling its charging/discharging. For this purpose, simple capacitors are preferred over batteries due to their superiority in terms of life cycle and compactness.

Figure 2. Block diagram of an implantable device with energy harvesting.

The methods of providing power to IMDs can be categorized into two types, namely the in-body type and the out-of-body type. The in-body energy sources come from the human body. Some examples are vibrations gathered from patient movements, breathing activity, and heartbeats through piezoelectric devices, or temperature gradients between the inner body, the skin and the air that are converted into voltage by thermo-electric generators (TEGs) [11–13]. Unfortunately, these in-body sources provide extremely low and unpredictable power levels which prevent their adoption in most applications [14–16]. In out-of-body power delivery, an external energy source is coupled to the energy harvester implanted inside the body, which will charge an accumulation device (rechargeable battery or, more frequently, a capacitor) or will directly feed the IMDs [5,17]. The external power can be provided through radiofrequency, electromagnetic induction or Ultrasound (US) waves. Among these power transfer systems, only US waves have the capability to enable simultaneous power and data transfer in deep-implanted (>2 cm) mm-sized devices [18–21]. Indeed, the spatial-peak temporal-average intensity (or ISPTA) allowed by American Food and Drug Administration is 7.2 mW/mm2 for diagnostic US applications, while the exposure limit for Electro-Magnetic (EM) systems, set by the Federal Communi- cations Commission and IEEE, is only 10–100 µW/mm2 [22]. As a result, about two orders of magnitude higher power can be transmitted using US, which is particularly useful for deep IMDs. Moreover, because acoustic waves do not directly interact with EM waves, they are not as susceptible to EM interference nor do they signiﬁcantly affect the EM ﬁelds Appl. Sci. 2021, 11, 2487 3 of 21

of the surroundings. Finally, US waves have smaller wavelengths in tissue (e.g., ∼1.5 mm at 1 MHz) and low tissue attenuation (∼0.5–1 dB/cm/MHz) allowing highly directive focusing down to millimeter spots at great depths and high acoustic-electrical efﬁciency with sub-millimeter-sized receivers [19,23]. The adoption of US energy harvesting systems relies on piezoelectric devices. The piezoelectric phenomenon was discovered in 1880 by the French physicists Jacques and Pierre Curie [24]. They discovered that certain materials generate an electrical polar- ization proportional to an applied mechanical stress via the piezoelectric effect (Figure3).

Figure 3. Concept of piezoelectricity.

When an external force is applied, positive and negative charged surfaces are generated, called polar surfaces. The piezoelectric potential created by these polar surfaces can be used to drive electrons in an external circuit, realizing the conversion of mechanical energy into electricity. During the operations of the piezoelectric devices, polar surfaces have to be maintained in order to generate continuously the electric energy. At this purpose, US waves are the widely used means to induce a stress on the piezoelectric material. Thus, the output voltage of a piezoelectric transducer results to be an AC voltage. The frequency of the US wave is set equal to the resonant frequency of the transducer, which is inversely proportional to its size. As mentioned above, from an electrical point of view a piezoelectric device generates an AC voltage. Therefore, a system that provides AC–DC conversion is required to provide a DC supply to the electronic systems of the IMD. At the same time, due to possible misalignment between the external generator and internal transducer, the amplitude of the output voltage could unpredictably vary and, consequently, it is not suitable to directly feed the circuits. As shown in Figure4, a typical power management integrated circuit (PMIC) consists of an AC–DC converter and a power converter, whose output voltage is controlled to provide a specific DC voltage value. Since the piezoelectric devices are often chosen from those commercially available, the architecture of the PMIC is the main diversification factor among the various proposed IMDs. In decades of evolution, the PMIC topology has been made more complex to meet the more and more stringent specifications imposed by device miniaturizations and ultra-low-power constraints. The output voltage of the rectifier is always less than the maximum input voltage, therefore, it may be too low to supply any electronics system. To solve this problem a boost converter is necessary. The DC-DC boost converter in Figure4 can be implemented using switched inductor (SI) or switched capacitor (SC) topologies. SI converters are suitable for applications requiring high power but requires bulky off-chip components (inductors and/or transformers), resulting in a cost increase of the entire system. Moreover, magnetic components strongly reduces scalability and compactness of the IMD, making it unsuit- able for applications requiring minimal invasive systems with mm-scale form factor [25]. On the other hand, in low-power low-area applications, SC converters represents a better Appl. Sci. 2021, 11, 2487 4 of 21

alternative since they are amenable for full on-chip integration SC converters with a voltage gain higher than one are referred to in the literature as voltage multipliers or charge pumps (CPs) [6,26–28]. The conventional topologies of a monolithic charge pumps are the linear known as Dickson and Cockcroft-Walton charge pumps, which are made up of MOSFET diodes and capacitors clocked by a two-phases clock generator. In these topologies, an increase of the output power requires an increase of the capacitance value of each stage. Thus, new schemes, aimed to reduce the silicon area which occupy and improve their power efﬁciency, are continuously studied and introduced in the literature [6].

Figure 4. Simpliﬁed block diagram of a power management integrated circuit for ultrasound-based energy harvesting.

With this in mind, this paper is aimed to provide a deep-insight of energy harvesting systems from US waves targeted to feed IMDs. This is allowed by analyzing the design constraints and basic topologies used to satisfy the speciﬁcations required by application, and reviewing the state-of-the-art. The work is organized as follows. The second section gives information about the operation principle and topology of the conventional circuits used to rectify the AC signal outputted by the piezoelectric device. In the third section, the state-of-the-art of the PMICs for IMDs is reviewed and performance comparison is reported in section four. Finally, some conclusions close the paper.

2. Conventional Topologies for AC–DC Conversion As mentioned above, the systems of interest harvest energy by means of a piezoelectric transducer, which converts ultrasound (US) waves into alternate electrical quantities, voltage and current. For medical devices, Food and Drug Administration (FDA) limits for power transmission into tissue to be the U.S. lesser than 7.2 mW/mm2. Therefore, with the compact size requirements, power induced by US sources results to be limited in the order of few milliWatts. Typically, attenuations due to the US link (in this case, human tissues) further decreases these values. Thus, the system requires a very efficient conversion from AC to a DC voltage and a regulator to supply the biomedical functional circuits. To convert the AC voltage into a DC voltage a circuit (called rectifier) is required. The basic elements of a rectifier are diodes, historically realized with PN junctions, but they can also be implemented by using transistors (i.e., diode-connected transistors, PMOS diodes and NMOS diodes). These diodes are made by connecting gate and drain of the transistor and the current flows as indicated by the arrow. This type of diode may exhibit a relatively high leakage current when realized by means of a short-channel transistor, therefore, to reduce the reverse leakage, a composite CMOS diode can be adopted [29]. Nonetheless, this topology increases the conduction resistance which in turn increases the forward dropout voltage. The choice of a specific diode is mainly driven by the Appl. Sci. 2021, 11, 2487 5 of 21

characteristics of the adopted technology, the minimum amplitude of the input signal and realization costs. However, the MOS-based diode, in its simple or composite version, seems to be a valid trade-off in many cases and it is the widely adopted device in AC– DC converters. The main rectifier topologies are classified as passive and active rectifiers. In passive rectifiers, the transistors work as simple diodes while in active rectifiers, auxiliary circuits are added to decrease the voltage drop and improve the performance of the transistors used as diodes. Two traditional passive rectifier topologies are shown in Figure5[29].

Figure 5. Schematics of (a) the half-wave rectiﬁer and (b) the full-wave rectiﬁer.

Focusing on Figure5a, in the first half cycle VAC is positive and the diode D1 will conduct when VAC1 goes higher than the DC output voltage VDC. During the second half cycle VAC is negative and D1 is surely reverse-biased. Therefore, this circuit delivers current from the AC source to the DC output, at the maximum, during a half cycle, therefore it is called half-wave rectifier. On the other hand, in the rectifier shown in Figure5b, during the first half cycle, the diodes D1 and D4 will conduct when VAC is higher than VDC. In next half cycle, D2 and D3 will conduct when the voltage VAC2 − VAC1 is higher than VDC. Therefore, this circuit delivers current to the output twice a cycle, it is so-called full-wave rectifier. These solutions of rectifiers are very simple but have high dropout voltage and require an input voltage greater than one or two threshold voltage. Another passive rectifier is the Cross Coupled topology, whose simplified diagram is shown in Figure6[29].

Figure 6. Cross-coupled rectiﬁer [6].

The cross-coupled rectifier is widely used for its low-voltage and auto-switching characteristics. For high input voltage VAC, the MOS transistors will act as switches with low on-resistance for rectification, and the forward voltage drop is minimized. However, a high leakage current may occur if the input voltage, during the transition instants, is too high because the PMOS and NMOS will be turned on simultaneously short-circuiting the two supply rails. This rectifier operates efficiently with low input voltage, also below Appl. Sci. 2021, 11, 2487 6 of 21

the threshold voltage level. In such case, reverse and short-circuit currents are extremely reduced, but the on-resistance is increased, making the rectifier useful for very-low power applications (e.g., sub-µW power level). If the input voltage is larger than the threshold voltage of the transistors, the leakage current becomes relevant and the efficiency decreases, but the channel becomes more conductive decreasing the on-resistance and enabling mW -power level operations. The active rectifier shown in Figure7 has the same structure of the passive full-wave rectifier but diodes are replaced by active-diodes.

Figure 7. Active full-wave rectiﬁer with NMOS active diode.

Active diodes are essentially comparator-controlled MOSFETs. The operation principle of the active full-wave rectifier can be described as follows. Let us assume that the process starts with VAC1 going down and VAC2 going up. When VAC2 − VAC1 > VTH,P (threshold voltage of MP1,2), MP1 is turned on and therefore VAC2 = VDC. Then VAC1 swings below the ground voltage, the comparator CMP1 turns on the switch MN1, and IAC1 charges up VDC through the AC source. When VAC1 swings above zero, M1 is then turned off by CMP1, finishing one half cycle of the full-wave rectification period. During the next half of the AC input cycle, the other half of the rectification circuit will conduct in a similar manner as described above. Active diodes do not exhibit the large forward dropout voltage of conventional diodes and prevent the reverse leakage current. However, the implementation of an active diode entails additional area and power consumption for comparators. Moreover, they suffer in start-up at low input voltage because, generally, the comparator is powered by the output voltage of the rectifier. As already mentioned, the output voltage of the transducer or the rectifier may be too low to directly supply any electronics system. A possible solution is to exploit blocks which boost the voltage to the needed level (e.g., voltage multipliers or charge pumps). Such circuit can constitute a different building block of the conversion chain or replace the rectifier, acting as AC–DC boost converter [8,30,31]. Figure8 shows the simplified schemes of the most used charge pump circuits. As with the rectifier topologies, diodes are often replaced by MOS-based passive and active diodes [6]. Signals which clock the circuit, named VCK and VCK in the figure, can be generated internally the IMDs, for example by using a controlled oscillator, or can be provided directly by the transducer. In the first case, the Dickson CP is the topology widely adopted and it acts as DC-DC boost convert, moreover, in order to decrease the capacitance value of the pumping capacitor, C, and improve the PCE, high frequency counter-phase square-wave signals are used. In the second case, where the frequency of the clock signal is imposed by the adopted piezoelectric transducer, the widest adopted is Cockcroft-Walton CP, and it implements the AC–DC conversion. Appl. Sci. 2021, 11, 2487 7 of 21

Figure 8. Simpliﬁed schemes of Dickson (above) and Cockcroft-Walton charge pumps.

It is worth noting that also the cross-coupled structure can be exploited to realize diodes for CPs [32,33]. They are essentially latch-configured inverters with VOUT similar to the dual-branch charge pumps [6], but the pumping capacitances of a single stage are halved. These dual compensated structures introduce many benefits akin to the dual- branch structures. It improves pumping efficiency and reduces ripples in the output voltage. Moreover, while in a Dickson CP the voltage drop across each switch is equal to the diode threshold voltage, VTH, in the cross coupled charge pump the voltage drop is equal to the drain-to-source voltage VDS, which is lower than VTH. The output voltage of the charge pump depends on the power required by the load, therefore this voltage can be change dynamically. To prevent changes in this voltage, some type of feedback control can be implemented. The principal control technique based on frequency modulation, pulse width modulation and amplitude modulation of clock signal, are deeply analyzed in [8].

3. The State-of-the-Art of AC–DC Converters Many solutions have been proposed in the literature to improve the performance of the PMIC for IMDs. Since the output voltage of the transducer is an AC signal whose frequency ranges from some kHz to about 30 MHz [5], AC–DC converters topologies exploited for radiofrequency energy harvesting within low frequency range (e.g., below 100 MHz) could be adopted. For this reason, in this review some works based on radiofrequency energy harvesting are also included. Moreover, although all the solutions analyzed in this paper are equally interesting, for the sake of of conciseness only the topologies suitable for ultrasound energy harvesting are considered. As a first example, Maleki et al., in [34], presented an ultrasonically powered implantable micro-oxygen generator (IMOG) that is capable of in situ tumor oxygenation through water electrolysis. Wireless ultrasonic powering (2.15 MHz) was employed to increase the penetration depth and eliminate the directional sensitivity associated with magnetic methods. The block diagram of the overall system is shown in Figure9. In this case the receiver is constituted of a passive full-wave rectifier, a filter and the interdigitated electrodes which act as micro-oxygen generator. Although an output voltage up to 6.4 V and an output current equal to 300 µA is reported [34], the system performance is limited mainly by the passive rectifier.

Figure 9. Block diagram of the system proposed in [34]. Reproduced with permission from T. Maleki, IEEE Transaction on Biomedical Engineering; published by IEEE, 2011. Appl. Sci. 2021, 11, 2487 8 of 21

Huang et al. proposed a generic rectifier system for biomedical implants [35]. As shown in Figure 10, the full-wave rectifier is composed of two cross-coupled PMOS and two active NMOS-diodes. As compared to the classic topology, it implements a real-time NMOS on/off calibration to make sure the rectifier always operates at near-optimum conditions with circuit-delay elimination under different (process, voltage and temperature) corners and loading conditions, thus both power conversion efficiency (PCE) and voltage conversion ratio (VCR) are significantly improved. Moreover, NMOS adaptive sizing is also introduced for PCE optimization over a wide loading range. However, this system operates at 13.56 MHz and requires a relatively high input voltage (from 1.2 V to 2.4 V).

Figure 10. Rectifier proposed in [35]: (a) simplified block diagram; (b) control strategy; (c) detailed schematic of the real-time on/off calibrations for one side of rectifier. Reproduced with permission from C. Huang, IEEE Journal of Solid-State Circuits; published by IEEE, 2016.

It is worth noting that a lot of solutions proposed in the literature adopt AC–DC with at the least one couple of active diodes, NMOS- or PMOS-type, because they allow heavily reducing reverse and short-circuit current losses, which are the main drawbacks of the conventional cross-coupled structure (i.e., currents flowing from the output to the ground when transistors are switched-off or switched-on simultaneously). Improved versions of active diodes have been continuously introduced with the aim of further increasing the power efficiency of the whole converter. Generally three aspects, namely turn-on instant, conduction angle and MOSFET channel conductivity, mainly affect the PCE. Turn-on instant, defined as the time when the active diode is turned-on, can affect cross-conduction of MOSFETs constituting a single leg (for instance, transistors MN1 and MP2 or, alternately, MN2 and MP1, which constitute a vertical section of Figure7). This time must be calibrated in order to avoid any time slot where transistors of the same leg are on simultaneously. In a simple implementation, it is sufficient to make sure that the active diode switches when the complementary MOSFET is cut-off. Contextually, conduction angle, defined by the effective angular portion of input signal which is converted, has to be maintained as wide as possible to preserve the highest power transferring. Therefore, solutions on this way can be categorized based on the adopted strategy to modulate turn-on instant and conduction angle. As an example, some works introduced architectures where auxiliary delay cells are inserted with the aim to adjust the times when the MOSFET have to switch from cut-off to conduction, and vice-versa [36]. Similar effect can be obtained by acting on the effective threshold of the comparator. This can be done adding a voltage generator in series with one of the input terminals or designing the inner differential couple in an asymmetrical way. Among the topologies that exploit these design strategies, there are those presented in [37–39]. On the other hand, modulation of the channel conductivity can be an effective strategy to pursuit for those applications whose input signal amplitude is lower than a conventional threshold voltage (about 600 mV). Bootstrapping of the gate terminal and/or body biasing techniques are often exploited to control the channel conductivity of interested MOSFETs. Both strategies act similarly on the electrical features of the MOSFET, and they can be Appl. Sci. 2021, 11, 2487 9 of 21

used to improve the conduction and/or to reduce reverse losses [40–42]. Simpliﬁed block diagrams of the architectural solutions just mentioned, are gathered in Figure 11.

Figure 11. Simpliﬁed block diagrams of modiﬁed active diodes: conventional (a), with improved turn-on instant and conduction angle by means of delay cell (b) and threshold voltage shifting (c), bootstrapped (d) and body biased (e).

In [31], it is shown as AC–DC charge pump circuits can be optimally designed to have the minimum circuit area for small form factor vibration energy harvesting. The proposed system (Figure 12) was composed by a passive cross-coupled AC–DC converter without ﬁlter, whose rectiﬁed output signal feeds a current-controlled ring oscillator and a Dickson CP, whose diodes were implemented by composite CMOS diodes. The frequency of the clock signals was higher than that of the input signal, in such manner pumping capacitances can be reduced and output current strongly increased as respect to the CPs for AC–DC conversion present in the literature.

Figure 12. System diagram of the rectiﬁer proposed in [31].

Lee proposed a technique that combines a passive rectifier and a linear regulator without using a comparator (named prectulator)[43]. Since there is no speed limitation due to the comparator, the proposed technique can operate with high frequency input signals. As can be seen in Figure 13, the output transistor used for regulating the output voltage in a linear regulator is also used as a passive rectifier. To achieve rectification without turning on the parasitic bipolar transistor of the output transistor, an auxiliary rectifier is used for biasing the bulk terminal of the output transistor. + VD + VDO a maximum swing of about half the peak-to-peak value of VAC. M1 VUDC M2 Similarly, MB1 is added to reduce the voltage swing seemed by VO both MB1 and MB2 in the n-prectulator. R1 RL co1 AE aux. VB rect. VB

+ + IO VO VAC - - C R C < |VTP| B1 2 B2 VAC VO VG Vref VG MPR R1 CB A I VAC I Active rectifier Linear regulator E L O (a) RL Vref R2 IOavg + VS 0 MS VO (a) S1 S2 R1 RL

AE DS VAC CB VAC VB VAC VB co1 + + - - R2 CB1 Vref CB2

(b) CB1 Fig. 1: Powering implant based on (a) conventional method and (b) active rectifier/regulator combo circuit proposedAppl. Sci. 2021 in, 11[6, 2487] (b) (c) 10 of 21 Fig. 2: (a) conceptual prectulator design and auxiliary rectifier For VAC > VG + |VTP| and VAC > VO, IO will flow from VAC design based on (b) Schottky diode and (c) MOS realization to VO as shown in Fig. 2a where VTP is the threshold voltage D V of MPR. To have a regulated VO, the average IO, IOavg, is T ACT VDD adjusted by controlling VG, which is determined by the MT2 oP VOP feedback loop that consists of R1, R2 and AE. VG is assumed to MT3 CTB1 be relatively constant. For a given reference input voltage, Vref, MT1 IOVT the desired VO is equal to (1+R1/R2)Vref. By considering MPR VGT2 AT gT as the output transistor of a linear regulator that has an CTB2 VTref R C equivalent transconductance, design techniques for linear CT CT RT1 RT2 V FBT regulator can be applied to design the prectulator. For VAC < AC p-prectulator VO, MPR should be off (IO = 0) with VG > VO – |VTP|. This n-prectulator condition is satisfied if AE does not overdrive MPR into triode FBB RB2 R region even for large IL when VAC is greater than VO. To VBref RCB CCB B1 achieve this, AE is required to limit the range of VG when the CBB2 VGB2 AB gB situation of overdriving MPR is detected as discussed below. IOVB MB1 3. Proposed Voltage Doubling Prectulator Design MB3 CBB1 VOM To maximize the DC output voltage from the AC input, a MB2 oM V voltage doubling prectulator is proposed as shown in Fig. 3. It SS DB VACB consists of two prectulators – p-prectulator and n-prectulator, which rectify the AC input, VAC, and produce a regulated FigureFig. 13.3:The Proposed voltage doubling voltage prectulator doubling proposed prectulator in [43]. Reproduced with permission from E. positive output, VOP, and a regulated negative output, VOM, In theK. F.p-prectulator, Lee, IEEE Proceedings; during published startup by with IEEE, 2015.VAC being applied respectively. The total output voltage, V , equal to V – initially, the gate voltage of M , V , is ~0V. When M is OC OP An implantable systemT2 for poweringGT2 and data transmissionT2 is proposed in [44] VOM is doubled when compared to the one shown in Fig. 2a. turned (onFigure for 14increasing). This system VAC employs, VOP can two be rectifier charged paths, to namelya voltage the main and the auxiliary The ideal values of VOP and VOM are equal to (1+RT1/RT2)VTref higher path. than In one the main |VTP path| above there are ground. the main Hence, rectifier (Figure MTP can15a), DC-DCbe cross coupled Dick- and (1+RB1/RB2)VBref, respectively, where VTref and VBref are overdrivenson charge and current pump (Figure flow 15 backb) and from a regulator VOP to (Figure VAC 15canc). Theoccur main rectifier is realized by cross coupled NMOS and active PMOS diode with a simple comparator. The auxiliary path reference input voltages. For the selected process, Schottky for VAC < VOP. As a result, VOP cannot be charged up further. is used to supply a ring oscillator and a bias generator circuit. The use of a ring oscillator al- diode is available and is used for realizing the auxiliary In addition, for VOP < (1+RT1/RT2)VTref, AT will try to increase lows working at high frequency thus reducing the size of the capacitors. The rectifier of the rectifiers. Since the currents drawn by the amplifiers – AT and VOP byauxiliary holding path VGT2 is aat push-pull ~0V. Hence, voltage doublerVOP will (Figure be stuck 15d). Forbelow high available input power, AB are relatively low, their supply voltages (VDD, ground and (1+RT1/RPCET2)forV thisTref architecture as observed increases in with simulations.Pout,dc. For low This available startup input power, Pout,dc is low, VSS) are provided by the auxiliary rectifiers. To extend the situationresulting is similar in lower to the rectification situation efficiency of overdriving because MPCERP isin limited Fig. 2 by the quiescent power 1744 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 8, AUGUST 2015 range of VAC to about double of the maximum drain-to-source for largedissipation IL as in discussed the LDO and in other Section circuit 2. blocks. Similar overdriven voltage limits of the MOSFETs, MT1 and MB1 are added. For situations can also occur to MB2 in the n-prectulator. the positive cycle of V and, M downlink is on communication. with its source However, voltage, in future work, addi- To detect overdriven situations on M in Fig. 3, M is ACtionalT1 blocks for clock recovery, data processing and modula- T2 T3 VACT, following VAC. Fortion the should negative be implemented cycle of forVAC achieving, MT1 ais complete off. wirelessadded in the p-prectulator. When overdriven situations occur, VACT will stay at ~0V. Asdata a result, link. both MT1 and MT2 only see VGT2 is less than VOP – |VTP|. Hence, MT3 will turn on and

III. POWER RECOVERY ARCHITECTURE A power recovery and management circuit is required, along with a regulated output DC rail, for reliably powering data trans- mitters, sensors or stimulation circuits required in most implant applications. In this proof-of-concept design, we target a regulated DC output voltage of 1 V and a maximum DC output current of A, i.e., a maximum DC load power Fig. 5. Hybrid two-path architecture of the power recovery circuit. of W. The target peak AC input voltage range for Figure 14. Hybrid two-path architecture of the power recovery circuit proposed in [44]. Reproduced the power recovery circuit is 0.6–1.1 V, based on the threshold with permission from J. Chartad, IEEE Journal of Solid-State Circuits; published by IEEE, 2015. voltage of typical rectifiers and the breakdown voltage limit high switching frequency (30 MHz) for reducing the size of cou- of transistors. pling capacitors. In this path, the AC input voltage is first rec- A. Chip-Piezoelectric Receiver Interface tifiedtoaDCvoltage using a full-wave active rectifier. A high-frequency voltage doubler is then used to double this The fundamental component of the input resistance voltage to . Subsequently, a low dropout regulator (LDO), of a typical AC-DC power recovery circuit is approximately powered from , generates a constant DC rail .In given by parallel to the main path, we implement an auxiliary power path consisting of a push-pull voltage doubler that generates (1) an auxiliary DC rail for powering low power con- suming blocks, such as a constant-gm bias circuit and a ring where is the average input power of the IC and oscillator that drives the high-frequency doubler. Due to low is the efficiency of the AC-DC converter. For between output power of this path, the size of coupling capacitors re- 0.6–1.1 V, between 10–100 W, and between quired in the push-pull doubler need not be large. This architec- 30–70%, is between 0.5–42.4 k . The input impedance ture thus enables the generation of reference and clock signals also is comprised of a shunt capacitance, which includes the at low available powers during startup, while still supporting a parasitic capacitance of MOS transistors or diodes connected large load power, without compromising efficiency or using im- at the AC inputs. However, it can be ignored at the frequency practical values of coupling capacitors. of interest (1 MHz) and for the typical values of in this For high available input power, power conversion efficiency design. Thus, the resistances of the AC-DC converter and (PCE) for this architecture increases with up to the max- the piezoelectric receiver can be designed to lie in a similar imum sustainable .Forverylow , PCE is limited range ( k ), allowing us to forego a dedicated input matching by the quiescent power dissipation in the LDO and other cir- network, while still achieving good power transfer efficiencies. cuit blocks. For low available input power, is low, resulting in lower rectification efficiency. Techniques for improving the B. Power Recovery Circuit Architecture efficiency of the rectifier at low [32], [33], and implemen- A typical Dickson multiplier used for power recovery in this tation of an efficient and reconfigurable charge-pump [34] for design would require very large values of coupling capacitors minimizing the voltage drop across the LDO pass transistor, can due to low input frequency (1 MHz) and large A further improve the PCE across a wide range of input powers requirement [29]–[31]. The output DC voltage of a single- and load currents. stage Dickson multiplier is approximately given by ,where is the coupling capacitance and is IV. CIRCUIT IMPLEMENTATION the input frequency. For simplicity, the above equation assumes zero voltage drop across the diodes in the multiplier circuit and A. Power Recovery Circuits ignores the effect of diode parasitic capacitance. Based on the Fig. 6(a) shows a schematic of the full-wave active recti- above equation, if , Aand MHz, fier consisting of a gate cross-coupled NMOS pair and active then for achieving , for instance, the required value PMOS diodes operating as switches [35]. This topology enables of is 1 nF. Moreover, the load capacitance at node is low dropout voltage across the transistors, resulting in a high typically chosen to be an order of magnitude larger than PCE. The active PMOS diode uses a high-speed comparator [30], resulting in a very large on-chip area. with a common-gate input stage. Current sources of the com- Thus, in order to reduce the size of coupling capacitors, we parator are biased from the constant-gm bias circuit powered decouple the constraints of low and large by designing from the rail. Reliable startup of the active rectifier is, a power recovery circuit with a hybrid two-path architecture as thus, guaranteed since rail is generated using a passive shown in Fig. 5. In this architecture, the main power path is voltage doubler. Post-layout simulation of this rectifier results designed to support the large A and operate at a in a of 0.72 V for peak of 0.8 V and a load power Appl. Sci. 2021, 11, 2487 11 of 21

(d) (e)

Figure 15. Power recovery circuits in the main power path [44]: (a) active full-wave rectiﬁer and the comparator used in the active PMOS diode; (b) high-frequency voltage doubler; (c) LDO circuit and generation of the POR signal; (d) Push-pull voltage doubler circuit used in the auxiliary power path;

(e) Over-voltage protection circuit for VDC2 rail. Reproduced with permission from J. Chartad, IEEE Journal of Solid-State Circuits; published by IEEE, 2015.

In [45], a PMIC is presented that adopts a full-wave CMOS rectifier (NMOS active diode and cross-coupled PMOS) to convert AC to DC voltage and a newly developed multi-ratio switched-capacitor DC-DC regulator to provide a regulated output voltage. However, this solution works on an input voltage range of 1.9 V to 3.5 V. The solution proposed in [46] consists of the dual-mode rectifier, shown in Figure 16, to work well on wide range of input AC voltage and many blocks to improve PCE. This 2370topology solves the problem during start-up and for low input powerIEEE JOURNAL with a OF cross-coupled SOLID-STATE CIRCUITS, VOL. 50, NO. 10, OCTOBER 2015 passive rectifier for high input power an active diode rectifier is used.

Figure 16. Dual-mode rectiﬁer for PE transducer proposed in [46]. Reproduced with permission from M. Shim, IEEE Journal of Solid-State Circuits; published by IEEE, 2015.

Fig. 5. (a) Dual-mode rectiﬁer for PE transducer, (b) voltage and current waveforms of the dual-mode rectiﬁer, (c) cross-coupled mode and (d) active diode mode, (e) zero crossing detector, (f) beta multiplier.

a ramp signal with low power dissipation even if the supply prevent the undershoot problem when we compare the and voltage is changed. Using the ramp signal, a switch con- . The switching controller uses two comparators with troller generates control signals for a switching converter. The hundreds of nA. The reverse current and BD remover also use proposed system adopts the buck-boost topology because the the comparator and the switching driver to control the switches system uses a fixed duty cycle and covers the 1 V to 7 V input of the buck-boost controller. voltage range. If the system adopts a buck topology with 0.5 duty cycle, it causes a problem when the input voltage is near B. Dual-Mode Rectifier With Fast Start-Up 1 V because the output voltage becomes only 0.5 V. If we use Fig. 5(a) shows a schematic of the proposed dual mode recti- the boost topology with 0.5 duty cycle, the system needs to fier with cross-coupled MOSFETs and active diodes. The active use the high-voltage MOSFETs which can increase the chip rectifier for the PE system has problems at start-up or with low area and power consumption of the controller. The control input power from the harvester because is considerably blocks of the buck-boost converter also prevent the reverse low to operate the control blocks. To solve this problem, we leakage current and the body-diode (BD) effect [15]. The total propose an FB rectifier that adopts a cross-coupled passive rec- power dissipation of the controller is 10 W and the quiescent tifier with better performance in cold start or low input power, current of the analog block is 3 Aatthe of 2.7 V. instead of diode-connected MOSFETs. As shown in Fig. 5(c), The detailed power consumption is presented in Fig. 4. The cross-coupled MOSFETs using and voltages as control switching controller and dead-time controller dissipate the signals do not have a large drop compared to diode-con- half of the total power because it needs sufficient energy to nected MOSFETs. Therefore, it achieves a fast start-up and a

Authorized licensed use limited to: University of Catania. Downloaded on April 02,2020 at 17:06:09 UTC from IEEE Xplore. Restrictions apply. 644 F. Khateb, S. Vlassis / Microelectronics Journal 44 (2013) 642–648

when Vin24Vin1 then: input in1 and to the input ininv of the simple inverter. The inverted sinusoidal signal of the V is obtained from the output of the V g ; r g ; r g ; in1 β ¼ out ¼ mb M2 out02 m M5 out2 ≈ mb M2 ≈1 ð5Þ 02 þ simple inverter (outinv) and therefore the input signals of the V in2 1 gmb;M3 rout02 gm;M5 rout2 gmb;M3 BD-WTA circuit standalone will be V in2 ¼ −V in1. It should be noted where gm and gmb denote the gate and bulk transconductances of here that the constant voltage which is appeared at the output of

the MOS devices, respectively, e.g. gmb,M1 is the bulk transconduc- the inverter is adjusted to be equal to Vbias by appropriate selection tance of M1. It should be mentioned here that rout2 is the output of the aspect ratio of M12 and M13. The output voltage is expected resistance of the second stages and rout01, rout02 are the output to be given by: resistances of the first stages which are formed by the group of ( þ ω ; 4 V bias V m sin t V in1 V in2 transistors: M1, M3, M4, M7, M9 and M2, M3, M4, M8, M9, ¼ ð Þ V out þ ω ; ≤ 9 respectively. V bias V m sin t V in1 V in2 Thanks to the negative feedback the low impedance value of ¼ the out terminal is guaranteed and it is given by: Then, for positive half-wave Vout Vin1 and for negative half- wave Vin24Vbias then Vout ¼Vin2. Hence a full-wave rectifier is 1 1 obtained. Rout≈ jj ð6Þ gmb;M1rout01gm;M6 gmb;M2rout02gm;M5 It is obvious that the proposed circuit offers high input and low output impedances that are important requirements for the 4. Simulation results voltage-mode operation. The advantage of using a flipped voltage follower for the input The circuits were designed and simulated using TSMC 0.18 mm stage biasing against the tail current transistor of the conventional n-well CMOS process with single supply of 0.6 V. The used SPICE

bulk-driven input stage is the capability for operation under lower model is available on [42]. The bias voltage Vbias was 0.3 V (mid supply voltage [32]. Based on Fig. 2, the most critical path, supply) and the power consumption was 2.14 mW. The optimal regarding the minimum supply voltage, is formed by the stacked transistor aspect ratios and the bias components are given in

transistors M4 and M9. Therefore, the minimum supply VDD.min will Table 1. be given by: The DC transfer characteristic of the simple inverter of Fig. 4 is shown in Fig. 5. For input voltage range from 100 to 500 mV the V DD:min ¼ V GS;M4 þ V DS;M9 ð7Þ voltage error is below 4 mV, out of this range this error is

where VGS,M4 is the gate-source voltage of M4 and VDS,M9 is the dramatically increased. Therefore, using Vbias ¼0.3 V and maxi- drain- source voltage of the active load device M9. The proposed mum input amplitude Vm.max of 200 mV, the inverter is not WTA-BD circuit is more efficient regarding the minimum supply expected to have strong impact to the overall rectifier accuracy. requirement compared with conventional bulk-driven input stages Fig. 6 shows the DC transfer characteristic of BD-WTA rectifier achieving the same common-mode dynamic range. in comparison with the ideal one and it confirms the precise rectification for input amplitude ranging 200 mV. The voltage offset is only 0.026 mV, and the large-signal positive and negative 3. LV LP rectifier based on BD WTA slopes of the characteristic are 0.997 and 0.994, respectively. It should be noted here that the difference between two character- Fig. 3(a) shows the half-wave rectifier based on BD-WTA istic for Vin below 100 mV is due to the limitation of the simple ¼ þ circuit. At the input in1 the sinusoidal signal V in1 V bias inverter. ω Appl. Sci. 2021 11 V m sin t is applied and at the input in2 only the constant voltage , , 2487 V is applied, where V is the input amplitude. For maximum 12 of 21 bias m VDD input swing the voltage Vbias can be chosen equal VDD/2. Therefore, ¼ þ ω in the sinusoidal signal V in1 V bias V m sin t is compared with the inv M13 Vbias one, and the output voltage will be given by: ( V ¼ V þ V sin ωt; V 4V in1 bias m in1 bias outinv V out ¼ ð8Þ V bias The; systemV in1 ≤V bias works for a wide range of input voltage, with a minimum value equal to

So, for1 positiveV. However, half-wave V theout ¼V largein1 and or number negative half-wave of ancillary blocks need additional input power. o ¼ fi Vin1 Vbias thenInVout [47Vbias],. Hence it is a presented half-wave recti er a is half/full obtained. wave rectifier (FigureM 1217) based on a maximum Fig. 3(b) shows the circuit topology of the full-wave rectifier, which consistselector, of BD-WTA which with is bias based circuit and on a bulk-driven simple MOS comparator. This technique is very low-power, inverter. The circuit of a simple analog inverter is presented in nevertheless it works¼ þ underω several ten of kilohertz. Fig. 4. Simple MOS Inverter. Fig. 4. The sinusoidal signal V in1 V bias V m sin tstill applied to

V V V bias Vbias t t Vin1=Vbias+Vmsin t in1 Vin1=Vbias+Vmsint in1

BD-WTA out Vout Inverter BD-WTA out Vout V Vin2=Vbias in2 V V in2 V V bias Vbias Vbias Vbias t t t t

Fig. 3. BD-WTA half-wave (a) and full-wave rectiﬁer (b). Figure 17. BD-WTA half-wave (a) and full-wave rectiﬁer (b) proposed in [47]. Reproduced with permission from F. Khateb, Microelectronics Journal; published by Elsevier, 2013.

A half-wave active rectifier is proposed in [48]. Figure 18 shows the circuit diagram of the single-stage half-wave active rectifier made up of a start-up rectifier, a half-wave rectifier, a comparator, a buffer and a power switch.

Figure 18. Circuit diagram of the single-stage active rectiﬁer realized in [48]. Reproduced with permission from F. Mazzilli, IEEE Transactions on Biomedical Circuits and Systems; published by IEEE, 2014.

The active rectifiers exploit a fast comparator to directly control the gate of PMOS transistors to reduce reverse current leakage from the output load to the input. In standard cross-coupled topology, full-wave input voltage is applied between the gate and source of all transistors. Consequently, PMOS and NMOS transistors will turn on/off roughly at the same time which creates a leakage path from load to source. To prevent leakage currents rectifier should only turn on when the input voltage is higher than the load voltage. For this reason, ref. [41] proposes a rectifier topology (Figure 19) where the turn on/off voltage level of rectifier is controlled by applying independent bias voltage to the NMOS transistors. At the same time, this solution requires high-input voltage (from 1.6 V to 3.6 V).

Appl. Sci. 2021, 11, 2487 13 of 21 Figure 4. Active rectifier with voltage comparators.

Figure 3. Simulated voltage and current waveforms of standard cross coupled topology. current only in one direction and consequently can prevent leakage currents. However, this configuration has poor PCE because to turn on each transistor a forward voltage drop of Figure 19. Rectifier proposed in [41]. Reproduced with permission from M. A. Ghanad, IEEE larger than transistor threshold voltage (VTH) is required. Using transistors in switching mode reduces the voltage drop FigureProceedings; 5. Proposed published rectifier. by IEEE, 2012. across them (fig. 2b). On the other hand, a switch is unable to Work in [49] presents an active rectifier with SAR-assisted coarse-fine adaptive digital control the direction of current flow and reverse leakage Fordelay practical compensation implementations technique for biomedical offset voltage implantable and devices. delay Both of the on- and off-delay currents will flow whenever the transistor is on and the load comparatorsare compensated degrade by adjusting the theperformance comparator offset.[7]. InThe order comparator to achieve accurate zero- potential is higher than the source potential. The problem of voltage switching against process, voltage, and temperature variations (PVT), a two-step speedcoarse-fine also digital limits tuning the methodoperation is introduced. frequency of the rectifier. To reverse leakage currents is studied in [5]. To explain the achieveThe high architecture PCE, ofpower adaptive consumption digital on/off of delay comparators compensation should loop for the power problem, voltage and current waveforms of the cross coupled beswitch small M Nfraction1 is shown of in delivered Figure 20. The DC loop power. consists For of a ultra sampled low block, power a detection circuit, rectifier of fig. 2b are depicted in fig 3. A sinusoidal input implantsan offset regulatoror high and afrequency gate signal generator.links the This active solution couldrectifier avoid is reverse current voltage with peak value of 2.1 V and frequency of 13.56 MHz ineffectiveand achieve maximumas the conductionpower timeconsumption for power switches. of comparators is applied in simulations and 23 pF and 9.1 KΩ are used as becomes comparable with the required power for processing C and R respectively. In fig. 3 all node voltages except V Rec L IN blocks. are shown with respect to rectifier ground. In positive half cycle, once the input voltage becomes larger than VTHN, MP1 ROPOSED ECTIFIER and MN2 are turned on. In this situation, the load has higher III. P R potential than the source and reverse leakage currents will In standard cross coupled topology the entire input voltage is flow from the load (green areas in fig. 3). As the input voltage applied between the gate and source of all transistors. exceeds the load voltage, rectifier starts to charge the load up Consequently PMOS and NMOS transistors will turn on/off to the point that the input voltage reaches to its peak value. roughly at the same time which creates a leakage path from When the input voltage decreases from its peak, the transistors load to source. To prevent leakage currents rectifier should are still on and the leakage current again discharges the load only turn on when the input voltage is higher than the load (yellow areas in fig. 3). Eventually, MN2 will turn off when the voltage.Figure 20. InArchitecture the proposed of digital delaytopology compensation (fig. loop5), proposedthe turn in [on/off49]. Reproduced with input voltage goes below VTHN. The rectifier shows similar voltagepermission level from of Y. Ma, rectifier IEEE Solid-State is controlled Circuits Letters; by applying published independent by IEEE, 2020. behavior in negative cycle of the input voltage waveform bias voltageThe rectifier to proposedthe NMOS in [50 transistors.], whose scheme The is depictedoutput involtage Figure 21is, consists of a except MP2 and MN1 are conducting during this cycle. In dividedCMOS passive to create rectifier the with bias active voltage bias tuning and (ABT), the allowingdivision a widelyratio extendedis input addition to degrading the PCE of rectifier, the leakage currents determinedrange with high according power conversion to the targeted efficiency. output voltage level. The increase the ripples of the rectified voltage. A larger external capacitorsThe ABT have is a digitalsmall circuit time which constant has two relative functions: to maintain the operation high PCE and regulate capacitor is required to suppress the ripples which is not frequencyVOUT by searching and instantly (Figure 22 couple). In particular, fraction in of closed-loop the input the voltage control senses to VOUT and desirable for size constrained implants. compare it with its previous value. The comparison result directs a finite-state machine the(FSM) gates to signalof NMOS either “charge” transistors. or “discharge” The capacitors to the switched-capacitor are optimized charge pump. Active rectifiers are reported to prevent leakage currents toThis only solution turn on is only theconvenient NMOS transistors if several cross-coupled around the structures peak value are cascaded. of In fact, [6]. Fig. 4 shows an active rectifier in which the comparators themeasurement input voltage. results ofFor three low chips current show that loads, this rectifier the voltage improves thedropsPCE over a wide input range, with a maximum value equal to 64.4%. detect the polarity of voltage difference between the drain and across transistors are lower than the turn on voltage of drain source of NMOS transistors. The NMOS transistors are turned bulk diodes, therefore active body biasing techniques are not on only when the voltage of their sources which is connected required for this design. Fig. 6a shows the operation voltage to the input terminals goes below the ground. This can result and current waveforms of the proposed rectifier with the same in unidirectional current flow to the load. simulation conditions as of fig. 3. The operation of the rectifier can be divided to different phases according to the

521 Appl. Sci. 2021, 11, 2487 14 of 21

Figure 21. Cross Coupled rectiﬁer with active bias tuning proposed in [50]. Reproduced with permission from X. Li, IEEE Journal of Solid-State Circuits; published by IEEE, 2020.

Figure 22. Single stage of the switched-capacitor-based charge pump integrator for ABT.

An active rectiﬁer with digitally controlled on-off delay-compensated for biomedical application is introduced in [51]. It consists of two NMOS active diodes and a cross-coupled PMOS transistor-pair (Figure 23). High efﬁciency is achieved by digital techniques that eliminate turn-on delay, reverse current and multiple pulsing. Appl. Sci. 2021, 11, 2487 15 of 21

Figure 23. (a) Circuit implementation of digitally controlled on-off delay compensated full-wave rectiﬁer and (b) control logic present in [51]. Reproduced with permission from S- Pal, IEEE Transactions on Circuits and System II: Express Briefs; published by IEEE, 2020.

4. Performance Comparison The choice of a specific rectifier topology depends upon the specific application, the used technology, and design specifications. The choice of a specific rectifier topology can be firstly done according to the input voltage range, as suggested in the following. • In ultra-low input voltage range (0.1–0.6 V) applications, such as micro-scale and battery-less biomedical implants, body driven circuits represent a good option because the threshold voltage of transistor is often relatively high and body driven topologies overcome this problem. Moreover, boost converters are often mandatory to adapt the rectified voltage at the levels conventionally required for functional block operations. • For low input voltage range (0.6–1.2 V) applications, passive rectifiers, such as cross- coupled and voltage doubler, are a good choice because the transistors work suffi- ciently well without additional circuits (that would reduce the PCE). • For mid and high input voltage range (higher than 1.2 V) applications, active rectifier topologies represent the best choice to optimize its performance in terms of power consumption (i.e., PCE). The solutions for implanted medical devices previously analyzed are compared in Table1. Please note that the data shown in the table do not refer only to the adopted rectifier but to the overall PMIC. In Table1, PCE and VCR are respectively defined as

2 P V /RL PCE = OUT · 100 = DC · 100 (1) R t0+N·T PIN 1 V (t) · I (t)dt N·T t0 AC AC Appl. Sci. 2021, 11, 2487 16 of 21

V VCR = OUT · 100 (2) VOUT,id

where VDC is the averaged rectified output DC voltage, RL is the output resistive load, T is the period of the input sinusoidal signal, N · T is the integration range over PIN is calculated, and VAC(t), IAC(t) are the instantaneous voltage and current of the AC input source, Vout and Vout,id are the actual and ideal output voltage of the system. Analysis of data reported in Table1 reveals that the body driven rectifier proposed in [47] is the only solution for ultra-low input voltage range. However, such result was accomplished because the proposed BD-WTA is supplied by an auxiliary power source whose voltage is higher than the input signal amplitude. Actually, the circuit works as comparator where the resulting output voltage is always the maximum between the two inputted signals. Main drawbacks and limits of this circuit are strictly related to the needed of auxiliary supply and biasing sources and the use of the body-driven approach which allows working on very-low voltage input signals but limits their maximum amplitude values. Definetively, comparator in [47] is particularly suited as envelope detector for applications where the input signal amplitude contains information to be extracted, such as amplitude modulation receiver. On the other hand, the features of [44] confirm that active topologies are not suitable for low input voltage range since they have PCE < 60%. Reasons of the relatively low power performance can be found in the loss of speed and driving capability of the auxiliaries, such as comparators and bias generators, when the transistors are constricted to work in sub-threshold region. This confirms the categorization done before, since typical values for the threshold voltage of a regular MOSFET is about 600 mV. The analysis of solutions in [35,41,45,48–51] further confirm the validity of the guidelines provided above, suggesting that mixed approaches are needed to extend the input voltage range. As a proof, the mixed rectifier, constituted by cross-coupled and active diode proposed in [46] allows functions in a wide input voltage range due to the adaptive configuration of the rectifier. Figure 24a reports PCE versus the maximum output power density, defined as the ratio between the maximum output power and area occupation for all the solutions in Table1 . It is apparent that [51] shows the best performance due to the higher value of PCE and output power density, while occupying much more area than [45]. High power efficiency of solution in [51] is reached thanks to an on-off delay compensation implemented through a digital control circuit. As claimed by the authors, Pal et al., the comparator and logic losses affects the total power breakdown for less than 1%, allowing obtaining a reduction of the losses, associated to rectifier, limited in the range of some percentile points. The achieved results prove that the use of digital-based circuitry to control switching activity of the active diodes is a captivating solution for high-power super-threshold IMD applications. Figure 24b shows the maximum output power density versus the input voltage. By inspection of this figure, it is apparent that the solution reported in [46] achieves a low value of maximum supply voltage (1.1 V) but it has the lowest output power density. Consequently, its performance is lower than [35,49,51]. The best performance is therefore achieved by the solutions proposed in [35,49,51]. Appl. Sci. 2021, 11, 2487 17 of 21

Table 1. Comparison of different rectiﬁers.

[35] S [44] S [45] S [46] S [47] R [48] R [41] R [49] S [50] S [51] S Transducer Magnetic Piezo Piezo Piezo Piezo Piezo Magnetic Magnetic Piezo Piezo Process (nm) 65 65 350 350 180 180 180 180 65 130 Rectiﬁer topology active active active passive + active passive active passive active passive active frequency (MHz) 13.56 1 1.5 0.09 0.2 1 13.56 13.56 200 40.68 Input voltage (V) 1.3–2.5 0.6–1.1 1.9–3.5 1–7 0.25–0.6 3–6.54 1.6–3.6 1.5–2 0.3–1.8 1–1.5 VOUT,max (V) 2.44 1 4 8 6.29 5.15 1.8 – 1.78 – POUT,max (mW) 248.1 0.1 40 * 1 – 25 3 54 1.58 9 PCEmax 94.6% 54% 83% 80% – 83.81% 81% 92.6% 64.4% 94% VCEmax 97.7% 99% – 99% – 78.74% 74% 95.7% 80% 97% Fully integrated yes yes no no no yes yes yes yes yes Area (mm2) 1.44 2 0.4 5.52 – 0.114 0.03 0.203 0.384 0.166 *: valued as indicated in the paper. R,S: data referring to Rectiﬁer or System. Appl. Sci. 2021, 11, 2487 18 of 21

Figure 24. Performance comparison, (a) PCE versus minimum output power density and (b) output

power density versus Vin. 5. Conclusions In this work, a review of several solutions of ultrasound-based energy harvesters for implantable devices is presented. After a general presentation of the widely adopted topologies which constitute the core of the power management section, the state-of-the-art has been reviewed and the various solutions have been compared. Historically, the AC–DC converter topologies have evolved to cope with technological progress, thus satisfying increasingly stringent constraints given by current applications (e.g., low input voltage and high power efficiency). Quantitative comparison of the state-of-the-art reveals that the choice of a particular topology is strongly dependent upon the design constraints, especially the amplitude of the AC input signal. A first analysis of the various works reveals that applications can be roughly distin- guished in three categories based on the input voltage range. In the bottom-side range, electrical features of most Metal-Oxide-Silicon transistors are strongly degraded and limited by their threshold voltages. In these cases, the use of body-driven approach and auxiliary boosting systems, such as charge pumps, are mandatory. In the middle range (i.e., from 0.6 to 1.2 V), conventional topologies are better choice because reach good performance without the additional circuits, thus without further power losses. On the other hand, architectures with modified active diodes are the better solutions when the input signals have high amplitude values. Concluding, a mixed approach where the main Appl. Sci. 2021, 11, 2487 19 of 21

topology can be switched from the conventional to the active topology by means of light control circuits appears to be the right way to run in order to achieve high PCEs and wide input voltage ranges. With this in mind, particular attention must be given to the design of auxiliary circuits, such as comparators and kick start systems, whose power consumption may seriously degrade the power conversion efficiency of the overall harvester. On this way, digital-based control circuits are promising solutions, since they are power scalable, especially if the frequency is in the range of the MHz, and robustly work also under low voltage conditions. Operation of energy harvesting applications with input voltages lesser than the needed for IMD suppling opens up the progress of new topologies and, mainly, on the voltage booster adopted. At this purpose, the use of low-threshold devices, if available, can be considered, but the potential power efficiency reduction due to their high leakage current should be taken into consideration. On the other hand, the use of standard-threshold devices working in the sub-threshold region leads to a reduced charge transfer capability. In this case, higher efficiency can be acquired at the cost of a larger area of active devices. When the amplitude of the input voltage is higher than the output DC voltage, active devices are recommended because they allow optimizing the conduction phase while reducing current leakage, thus improving the power transfer to the load.

Author Contributions: Conceptualization: A.B. and A.D.G.; data curation, A.B. and M.B.; original draft preparation: A.B. and M.B.; writing, review and editing: A.B. and A.D.G.; formal analysis: all authors; supervision: A.B. and A.D.G. All authors have read and agreed to the published version of the manuscript. Funding: This research has been funded by the Brain28nm Project (Prot. 20177MEZ7T)-Italian Minister of University and Research. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Greatbatch, W.; Holmes, C.F. History of implantable devices. IEEE Eng. Med. Biol. Mag. 1991, 10, 38–41. [CrossRef] 2. Katic, J. Highly-Efﬁcient Energy Harvesting Interfaces for Implantable Biosensors. Doctoral Dissertation, KTH Royal Institute of Technology, Stockholm, Sweden, 2017. 3. Amar, A.B.; Kouki, A.B.; Cao, H. Power Approaches for Implantable Medical Devices. Sensors 2015, 15, 28889–28914. [CrossRef] 4. Nandish, M.B.; Hosamani, B. A Review of Energy Harvesting From Vibration using Piezoelectric Material. Int. J. Eng. Res. Technol. 2014, 1607. 5. Taalla, R.V.; Areﬁn, M.S.; Kaynak, A.; Kouzani, A.Z. A Review on Miniaturized Ultrasonic Wireless Power Transfer to Implantable Medical Devices. IEEE Access 2019, 7, 2092–2106. [CrossRef] 6. Ballo, A.; Grasso, A.D.; Palumbo, G. A Review of Charge Pump Topologies for the Power Management of IoT Nodes. Electronics 2019, 8, 480. [CrossRef] 7. Basaeri, H.; Christensen, D.B.; Roundy, S. A review of acoustic power transfer for bio-medical implants. Smart Mater. Struct. 2016, 25, 123001. [CrossRef] 8. Ballo, A.; Bottaro, M.; Grasso, A.D.; Palumbo, G. Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS. Electronics 2020, 9, 998. [CrossRef] 9. Denisov, A.; Yeatman, E. Ultrasonic vs. Inductive Power Delivery for Miniature Biomedical Implants. In Proceedings of the 2010 International Conference on Body Sensor Networks, Singapore, 7–9 June 2010; pp. 84–89. [CrossRef] 10. Zhou, Y.; Liu, C.; Huang, Y. Wireless Power Transfer for Implanted Medical Application: A Review. Energies 2020, 13, 2837. [CrossRef] 11. Jiang, D.; Shi, B.; Ouyang, H.; Fan, Y.; Wang, Z.L.; Li, Z. Emerging Implantable Energy Harvesters and Self-Powered Implantable Medical Electronics. ACS Nano 2020, 14, 6436–6448. [CrossRef] 12. Zhao, J.; Ghannam, R.; Htet, K.O.; Liu, Y.; Law, M.K.; Roy, V.A.L.; Michel, B.; Imran, M.A.; Heidari, H. Self-Powered Implantable Medical Devices: Photovoltaic Energy Harvesting Review. Adv. Healthc. Mater. 2020, 9, 2000779. [CrossRef] 13. Kumar, P.M.; Jagadeesh Babu, V.; Subramanian, A.; Bandla, A.; Thakor, N.; Ramakrishna, S.; Wei, H. The Design of a Thermoelec- tric Generator and Its Medical Applications. Designs 2019, 3, 22. [CrossRef] Appl. Sci. 2021, 11, 2487 20 of 21

14. Selvarathinam, J.; Anpalagan, A. Energy Harvesting From the Human Body for Biomedical Applications. IEEE Potentials 2016, 35, 6–12. [CrossRef] 15. Ballo, A.; Grasso, A.D.; Palumbo, G. A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start. IEEE Access 2020, 8, 188959–188969. [CrossRef] 16. Yang, Y.; Dong Xu, G.; Liu, J. A Prototype of an Implantable Thermoelectric Generator for Permanent Power Supply to Body Inside a Medical Device. J. Med. Devices 2013, 8.[CrossRef] 17. Meng, M.; Kiani, M. Design and Optimization of Ultrasonic Wireless Power Transmission Links for Millimeter-Sized Biomedical Implants. IEEE Trans. Biomed. Circuits Syst. 2017, 11, 98–107. [CrossRef][PubMed] 18. Das, R.; Moradi, F.; Heidari, H. Biointegrated and Wirelessly Powered Implantable Brain Devices: A Review. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 343–358. [CrossRef] 19. Barbruni, G.L.; Ros, P.M.; Demarchi, D.; Carrara, S.; Ghezzi, D. Miniaturised Wireless Power Transfer Systems for Neurostimula- tion: A Review. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 1160–1178. [CrossRef][PubMed] 20. Ibrahim, A.; Meng, M.; Kiani, M. A Comprehensive Comparative Study on Inductive and Ultrasonic Wireless Power Transmission to Biomedical Implants. IEEE Sens. J. 2018, 18, 3813–3826. [CrossRef] 21. Agarwal, K.; Jegadeesan, R.; Guo, Y.; Thakor, N.V. Wireless Power Transfer Strategies for Implantable Bioelectronics. IEEE Rev. Biomed. Eng. 2017, 10, 136–161. [CrossRef] 22. Arbabian, A.; Chang, T.C.; Wang, M.L.; Charthad, J.; Baltsavias, S.; Fallahpour, M.; Weber, M.J. Sound Technologies, Sound Bodies: Medical Implants with Ultrasonic Links. IEEE Microw. Mag. 2016, 17, 39–54. [CrossRef] 23. Shi, C.; Costa, T.; Elloian, J.; Zhang, Y.; Shepard, K.L. A 0.065-mm3 Monolithically-Integrated Ultrasonic Wireless Sensing Mote for Real-Time Physiological Temperature Monitoring. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 412–424. [CrossRef][PubMed] 24. Manbachi, A.; Cobbold, R.S.C. Development and Application of Piezoelectric Materials for Ultrasound Generation and Detection. Ultrasound 2011, 19, 187–196. [CrossRef] 25. Seeman, M.D.; Ng, V.W.; Le, H.; John, M.; Alon, E.; Sanders, S.R. A comparative analysis of Switched-Capacitor and inductor- based DC-DC conversion technologies. In Proceedings of the 2010 IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL), Boulder, CO, USA, 28–30 June 2010; pp. 1–7. [CrossRef] 26. Ballo, A.; Grasso, A.D.; Palumbo, G. Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging. IEEE Trans. Circuits Syst. II Express Briefs 2020.[CrossRef] 27. Ballo, A.; Grasso, A.D.; Palumbo, G. A simple and effective design strategy to increase power conversion efficiency of linear charge pumps. Int. J. Circuit Theory Appl. 2020, 48, 157–161. [CrossRef] 28. Ballo, A.; Grasso, A.D.; Palumbo, G. Current-mode body-biased switch to increase performance of linear charge pumps. Int. J. Circuit Theory Appl. 2020, 48, 1864–1872. [CrossRef] 29. Lu, Y.; Ki, W.H. CMOS Integrated Circuit Design for Wireless Power Transfer; Analog Circuits and Signal Processing; Springer: Singapore, 2018. [CrossRef] 30. Shigeta, Y.; Yamamoto, T.; Fujimori, K.; Sanagi, M.; Nogi, S.; Tsukagoshi, T. Development of ultrasonic wireless power transmission system for implantable electronic devices. In Proceedings of the 2009 European Wireless Technology Conference, Rome, Italy, 28–29 September 2009; pp. 49–52. 31. Ye, J.; Tanzawa, T. An Optimum Design of Clocked AC-DC Charge Pump Circuits for Vibration Energy Harvesting. Electronics 2020, 9, 2031. [CrossRef] 32. Ballo, A.; Grasso, A.D.; Giustolisi, G.; Palumbo, G. Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 1977–1981. [CrossRef] 33. Ballo, A.; Grasso, A.D.; Palumbo, G.; Tanzawa, T. Linear distribution of capacitance in Dickson charge pumps to reduce rise time. Int. J. Circuit Theory Appl. 2020, 48, 555–566. [CrossRef] 34. Maleki, T.; Cao, N.; Song, S.H.; Kao, C.; Ko, S.; Ziaie, B. An Ultrasonically Powered Implantable Micro-Oxygen Generator (IMOG). IEEE Trans. Biomed. Eng. 2011, 58, 3104–3111. [CrossRef][PubMed] 35. Huang, C.; Kawajiri, T.; Ishikuro, H. A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants. IEEE J. Solid-State Circuits 2016.[CrossRef] 36. Almansouri, A.S.; Kosel, J.; Salama, K.N. A Dual-Mode Nested Rectifier for Ambient Wireless Powering in CMOS Technology. IEEE Trans. Microw. Theory Tech. 2020, 68, 1754–1762. [CrossRef] 37. Guo, S.; Lee, H. An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants. IEEE J. Solid State Circuits 2009, 44, 1796–1804. [CrossRef] 38. Chang, R.C.; Chen, W.; Hsiao, W. A high-performance AC-DC rectifier with fully actively controlled switches for vibration energy harvesting. In Proceedings of the 2017 IEEE Wireless Power Transfer Conference (WPTC), Taipei, Taiwan, 10–12 May 2017; pp. 1–4. [CrossRef] 39. Chang, R.C.H.; Chen, W.C.; Liu, L.; Cheng, S.H. An AC–DC Rectifier With Active and Non-Overlapping Control for Piezoelectric Vibration Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 2020, 67, 969–973. [CrossRef] 40. Huang, L.; Murray, A.; Flynn, B.W. A High-Efficiency Low-Power Rectifier for Wireless Power Transfer Systems of Deep Micro-Implants. IEEE Access 2020, 8, 204057–204067. [CrossRef] Appl. Sci. 2021, 11, 2487 21 of 21

41. Ghanad, M.A.; Dehollain, C. A passive CMOS rectifier with leakage current control for medical implants. In Proceedings of the 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 9–12 December 2012; pp. 520–523. [CrossRef] 42. Laursen, K.; Rashidi, A.; Hosseini, S.; Mondal, T.; Corbett, B.; Moradi, F. Ultrasonically Powered Compact Implantable Dust for Optogenetics. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 583–594. [CrossRef] 43. Lee, E.K.F. A voltage doubling passive rectifier/regulator circuit for biomedical implants. In Proceedings of the 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 28–30 September 2015; pp. 1–4. [CrossRef] 44. Charthad, J.; Weber, M.J.; Chang, T.C.; Arbabian, A. A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link. IEEE J. Solid-State Circuits 2015, 50, 1741–1753. [CrossRef] 45. Zhang, X.; Lee, H.; Guo, S. A power- and area-efficient integrated power management system for inductively-powered biomedical implants. In Proceedings of the 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS), San Diego, CA, USA, 10–12 November 2011; pp. 213–216. [CrossRef] 46. Shim, M.; Kim, J.; Jeong, J.; Park, S.; Kim, C. Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time. IEEE J. Solid-State Circuits 2015, 50, 2367–2379. [CrossRef] 47. Khateb, F.; Vlassis, S. Low-voltage bulk-driven rectifier for biomedical applications. Microelectron. J. 2013, 44, 642–648. j.mejo.2013.04.009. [CrossRef] 48. Mazzilli, F.; Lafon, C.; Dehollain, C. A 10.5 cm Ultrasound Link for Deep Implanted Medical Devices. IEEE Trans. Biomed. Circuits Syst. 2014, 8, 738–750. [CrossRef][PubMed] 49. Ma, Y.; Cui, K.; Ye, Z.; Sun, Y.; Fan, X.Y. A 13.56-MHz Active Rectifier With SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices. IEEE Solid-State Circuits Lett. 2020.[CrossRef] 50. Li, X.; Mao, F.; Lu, Y.; Martins, R.P. A VHF Wide-Input Range CMOS Passive Rectifier With Active Bias Tuning. IEEE J. Solid-State Circuits 2020, 55, 2629–2638. [CrossRef] 51. Pal, S.; Ki, W.H. 40.68 MHz Digital On-Off Delay-Compensated Active Rectifier for WPT of Biomedical Applications. IEEE Trans. Circuits Syst. II Express Briefs 2020, 67, 3307–3311. [CrossRef]