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Embedded Processors on FPGA: Hard-Core Vs Soft-Core Vivek J
Implementation, Verification and Validation of an Openrisc-1200
Openpiton: an Open Source Manycore Research Framework
Implementing Post-Quantum Cryptography on Embedded Microcontrollers
FPGA Architecture: Survey and Challenges Full Text Available At
Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
Evaluation of Synthesizable CPU Cores
An Evaluation of Soft Processors As a Reliable Computing Platform
High Performance Embedded Computing in Space
Open-Source 32-Bit RISC Soft-Core Processors
A High Performance Microprocessor with Dsp Extensions Optimized for the Virtex-4 Fpga
A Multithreaded Soft Processor for Sopc Area Reduction
0001012870-00-001494.Pdf
Basic Custom Openrisc System Hardware Tutorial
A Multicore Computing Platform for Benchmarking
Virtex 4 Ethernet Ethernet I/F Transceiver FLASH/ SRAM 32/64 Bit PCI Interface Power and 5V Regulation Memory Expansion User I/O
HW/SW Co-Engineering in ECSS-E-ST-40C Rev1 and ECSS-E-ST-20-40C Standards
Top View
WP402: Considerations Surrounding Single Event Effects in Fpgas
On-Board Software Technology Trends in Space Applications
Opensparc™ Internals
Architectural Performance Analysis of FPGA Synthesized LEON Processors Corentin Damman, Gregory Edison, Fabrice Guet, Eric Noulard, Luca Santinelli, Jérôme Hugues
Introducing Open Source Hardware in Computer Engineering Courses
Rad-Tolerant/Rad-Hard Integrated Circuits
Introducing Laboratories with Soft Processor Cores Using Fpgas Into
Implementation of a Radiation-Tolerant Computer
Implementation of a Real-Time Computer for Space Applications Master of Science Thesis Embedded Electronic System Design
Intel® Iot RFP Ready Kit Solutions Playbook
LEON-G1 Series Quad-Band GSM/GPRS Data & Voice Modules System Integration Manual
Small Soft Core up Inventory Opencore and Other Soft Core Processors Only Cores in the "Usable" Category Included
The Case for RISC-V
QUARTERLY REPORT PURSUANT to SECTION 13 OR 15 (D) of the SECURITIES EXCHANGE ACT of 1934
LEON 3FT to Sμmmit Interface
Basic Custom Openrisc System Hardware Tutorial
ITEE Journal Information Technology & Electrical Engineering
Processor Overview
RTEMS CPU Architecture Supplement Release 6.7B289f6 (23Th September 2021) © 1988, 2020 RTEMS Project and Contributors
Opencore and Other Soft Core Processors up Cores Test Folder
A Genetic Algorithm for ASIC Floorplanning
A RISC-V Processor Design for Transparent Tracing
United States Securities and Exchange Commission
Opencore and Other Soft Core Processors
The Open Linux-On-Chip System
Standard PCI LEON Virtex-5.Ai
The Soft Core Processors: a Review
LPC20 Soc Support in the Kernel
Noel-V/Grlib
Sixteen Years After the Passage of the US Semiconductor Chip Protection
Softcore HDL Processor for Implementation in FPGA and ASIC
Small Soft Core up Inventory Opencore and Other Soft Core Processors Only Cores in the "Usable" Category Included
Introduction of Fault-Tolerant Concepts for RISC-V in Space Applications (RV4S) Final Presentation ESA/ESTEC Contract 4000123876/18/NL/CRS
Trends and Patterns of ASIC and FPGA Use in European Space Missions
Building a Soc for Industrial Applications Based on LEON Microprocessor and a GNU/Linux Distribution
A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration" (2006)
A Genetic Algorithm for Asic Floorplanning
LEON/GRLIB Design and Configuration Guide
Small Soft Core up Inventory ©2014 James Brakefield Opencore and Other Soft Core Processors
Revisiting the High-Performance Reconfigurable Computing For
LEON-PF User's Manual
Embedded Linux on Fpgas for Fun and Profit
Open Source Hardware Development and the Openrisc Project
Comparison of Synthesizable Processor Cores
Hardware/Software Co-Design for Matrix Inversion
Conversion Study of Leon3 Processor Core from SPARC
Intel® Technology Journal Compute-Intensive, Highly Parallel Applications and Uses