DOCSLIB.ORG

RTEMS CPU Architecture Supplement Release 6.7B289f6 (23Th September 2021) © 1988, 2020 RTEMS Project and Contributors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
RTEMS CPU Architecture Supplement Release 6.7B289f6 (23Th September 2021) © 1988, 2020 RTEMS Project and Contributors RTEMS CPU Architecture Supplement Release 6.7b289f6 (23th September 2021) © 1988, 2020 RTEMS Project and contributors CONTENTS 1 Preface 3 2 Port Specific Information5 2.1 CPU Model Dependent Features...........................6 2.1.1 CPU Model Name...............................6 2.1.2 Floating Point Unit..............................6 2.2 Multilibs........................................8 2.3 Calling Conventions..................................9 2.3.1 Calling Mechanism..............................9 2.3.2 Register Usage.................................9 2.3.3 Parameter Passing...............................9 2.3.4 User-Provided Routines............................9 2.4 Memory Model..................................... 10 2.4.1 Flat Memory Model.............................. 10 2.5 Interrupt Processing.................................. 11 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 13 2.7 Symmetric Multiprocessing.............................. 14 2.8 Thread-Local Storage................................. 15 2.9 CPU counter...................................... 16 2.10 Interrupt Profiling................................... 17 2.11 Board Support Packages................................ 18 2.11.1 System Reset................................. 18 3 ARM Specific Information 19 3.1 CPU Model Dependent Features........................... 20 3.1.1 CPU Model Name............................... 20 3.1.2 Count Leading Zeroes Instruction...................... 20 3.1.3 Floating Point Unit.............................. 20 3.2 Multilibs........................................ 21 3.3 Calling Conventions.................................. 22 3.4 Memory Model..................................... 23 3.5 Interrupt Processing.................................. 24 3.5.1 Interrupt Levels................................ 24 3.5.2 Interrupt Stack................................ 24 3.6 Default Fatal Error Processing............................. 25 i 3.7 Symmetric Multiprocessing.............................. 26 3.8 Thread-Local Storage................................. 27 4 Atmel AVR Specific Information 29 4.1 CPU Model Dependent Features........................... 30 4.1.1 Count Leading Zeroes Instruction...................... 30 4.2 Calling Conventions.................................. 31 4.2.1 Processor Background............................ 31 4.2.2 Register Usage................................. 31 4.2.3 Parameter Passing............................... 31 4.3 Memory Model..................................... 32 4.4 Interrupt Processing.................................. 33 4.4.1 Vectoring of an Interrupt Handler...................... 33 4.4.2 Disabling of Interrupts by RTEMS...................... 33 4.4.3 Interrupt Stack................................ 33 4.5 Default Fatal Error Processing............................. 34 4.6 Symmetric Multiprocessing.............................. 35 4.7 Thread-Local Storage................................. 36 4.8 Board Support Packages................................ 37 4.8.1 System Reset................................. 37 5 Blackfin Specific Information 39 5.1 CPU Model Dependent Features........................... 40 5.1.1 Count Leading Zeroes Instruction...................... 40 5.2 Calling Conventions.................................. 41 5.2.1 Processor Background............................ 41 5.2.2 Register Usage................................. 41 5.2.3 Parameter Passing............................... 41 5.3 Memory Model..................................... 42 5.4 Interrupt Processing.................................. 43 5.4.1 Vectoring of an Interrupt Handler...................... 43 5.4.2 Disabling of Interrupts by RTEMS...................... 43 5.4.3 Interrupt Stack................................ 43 5.5 Default Fatal Error Processing............................. 44 5.6 Symmetric Multiprocessing.............................. 45 5.7 Thread-Local Storage................................. 46 5.8 Board Support Packages................................ 47 5.8.1 System Reset................................. 47 6 Epiphany Specific Information 49 7 Intel/AMD x86 Specific Information 51 7.1 CPU Model Dependent Features........................... 52 7.1.1 bswap Instruction............................... 52 7.2 Calling Conventions.................................. 53 7.2.1 Processor Background............................ 53 7.2.2 Calling Mechanism.............................. 53 7.2.3 Register Usage................................. 53 7.2.4 Parameter Passing............................... 53 7.3 Memory Model..................................... 54 7.3.1 Flat Memory Model.............................. 54 7.4 Interrupt Processing.................................. 55 ii 7.4.1 Vectoring of Interrupt Handler........................ 55 7.4.2 Interrupt Stack Frame............................ 55 7.4.3 Interrupt Levels................................ 55 7.4.4 Interrupt Stack................................ 56 7.5 Default Fatal Error Processing............................. 57 7.6 Symmetric Multiprocessing.............................. 58 7.7 Thread-Local Storage................................. 59 7.8 Board Support Packages................................ 60 7.8.1 System Reset................................. 60 7.8.2 Processor Initialization............................ 60 8 Lattice Mico32 Specific Information 63 8.1 CPU Model Dependent Features........................... 64 8.2 Register Architecture................................. 65 8.3 Calling Conventions.................................. 66 8.3.1 Calling Mechanism.............................. 66 8.3.2 Register Usage................................. 66 8.3.3 Parameter Passing............................... 66 8.4 Memory Model..................................... 67 8.5 Interrupt Processing.................................. 68 8.6 Default Fatal Error Processing............................. 69 8.7 Symmetric Multiprocessing.............................. 70 8.8 Thread-Local Storage................................. 71 8.9 Board Support Packages................................ 72 8.9.1 System Reset................................. 72 9 Renesas M32C Specific Information 73 10 M68xxx and Coldfire Specific Information 75 10.1 CPU Model Dependent Features........................... 76 10.1.1 BFFFO Instruction.............................. 76 10.1.2 Vector Base Register............................. 76 10.1.3 Separate Stacks................................ 76 10.1.4 Pre-Indexing Address Mode......................... 76 10.1.5 Extend Byte to Long Instruction....................... 76 10.2 Calling Conventions.................................. 77 10.2.1 Calling Mechanism.............................. 77 10.2.2 Register Usage................................. 77 10.2.3 Parameter Passing............................... 77 10.3 Memory Model..................................... 78 10.4 Interrupt Processing.................................. 79 10.4.1 Vectoring of an Interrupt Handler...................... 79 10.4.1.1 Models Without Separate Interrupt Stacks............. 79 10.4.1.2 Models With Separate Interrupt Stacks............... 79 10.4.2 CPU Models Without VBR and RAM at 0.................. 80 10.4.3 Interrupt Levels................................ 81 10.5 Default Fatal Error Processing............................. 82 10.6 Symmetric Multiprocessing.............................. 83 10.7 Thread-Local Storage................................. 84 10.8 Board Support Packages................................ 85 10.8.1 System Reset................................. 85 10.8.2 Processor Initialization............................ 85 iii 11 Xilinx MicroBlaze Specific Information 87 11.1 Symmetric Multiprocessing.............................. 88 11.2 Thread-Local Storage................................. 89 12 MIPS Specific Information 91 12.1 CPU Model Dependent Features........................... 92 12.1.1 Another Optional Feature.......................... 92 12.2 Calling Conventions.................................. 93 12.2.1 Processor Background............................ 93 12.2.2 Calling Mechanism.............................. 93 12.2.3 Register Usage................................. 93 12.2.4 Parameter Passing............................... 93 12.3 Memory Model..................................... 94 12.3.1 Flat Memory Model.............................. 94 12.4 Interrupt Processing.................................. 95 12.4.1 Vectoring of an Interrupt Handler...................... 95 12.4.2 Interrupt Levels................................ 95 12.5 Default Fatal Error Processing............................. 96 12.6 Symmetric Multiprocessing.............................. 97 12.7 Thread-Local Storage................................. 98 12.8 Board Support Packages................................ 99 12.8.1 System Reset................................. 99 12.8.2 Processor Initialization............................ 99 13 Altera Nios II Specific Information 101 13.1 Symmetric Multiprocessing.............................. 102 13.2 Thread-Local Storage................................. 103 14 OpenRISC 1000 Specific Information 105 14.1 Calling Conventions.................................. 106 14.1.1 Floating Point Unit.............................. 106 14.2 Memory Model..................................... 107 14.3
Load more

Recommended publications
  • 12 Questions To... Natami Team - Part 1
    12 questions to... Natami Team - part 1 Banter (c) Polski Portal Amigowy (www.ppa.pl) Today I will tell you about something unique. I will present you the latest 68k CPU! You may wonder... What actually is N68050? The N68050 (N050) is a new 68k family processor developed by the Natami Team. It runs inside the FPGA together with the Natami chipset. The 050 is the first revision of our 68k CPU architecture. Further on, we will extend the architecture to the N68050E and later the N68070 specification. The N68050 softcore will be the default CPU of the Natami system. But if the user wants to, he could also get a separate CPU card with a physical 68060 for his Natami system, connected to the mainboard over the SyncZorro bus. The development history of the N68050 core. One could say it started in 1998, when Gunnar tried to write his first 68k softcore. But FPGAs were unfortunately too small to accomplish this task back then. The actual development of the Natami softcore started two years ago, after we dismissed Coldfire as a possible CPU for the Natami. Coldfire was interesting, but our testing and estimates showed us that solving it with our own softcore is even better. The first "N68070" softcore design idea was similar to a crossbreed of 68000 and Coldfire. Our first concept was to use a pipeline similar to the Coldfire V3 pipeline. To improve performance we changed this and reworked the pipeline to be longer. Our goal for the softcore was to reach a higher clockrate and to be in all regards better than the original Motorola 68060 clocked at the same speed.
    [Show full text]
  • Latticemico32 Development Kit User's Guide for Latticeecp
    LatticeMico32 Development Kit User’s Guide for LatticeECP Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 May 2007 Copyright Copyright © 2007 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More of the Best are service marks of Lattice Semiconductor Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimers NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS” WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF ACCURACY, COMPLETENESS, MERCHANTABILITY, NONINFRINGEMENT OF INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
    [Show full text]
  • Embedded Processors on FPGA: Hard-Core Vs Soft-Core Vivek J
    Grand Valley State University ScholarWorks@GVSU Masters Theses Graduate Research and Creative Practice 5-19-2017 Embedded processors on FPGA: Hard-core vs Soft-core Vivek J. Vazhoth Kanhiroth Grand Valley State University Follow this and additional works at: http://scholarworks.gvsu.edu/theses Part of the Engineering Commons Recommended Citation Vazhoth Kanhiroth, Vivek J., "Embedded processors on FPGA: Hard-core vs Soft-core" (2017). Masters Theses. 845. http://scholarworks.gvsu.edu/theses/845 This Thesis is brought to you for free and open access by the Graduate Research and Creative Practice at ScholarWorks@GVSU. It has been accepted for inclusion in Masters Theses by an authorized administrator of ScholarWorks@GVSU. For more information, please contact [email protected]. Embedded processors on FPGA: Hard-core vs Soft-core Vivek Jayakrishnan Vazhoth Kanhiroth A Thesis submitted to the Graduate Faculty of GRAND VALLEY STATE UNIVERSITY In Partial Fulfilment of the Requirements For the Degree of Master of Science in Electrical Engineering Padnos College of Engineering and Computing April 2017 DEDICATION To my parents Jayakrishnan and Jayalakshmi who are my biggest inspiration and to my mentor Rajesh without whose help I would never have come out of my shell. 3 ACKNOWLEDGEMENTS I would like to thank my Thesis Advisor Dr. Chirag Parikh without whose patience, guidance and understanding I would not have finished this thesis. I would also like to thank my Thesis committee members Dr. Christian Trefftz and Dr. Azizur Rahman for their valuable inputs and feedback about my thesis. I am indebted to Dr. Shabbir Choudhuri for always being approachable and helping me on innumerable occasions over the last 3 years.
    [Show full text]
  • Vxworks Architecture Supplement, 6.2
    VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction
    [Show full text]
  • Latticemico32 Software Developer User Guide
    LatticeMico32 Software Developer User Guide May 2014 Copyright Copyright © 2014 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, CleanClock, Custom Mobile Device, DiePlus, E2CMOS, ECP5, Extreme Performance, FlashBAK, FlexiClock, flexiFLASH, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, iCE Dice, iCE40, iCE65, iCEblink, iCEcable, iCEchip, iCEcube, iCEcube2, iCEman, iCEprog, iCEsab, iCEsocket, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDX2, ispGDXV, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, Lattice Diamond, LatticeCORE, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeECP4, LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MachXO2, MachXO3, MACO, mobileFPGA, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager, ProcessorPM, PURESPEED, Reveal, SensorExtender, SiliconBlue, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex
    [Show full text]
  • Corecommander for Microprocessors and Microcontrollers
    CORECOMMANDER FOR MICROPROCESSORS AND MICROCONTROLLERS Factsheet Direct access to memory and peripheral devices (I/O) for testing, debugging and in-system programming • Direct access to memory and peripheral (I/O) devices of a micro- processor through its (JTAG) debug interface • Read data from, write data to memory and peripherals without software programming • At-speed execution of read and write cycles • Testing and debugging of the connectivity of processor memory and peripherals with at-speed bus cycles without software programming • Easy programming of processor flash memory without software programming Corecommander provides high-level functions to write data to and read data from microprocessor memory Order information CoreComm Micro (core) and I/O addresses without software programming. (core) = ARM 7, ARM 9, ARM 11, Cortex-A, Cortex-R, CoreCommander functions are applied via the JTAG Cortex-M, Blackfin, PXA2xx, PXA3xx, IXP4xx, PowerPC- interface. MPC500 family, PowerPC-MPC5500 family, PowerPC- MPC5600 family, C28x, XC166, Tricore, PIC32 Applications CoreCommander is used in design debug, manufactu- ring test and (field) service for many different applica- [1] if the uProcessor also contains a boundary-scan register then teh tests and in-system tions such as: programming operations can also be done using the boundary-scan register instead of the CoreCommander. Whether in that case the CoreCommander or the boundary-scan register is used depends on preference or performance. • Diagnosing “dead-kernel” boards; no embedded code is required to perform memory reads and Background writes. A uP performs read and write operations on its bus to ac- cess memory and I/O locations. The read and write cycles • Determining the right settings for the peripheral normally result when the uP executes a program that is controller (DDR controller, flash memory controller, stored in memory.
    [Show full text]
  • ARM Architecture
    ARM Architecture Comppgzuter Organization and Assembly ygg Languages Yung-Yu Chuang with slides by Peng-Sheng Chen, Ville Pietikainen ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simp lic ity comes from the inexper ience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Mac hine ), owned by Acorn, Apple and VLSI ARM Ltd Design and license ARM core design but not fabricate Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 90% of 32-bit embedded RISC processors till 2009 • Used especially in portable devices due to its low power consumption and reasonable performance ARM powered products ARM processors • A simple but powerful design • A whlhole filfamily of didesigns shiharing siilimilar didesign principles and a common instruction set Naming ARM •ARMxyzTDMIEJFS – x: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazell e (JVM) – F: Floating-point – S: SthiiblSynthesizible version (source code version for EDA tools) Popular ARM architectures •ARM7TDMI – 3 pipe line stages (ft(fetc h/deco de /execu te ) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fe tc h/deco de /execu te /memory /wr ite ) – Separate instruction and data cache •ARM11 ARM family comparison year 1995 1997 1999 2003 ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed.
    [Show full text]
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • Historical Perspective and Further Reading 162.E1
    2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory.
    [Show full text]
  • Lecture 1: Course Introduction G Course Organization G Historical Overview G Computer Organization G Why the MC68000? G Why Assembly Language?
    Lecture 1: Course introduction g Course organization g Historical overview g Computer organization g Why the MC68000? g Why assembly language? Microprocessor-based System Design 1 Ricardo Gutierrez-Osuna Wright State University Course organization g Grading Instructor n Exams Ricardo Gutierrez-Osuna g 1 midterm and 1 final Office: 401 Russ n Homework Tel:775-5120 g 4 problem sets (not graded) [email protected] n Quizzes http://www.cs.wright.edu/~rgutier g Biweekly Office hours: TBA n Laboratories g 5 Labs Teaching Assistant g Grading scheme Mohammed Tabrez Office: 339 Russ [email protected] Weight (%) Office hours: TBA Quizes 20 Laboratory 40 Midterm 20 Final Exam 20 Microprocessor-based System Design 2 Ricardo Gutierrez-Osuna Wright State University Course outline g Module I: Programming (8 lectures) g MC68000 architecture (2) g Assembly language (5) n Instruction and addressing modes (2) n Program control (1) n Subroutines (2) g C language (1) g Module II: Peripherals (9) g Exception processing (1) g Devices (6) n PI/T timer (2) n PI/T parallel port (2) n DUART serial port (1) g Memory and I/O interface (1) g Address decoding (2) Microprocessor-based System Design 3 Ricardo Gutierrez-Osuna Wright State University Brief history of computers GENERATION FEATURES MILESTONES YEAR NOTES Asia Minor, Abacus 3000BC Only replaced by paper and pencil Mech., Blaise Pascal, Pascaline 1642 Decimal addition (8 decimal figs) Early machines Electro- Charles Babbage Differential Engine 1823 Steam powered (3000BC-1945) mech. Herman Hollerith,
    [Show full text]
  • Motorola 68000 Opcodes
    Motorola 68000 CPU Opcodes Mnemonic Size Single Effective Address Operation Word Data Mnemonic Size Single Effective Address Operation Word Data Addressing Mode Format M Xn ORI to CCR B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 B I RTE 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 Data register Dn 0 0 0 reg ORI to SR W 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 W I RTS 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 Address register An 0 0 1 reg ORI B W L 0 0 0 0 0 0 0 0 S M Xn I TRAPV 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 Address (An) 0 1 0 reg ANDI to CCR B 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 B I RTR 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 Address with Postincrement (An)+ 0 1 1 reg ANDI to SR W 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 W I JSR 0 1 0 0 1 1 1 0 1 0 M Xn Address with Predecrement -(An) 1 0 0 reg ANDI B W L 0 0 0 0 0 0 1 0 S M Xn I JMP 0 1 0 0 1 1 1 0 1 1 M Xn Address with Displacement (d16, An) 1 0 1 reg SUBI B W L 0 0 0 0 0 1 0 0 S M Xn I MOVEM W L 0 1 0 0 1 D 0 0 1 S M Xn W M Address with Index (d8, An, Xn) 1 1 0 reg ADDI B W L 0 0 0 0 0 1 1 0 S M Xn I LEA L 0 1 0 0 An 1 1 1 M Xn Program Counter with Displacement (d16, PC) 1 1 1 0 1 0 EORI to CCR B 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 B I CHK W 0 1 0 0 Dn 1 1 0 M Xn Program Counter with Index (d8, PC, Xn) 1 1 1 0 1 1 EORI to SR W 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 W I ADDQ B W L 0 1 0 1 Data 0 S M Xn Absolute Short (xxx).W 1 1 1 0 0 0 EORI B W L 0 0 0 0 1 0 1 0 S M Xn I SUBQ B W L 0 1 0 1 Data 1 S M Xn Absolute Long (xxx).L 1 1 1 0 0 1 CMPI B W L 0 0 0 0 1 1 0 0 S M Xn I Scc B 0 1 0 1 Condition 1 1 M Xn Immediate #imm 1 1 1 1 0 0 BTST B L 0 0 0 0 1 0 0
    [Show full text]
  • Computer Architectures
    Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative ..
    [Show full text]