An On-Chip 96.5% Current Efficiency CMOS Linear Regulator Using A

34 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 An On-Chip 96.5% Current Efficiency CMOS Linear Regulator Using a Flexible Control Technique of Output Current Tetsuo Endoh, Member, IEEE, Kazuhisa Sunaga, Hiroshi Sakuraba, and Fujio Masuoka, Fellow, IEEE

Abstract—This paper proposes an on-chip 96.5% current effi- linear regulators are only applicable to one with a light load in ciency CMOS linear regulator using a Flexible Control technique order to realize a stable output voltage supply and low-power of Output Current (FCOC). By the use of the FCOC technique, operation at the same time. Our proposed linear regulator the proposed circuit realizes to drive a flexible output current according to the load current variation. Therefore, the proposed overcomes the issue by the FCOC technique. Therefore, the linear regulator can supply stable output voltage using the FCOC proposed linear regulator is applicable to the one with a heavier technique. The linear regulator is fabricated by double-metal load current in comparison with reported linear regulators. 1.2- m CMOS technology. The number of transistors is 46 and the P We proposed the FCOC technique from the above viewpoints die size is 0.423 mm . The fabricated linear regulator achieves a and showed a good performance by using circuit simulation fluctuation of output voltage less than 6.81 mV at a frequency [3]–[5]. However, the FCOC technique was verified only of output current @ outA ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can with circuit simulation. In this paper, we fabricate the linear achieve 96.5% current efficiency. regulator with the FCOC technique using 1.2- m CMOS Index Terms—CMOS, driving current, linear regulator, low technology and verify the performance of this linear regulator power, quick response. experimentally. As a result, an on-chip linear regulator using the FCOC technique can achieve current efficiency over 96.5%, with output noise less than 150 mV . I. INTRODUCTION N ON-CHIP linear regulator with high current efficiency, A high packing density, and easy implementation to LSIs is II. FLEXIBLE CONTROL TECHNIQUE OF OUTPUT CURRENT needed for single-supply voltage and low-power operation of (FCOC TECHNIQUE) LSIs. To obtain high efficiency, dc/dc converters using a fixed The schematic of the proposed linear regulator is shown in pulse-width modulation (PWM) and divided switches with Fig. 1. In order to keep the constant output voltage, a linear current control (DSCC) have been reported [1], [2]. However, regulator should perfectly drive the output current which has these reported converters cannot realize a high packing density the same value of the load current. The FCOC technique on board and easy implementation to LSIs, because these dynamically drives the output current in seven different stages reported converters need additional off-chip implementations according to a variation of the load current, as shown in Fig. 2. of inductance, capacitance, and pn-diode on board. These Moreover, the FCOC technique achieves little consumption additional off-chip implementations require much area to current even at flowing large output currents. As a result, the be sacrificed on board. These are the most important points on-chip linear regulator using FCOC technique achieves high for practical use. In order to overcome these drawbacks, the current efficiency. specifications for the linear regulator are: A FCOC circuit is shown at Block (A) including three 1) easy implementation to LSIs; ( ) circuits in Fig. 1. The operation principle of the 2) high current efficiency over 90% (at mA, FCOC circuit is shown in Fig. 2. Each circuit consists of an 5.0 V 3.0 V); nMOS driver transistor (N-Tr), a pMOS driver transistor (P-Tr) 3) low output noise below 150 mV . and a current mirror amplifier circuit. Two reference voltages For these three specifications, Flexible Control technique ( -high- , -low- ), which are generated by the reference of Output Current (FCOC) can realize easy implementation voltage generator of Block (B), are supplied into the current to LSIs and high current efficiency. The current efficiency is mirror amplifier circuit in each circuit. Each -high- is defined as the ratio of output current ( ) to the total current a higher reference voltage for each , and each -low- is of the linear regulator ( ), that is, , where a lower reference voltage for each . When the output voltage is the current flowing from . Moreover, previous reported is smaller than -low- , only the nMOS driver transistor in the turns on, and the pMOS driver transistor in the turns Manuscript received January 18, 2000; revised August 4, 2000. off. On the other hand, when the output voltage is larger than The authors are with the Research Institute of Electrical Communication, -high- , only the pMOS driver transistor in the turns on, Tohoku University, Sendai 980-8577, Japan (e-mail: [email protected] hoku.ac.jp). and the nMOS driver transistor in the turns off. As a result, Publisher Item Identifier S 0018-9200(01)00430-9. the number of charging or discharging current paths at the output

Fig. 1. Schematic of the on-chip linear regulator.

Fig. 2. Operation principle of FCOC technique. node of the linear regulator can be automatically changed ac- ations of all six reference voltages are suppressed to less than cording to a variation of the output current. Therefore, the pro- 17 mV for a supply voltage ranging from 4.5 to 5.5 V. posed circuit realizes to drive a flexible output current according As shown in Fig. 3, the output current and each driving cur- to the load current variation, as shown in Fig. 2. Moreover, little rent of ) as shown in Fig. 1 are simulated at pass-through current flows. Therefore, the consumption current V and V. As shown in Fig. 3, when the output is very small in comparison with the output current. voltage is between 2.9 and 3.0 V, only the A1 circuit drives In Block (A), each transistor in circuit is designed as fol- the output current with charging the output node. When is lows. The total gate size, that is, the sum over all driver tran- between 2.8 and 2.9 V, both A1 and A2 drive the output cur- sistors of each , is optimized for an output current of 30 mA rent. When is lower than 2.8 V, A1, A2, and A3 all drive and an output current frequency of 100 MHz. The gate size of the output current. The driving current flows from the power each driver transistor is determined by the minimum that can source to the output node of the linear regulator. On the other supply the 7-mA target maximum current within the saturation hand, when is between 3.2 and 3.3 V, only A1 drives the region of the transistor. The output current is quickly changed output current with discharging the output node. When is by the quick response of the current mirror circuit. The output between 3.3 and 3.4 V, both A1 and A2 drive the output current. current is given by – , where and When is higher than 3.4 V, A1, A2 and A3 all drive the are currents flowing from and , respectively. Each output current. This driving current flows from the output node transistor in Block (B) is designed as follows. 1) The six refer- of the linear regulator to the ground. Moreover, when is be- ence voltages, which differ from each other by 0.1 V, are tween 3.0 and 3.2 V, A1, A2 and A3 all drive no output current generated from the setting voltage . 2) The voltage fluctu- to the output node with little consumption current. 36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001

Fig. 5. Measurement setup.

Fig. 3. Simulated output current vs. output voltage.

Fig. 6. Measured output voltage vs. supply voltage.

Fig. 4. Chip micrograph. 1.2110.35mm die.

III. FABRICATION OF THE LINEAR REGULATOR USING FCOC TECHNIQUE The proposed on-chip linear regulator is fabricated using the 1.2- m CMOS double-metal and single-polysilicon process. Fig. 4 shows the photomicrograph of the fabricated proposed linear regulator. The number of transistors is 46 and the die Fig. 7. Measurement method to evaluate frequency characteristic. size is 0.423 mm . B. Experimental Results and Discussion IV. EXPERIMENTAL RESULTS AND DISCUSSION Fig. 6 shows the stability of the output voltage for fluctuation of the supply voltage of the fabricated linear regulator. The A. Measurement Method axis is supply voltage , and the axis is the output voltage The measurement of this chip is performed as shown in . This measurement condition is that setting voltage is Fig. 5. Since this linear regulator needs the external power equal to 3.0 V, as is shown in Fig. 1. supply voltage ( , , , and ) and the driving current, The reference voltage generator (Block B) suppresses the fluc- a semiconductor parameter analyzer (HP4156A) and a pulse tuationofreferencevoltagesto 17mV againstthesupply generator (HP8110A) are used, respectively. The driving voltage at V V.Therefore, by the six stable current of this chip is controlled by the MOSFET, whose gate referencevoltagesfromBlock(B),thelinearregulatorcansupply voltage is changed by the pulse generator. The output node is anoutputvoltageof2.978V 128mVat V 0.5 connected to the sampling oscilloscope (HP54602B), which V. Moreover, at the output voltage range of 5.0 V 0.3 V, has 2-GSa/s sampling rate, because the parasitic capacitance the linear regulator can supply 2.9005 V 50 mV. The stable for monitor must be small. Therefore, the power consumption output voltage of the linear regulator is realized. current and the output voltage of the linear regulator are Fig. 7 shows the measurement method of the frequency char- monitored at the same time. acteristics of fabricated linear regulator. The gate voltage of ENDOH et al.: ON-CHIP 96.5% CURRENT EFFICIENCY CMOS LINEAR REGULATOR 37

(a) (b)

(c)

Fig. 8. (a) Measured load current waveform at f@s AaIXV Hz. (b) Measured output voltage waveform at f@s AaIXV Hz. (c) Measured output voltage versus load current frequency. the MOSFET (MOS) in Fig. 7 used as the load of linear reg- current frequency of the fabricated linear regulator. The ulator is supplied with a sawtooth waveform by the pulse gen- axis is the load current frequency , and the axis is erator. Therefore, the load current is dynamically changed. By the output voltage . The output voltage, which is the aver- flowing the load current, the output voltage is measured with aged value of the measured waveform, is plotted at each load an oscilloscope. By this method, the dependence of the output current frequency ranging from 1.8 Hz to 100 MHz. voltage fluctuation on the load current frequency can be exper- The maximum load current is 13.8 A at each load current fre- imentally analyzed. quency ranging from 1.8 Hz to 100 MHz. Measurement Fig. 8 shows the characteristic of an output voltage fluctua- conditions are as follows: Supply voltage equals 5.0 V and tion for a frequency of a load current that is not zero. In prac- setting voltage , as shown in Fig. 1, equals 3.0 V. The linear tical use, even if no transistor is active, the LSI consumes some regulator can supply an output voltage from 2.8302 to 2.8165 V leakage current, e.g., pn-junction leakage currents, subthreshold at a frequency of output current ranging from 1.8 Hz to leakage currents, and so on. Therefore, load current does not 100 MHz. The linear regulator, which is fabricated using 1.2- m become zero. Under the condition that a load current flows, technology, achieves a fluctuation of output voltage less than we evaluate the output voltage fluctuation as shown in Fig. 8. 6.81 mV at a frequency of output current ranging Fig. 8(a) shows a measurement output current at a fre- from 1.8 Hz to 100 MHz. Moreover, the 1.2- m linear regulator quency of output current Hz, which is the drain achieves a fluctuation of output voltage less than 150 mV at current of the MOSFET (MOS) in Fig. 7. The maximum current an output current ranging from 0 to 5.7 mA. From circuit sim- is 13.8 A at each load current frequency ulation results (using HSPICE), it is estimated that the linear ranging from 1.8 Hz to 100 MHz. Fig. 8(b) shows a measured regulator using the FCOC technique, which has been designed output voltage waveform of the fabricated linear regulator at a using 0.13- m technology, achieves an output voltage fluctu- frequency of output current Hz. The proposed ation less than 30 mV at output current ranging from 0 to linear regulator can supply stable output voltage at a frequency 900 mA. of output current Hz, as shown in Fig. 8(b). Fig. 9 shows the measured current efficiency of the fabri- Fig. 8(c) shows the stability of the output voltage for the load cated linear regulator. The axis is the output current and 38 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001

hot holes flow to substrate. Therefore, hot hole carrier current flows to substrate. increases as increases. From above all, the and increase as increases. In Fig. 9, the measured current efficiency decreases because and increase according to the increase of . Table I summarizes the chip performance.

V. C ONCLUSION This paper proposed an on-chip 96.5% current efficiency CMOS linear regulator using a Flexible Control technique of Output Current. By the use of the FCOC technique, the Fig. 9. Measured linear regulator current efficiency versus output current. proposed circuit realizes to drive a flexible output current according to the load current variation. The FCOC technique dynamically drives the output current in seven different stages TABLE I CHIP PERFORMANCE SUMMARY according to a variation of the load current. Moreover, the FCOC technique can achieve little consumption current even at flowing large output currents. Therefore, the proposed linear regulator can supply stable output voltage using the FCOC technique at any place on chip. The linear regulator is fabricated by double-metal 1.2- m CMOS technology. The number of transistors is 46 and the die size is 0.423 mm . The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV at a frequency of output current ranging from 1.8 Hz to 100 MHz. Moreover, the 1.2- m linear regulator achieves a fluctuation of output voltage less than 150 mV at an output current ranging from 0 to 5.7 mA. From circuit simulation results (HSPICE), it is estimated the axis is the current efficiency of the fabricated linear reg- the linear regulator using FCOC technique, which has been ulator. Measurement conditions are as follows: Supply voltage designed using 0.13- m technology, achieves an output voltage equals 5.0 V and setting voltage , as shown in Fig. 1, fluctuation less than 30 mV at output current ranging from equals 3.0 V. This current efficiency is defined as the ratio of 0 to 900 mA. The fabricated linear regulator using FCOC output current to the total current of the linear regulator technique can achieve 96.5% current efficiency. . As the current efficiency increases, the power dissipation of the linear regulator decreases. Therefore, the enhanced cur- ACKNOWLEDGMENT rent efficiency can achieve a linear regulator with reduced power consumption. The proposed on-chip linear regulator using the The authors would like to thank the VLSI Design and FCOC technique achieves 96.5% current efficiency at an output Education Center (VDEC) as follows: “The VLSI chip in this current of 5.7 mA and 90% current efficiency at an output cur- study has been fabricated in the chip fabrication program of rent of 27.35 mA. The concept of the FCOC technique is that VLSI Design and Education Center (VDEC), the University of no current flows from to ground in the FCOC circuit at Tokyo, with collaboration by On-Semiconductor, Nippon Mo- any output voltage. However, actually consists of , torola LTD., Dai Nippon Printing Corporation, and KYOCERA , , and . is the output current of fabri- Corporation.” cated linear regulator. is the current of Block (B). is a pn-leakage current from an n diffusion layer to substrate. REFERENCES is a hot carrier current to substrate from drain edge. [1] W. Namgoong et al., “A high-efficiency variable-voltage CMOS dy- Therefore, the measured current efficiency, , is de- namic dc–dc switching regulator,” in ISSCC Dig., 1997, pp. 380–381. fined as ). is propor- [2] S. Sakiyama, J. Kajiwara, M. Kinoshita, K. Satomi, K. Ohtani, and A. tional to the area of the n diffusion layer. The on-chip CMOS Matsuzawa, “An on-chip high-efficiency and low-noise dc/dc converter using divided switches with current control technique,” in ISSCC Dig., linear regulator has a large driver transistor in order to drive 1999, pp. 156–157. a large stable load current. In our proposed circuit, there are [3] T. Endoh, K. Nakamura, and F. Masuoka, “A new voltage downconverter three nMOS driver transistors whose gate width is 2000 m. (VDC) with low ratio of consuming current to load current for ULSI,” IEICE Trans. Electron., vol. J80-C, no. 3, pp. 117–118, Mar. 1997. The sum of nMOS transistor gate widths is more than 6000 m. [4] , “Evaluation of the voltage down converter (VDC) with low ratio Therefore, the area of the n diffusion layer is very large and of consuming current to load current in dc/ac operation mode,” IEICE is not negligible. Moreover, the pn-junction is heated up as Trans. Electron., vol. E81-C, no. 6, pp. 968–974, June 1998. [5] , “A high-performance voltage down converter (VDC) using new increases, as a result increases, too. Moreover, usually flexible control technology of driving current,” IEICE Trans. Electron., hot carriers are generated at the drain edge area and generated vol. E81-C, no. 12, pp. 1905–1912, Dec. 1998. ENDOH et al.: ON-CHIP 96.5% CURRENT EFFICIENCY CMOS LINEAR REGULATOR 39

Tetsuo Endoh (M’89) was born in Tokyo, Japan, in Hiroshi Sakuraba was born in Akita, Japan, in 1961. 1962. He received the B.S. degree in physics from He received the B.E., M.E., and Ph.D. degrees in elec- the University of Tokyo in 1987, and the Ph.D. de- trical engineering from Tohoku University, Sendai, gree in electronic engineering from Tohoku Univer- Japan, in 1987, 1989, and 1992 respectively. sity, Sendai, Japan, in 1995. Since 1992, he had been a Research Associate of He joined the Research and Development Center, the Faculty of Engineering of Tohoku University, Toshiba Corporation, Kawasaki, Japan, in 1987, where he was engaged in the research of the surface where he was engaged in research on CMOS device reaction mechanism of semiconductor crystal design. Since 1988, he has been engaged in research growth. Since 1996, he has been with the Research on high-density Flash EEPROMs and reliability of Institute of Electrical Communication (RIEC), Flash EEPROMs at the ULSI Research Laboratories, Tohoku University. His current research interest is Research and Development Center, Toshiba Corporation, Kawasaki. He was the device and process technology of ULSI. a Lecturer at the Research Institute of Electrical Communication (RIEC), Tohoku University, in 1995. Since 1997, he has been an Assistant Professor at RIEC. He has been engaged in research on CMOS device design, low-power and high-speed logic technology, and clean-room technology. Fujio Masuoka (A’88–SM’94–F’95) was born on Dr. Endoh is a member of the Institute of Electronics, Information and Com- May 8, 1943, in Gunma, Japan. He received the B.E., munication Engineers (IEICE), and the Japan Society of Applied Physics. M.E., and Ph.D. degrees in electrical engineering from Tohoku University, Sendai, Japan, in 1966, 1968, and 1971, respectively. In 1971, he joined Toshiba Research and De- velopment Center, where in 1972, he developed the stacked gate avalanche injection-type MOS read-only memory (SAMOS), which is the origin of the current EPROM and Flash memory. In 1976, he developed the dynamic memory cell with double poly-Si structure. In 1977, he moved to Toshiba Semiconductor Business Division, where he developed 1-Mb DRAM, and in 1980, he applied for the Flash memory patent for the first time. In 1984, he presented Flash memory for the first time at the IEDM, and in 1985 at the ISSCC. In 1987, he returned to Kazuhisa Sunaga was born in Kanagawa, Japan, in Toshiba Research and Development Center, where he began to develop NAND 1975. He received the B.E. degree in electrical en- structured Flash memory, which was presented in 1987 at the IEDM. He moved gineering in 1998 and the M.E. degree in electronic to Tohoku University as a Professor in 1994. He has 170 registered patents in engineering in 2000 from Tohoku University, Sendai, the U.S., Germany, France and Great Britain, 100 registered patents in Japan, Japan. where he is currently working toward the D.E. and 71 pending patents. He has authored and co-authored approximately 150 degree in electronics. papers. His research interest is in low-power circuits, es- Dr. Masuoka received the Watanabe Award and the National Invention Award pecially low-power converters. in 1977 and 1978, respectively. He received the 1997 IEEE Morris N. Liebmann Mr. Sunaga is a student member of the Institute of Memorial Award, and the 2000 Ichimura Prizes in Industry–Main Prize for the Electronics, Information and Communication Engi- development of flash memory. He is a member of the Institute of Electronics, neers (IEICE). Information and Communication Engineers (IEICE).