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An On-Chip 96.5% Current Efficiency CMOS Linear Regulator Using A 34 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 An On-Chip 96.5% Current Efficiency CMOS Linear Regulator Using a Flexible Control Technique of Output Current Tetsuo Endoh, Member, IEEE, Kazuhisa Sunaga, Hiroshi Sakuraba, and Fujio Masuoka, Fellow, IEEE Abstract—This paper proposes an on-chip 96.5% current effi- linear regulators are only applicable to one with a light load in ciency CMOS linear regulator using a Flexible Control technique order to realize a stable output voltage supply and low-power of Output Current (FCOC). By the use of the FCOC technique, operation at the same time. Our proposed linear regulator the proposed circuit realizes to drive a flexible output current according to the load current variation. Therefore, the proposed overcomes the issue by the FCOC technique. Therefore, the linear regulator can supply stable output voltage using the FCOC proposed linear regulator is applicable to the one with a heavier technique. The linear regulator is fabricated by double-metal load current in comparison with reported linear regulators. 1.2- m CMOS technology. The number of transistors is 46 and the P We proposed the FCOC technique from the above viewpoints die size is 0.423 mm . The fabricated linear regulator achieves a and showed a good performance by using circuit simulation fluctuation of output voltage less than 6.81 mV at a frequency [3]–[5]. However, the FCOC technique was verified only of output current @ outA ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can with circuit simulation. In this paper, we fabricate the linear achieve 96.5% current efficiency. regulator with the FCOC technique using 1.2- m CMOS Index Terms—CMOS, driving current, linear regulator, low technology and verify the performance of this linear regulator power, quick response. experimentally. As a result, an on-chip linear regulator using the FCOC technique can achieve current efficiency over 96.5%, with output noise less than 150 mV . I. INTRODUCTION N ON-CHIP linear regulator with high current efficiency, A high packing density, and easy implementation to LSIs is II. FLEXIBLE CONTROL TECHNIQUE OF OUTPUT CURRENT needed for single-supply voltage and low-power operation of (FCOC TECHNIQUE) LSIs. To obtain high efficiency, dc/dc converters using a fixed The schematic of the proposed linear regulator is shown in pulse-width modulation (PWM) and divided switches with Fig. 1. In order to keep the constant output voltage, a linear current control (DSCC) have been reported [1], [2]. However, regulator should perfectly drive the output current which has these reported converters cannot realize a high packing density the same value of the load current. The FCOC technique on board and easy implementation to LSIs, because these dynamically drives the output current in seven different stages reported converters need additional off-chip implementations according to a variation of the load current, as shown in Fig. 2. of inductance, capacitance, and pn-diode on board. These Moreover, the FCOC technique achieves little consumption additional off-chip implementations require much area to current even at flowing large output currents. As a result, the be sacrificed on board. These are the most important points on-chip linear regulator using FCOC technique achieves high for practical use. In order to overcome these drawbacks, the current efficiency. specifications for the linear regulator are: A FCOC circuit is shown at Block (A) including three 1) easy implementation to LSIs; ( ) circuits in Fig. 1. The operation principle of the 2) high current efficiency over 90% (at mA, FCOC circuit is shown in Fig. 2. Each circuit consists of an 5.0 V 3.0 V); nMOS driver transistor (N-Tr), a pMOS driver transistor (P-Tr) 3) low output noise below 150 mV . and a current mirror amplifier circuit. Two reference voltages For these three specifications, Flexible Control technique ( -high- , -low- ), which are generated by the reference of Output Current (FCOC) can realize easy implementation voltage generator of Block (B), are supplied into the current to LSIs and high current efficiency. The current efficiency is mirror amplifier circuit in each circuit. Each -high- is defined as the ratio of output current ( ) to the total current a higher reference voltage for each , and each -low- is of the linear regulator ( ), that is, , where a lower reference voltage for each . When the output voltage is the current flowing from . Moreover, previous reported is smaller than -low- , only the nMOS driver transistor in the turns on, and the pMOS driver transistor in the turns Manuscript received January 18, 2000; revised August 4, 2000. off. On the other hand, when the output voltage is larger than The authors are with the Research Institute of Electrical Communication, -high- , only the pMOS driver transistor in the turns on, Tohoku University, Sendai 980-8577, Japan (e-mail: [email protected] hoku.ac.jp). and the nMOS driver transistor in the turns off. As a result, Publisher Item Identifier S 0018-9200(01)00430-9. the number of charging or discharging current paths at the output 0018–9200/01$10.00 © 2001 IEEE ENDOH et al.: ON-CHIP 96.5% CURRENT EFFICIENCY CMOS LINEAR REGULATOR 35 Fig. 1. Schematic of the on-chip linear regulator. Fig. 2. Operation principle of FCOC technique. node of the linear regulator can be automatically changed ac- ations of all six reference voltages are suppressed to less than cording to a variation of the output current. Therefore, the pro- 17 mV for a supply voltage ranging from 4.5 to 5.5 V. posed circuit realizes to drive a flexible output current according As shown in Fig. 3, the output current and each driving cur- to the load current variation, as shown in Fig. 2. Moreover, little rent of ) as shown in Fig. 1 are simulated at pass-through current flows. Therefore, the consumption current V and V. As shown in Fig. 3, when the output is very small in comparison with the output current. voltage is between 2.9 and 3.0 V, only the A1 circuit drives In Block (A), each transistor in circuit is designed as fol- the output current with charging the output node. When is lows. The total gate size, that is, the sum over all driver tran- between 2.8 and 2.9 V, both A1 and A2 drive the output cur- sistors of each , is optimized for an output current of 30 mA rent. When is lower than 2.8 V, A1, A2, and A3 all drive and an output current frequency of 100 MHz. The gate size of the output current. The driving current flows from the power each driver transistor is determined by the minimum that can source to the output node of the linear regulator. On the other supply the 7-mA target maximum current within the saturation hand, when is between 3.2 and 3.3 V, only A1 drives the region of the transistor. The output current is quickly changed output current with discharging the output node. When is by the quick response of the current mirror circuit. The output between 3.3 and 3.4 V, both A1 and A2 drive the output current. current is given by – , where and When is higher than 3.4 V, A1, A2 and A3 all drive the are currents flowing from and , respectively. Each output current. This driving current flows from the output node transistor in Block (B) is designed as follows. 1) The six refer- of the linear regulator to the ground. Moreover, when is be- ence voltages, which differ from each other by 0.1 V, are tween 3.0 and 3.2 V, A1, A2 and A3 all drive no output current generated from the setting voltage . 2) The voltage fluctu- to the output node with little consumption current. 36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 Fig. 5. Measurement setup. Fig. 3. Simulated output current vs. output voltage. Fig. 6. Measured output voltage vs. supply voltage. Fig. 4. Chip micrograph. 1.2110.35mm die. III. FABRICATION OF THE LINEAR REGULATOR USING FCOC TECHNIQUE The proposed on-chip linear regulator is fabricated using the 1.2- m CMOS double-metal and single-polysilicon process. Fig. 4 shows the photomicrograph of the fabricated proposed linear regulator. The number of transistors is 46 and the die Fig. 7. Measurement method to evaluate frequency characteristic. size is 0.423 mm . B. Experimental Results and Discussion IV. EXPERIMENTAL RESULTS AND DISCUSSION Fig. 6 shows the stability of the output voltage for fluctuation of the supply voltage of the fabricated linear regulator. The A. Measurement Method axis is supply voltage , and the axis is the output voltage The measurement of this chip is performed as shown in . This measurement condition is that setting voltage is Fig. 5. Since this linear regulator needs the external power equal to 3.0 V, as is shown in Fig. 1. supply voltage ( , , , and ) and the driving current, The reference voltage generator (Block B) suppresses the fluc- a semiconductor parameter analyzer (HP4156A) and a pulse tuationofreferencevoltagesto 17mV againstthesupply generator (HP8110A) are used, respectively. The driving voltage at V V.Therefore, by the six stable current of this chip is controlled by the MOSFET, whose gate referencevoltagesfromBlock(B),thelinearregulatorcansupply voltage is changed by the pulse generator. The output node is anoutputvoltageof2.978V 128mVat V 0.5 connected to the sampling oscilloscope (HP54602B), which V. Moreover, at the output voltage range of 5.0 V 0.3 V, has 2-GSa/s sampling rate, because the parasitic capacitance the linear regulator can supply 2.9005 V 50 mV.
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