3D Incities the First Decade Magazine

Volume 1, 2019 3DInCites.com

Page 27 The Past, Present Page 36 Ten Years of Page 62 The First and Future of 3D Integration Invent, Innovate, Implement Decade in Pictures BREAKTHROUGH ALIGNMENT ACCURACY FOR 3D DEVICE STACKING

Introducing the new SmartView® NT3 with sub-50 nm alignment accuracy on the GEMINI® FB XT bonding platform

Fusion and hybrid wafer bonding enables leading-edge 3D Stacked CIS, Memory Stacking and 3D SoC devices

GET2 IN TheTOUCH First Decade to discuss your manufacturing needs www.EVGroup.com GEMINI® FB XT CONTENTS The Past, Present, and Future of 3D Integration In this special section, industry experts talk about pivotal moments and future 27 expectations for 3D and heterogeneous integration.

27 3D InCites Turns 10: A Brief Analysis of the 3D Journey Yann Guillou, Trymax 28 3D Powered: From Image Sensors to Edge Computing Paul Werbaneth, Nor-Cal Products, Inc. 29 3D Integration’s Thousand Mile Journey Amy Leong, FormFactor 29 3D Enables More than Moore Paul Lindner, Executive Technology Director, EV Group 30 A Shift in Value from Single to Multi-die ICs Herb Reiter, eda2asic 31 Eliminating the Memory Wall Jan Vardaman, TechSearch International, Inc. 32 From 3D Pioneers to 3D Robots Dr. Phil Garrou, IFTLE, Microelectronics Consultants of North America 32 Thank 2.5D Interposers for the Success of 3D ICs Mark Scannell, CEA-Leti 34 Heterogeneous Integration Calls for Increased Materials Reliability Dr. Andy C. Mackie, PhD, Indium Corporation 34 Extending Moore’s Law through Advanced Packaging Carl McMahon, Genmark Automation

ON THE COVER: 36 10 Years of Invent, Innovate, Implement Françoise von Trapp returns to EV Group for her fourth visit and reminisces about the past 10 years.

FEATURES 8 Hybrid Bonding: From Concept to Commercialization An interview with Xperi’s Gil Fountain 12 Advanced Packaging: An IFTLE Historical Perspective By Dr. Phil Garrou, Microelectronics Consultants of NC 16 Why Today’s Advanced Packages Need Better Inspection By Françoise von Trapp 19 Diversification of Markets Calls for Hybrid Metrology with Multi-Sensor Technology An interview with Thomas Fries, FRT- The Art of Metrology 21 3D Test - No Longer a Bottleneck! By Eric Jan Marinissen, imec 43 Advanced Heterogeneous Packaging Solutions for High-Performance Computing By Ron Huemoeller, Mike Kelly, Curtis Zwenger, Dave Hiner, and George Scott, Amkor Technology, Inc.

3D InCites Magazine 3 CONTENTS CONTINUED

45 CoolCube™: Much more than a True 3DVLSI Alternative to Scaling By Jean-Eric Michalette, CEA-Leti 53 Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging Q&A featuring Anil Vijayendran, Veeco Instruments 55 Reliable Process Control Solutions for the Growing Power Device Market By Dr. Dario Alliata, Unity-SC 57 3D NAND: Where Haste You So? By Andrew Walker, Schiltron, Corp. 62 The First Decade in Pictures 3D InCites has always been about the people in our industry. Here is a collection of photos from throughout the years.

STAFF

Françoise von Trapp, Ale Moreno, Dr. Maaike M. Visser Taklo, Editor-in-Chief Web Developer Disruptive Technologies, Norway [email protected] Ph: 978.340.0773 Technical Advisory Board E. Jan Vardaman, TechSearch International, Inc. Martijn Pierik, Publisher Sitaram R. Arkalgud, Ph.D., Xperi Corporation, USA [email protected] Paul Werbaneth, Ph: 602.366.5599 Nor-Cal Products, Inc. Rozalia Beica, DowDupont, USA Danielle Friedman, M. Juergen Wolf, Fraunhofer IZM-ASSID, Germany Director of Operations [email protected] Pascal Couderc, 3D PLUS, France Visit us at www.3DInCites.com Ph: 602.443.0030 Yann Guillou, Subscribe to our e-newsletter, Phil Garrou, Contributing Editor Trymax Semiconductor, 3D InCites In Review: https://ww- [email protected] Netherlands w.3dincites.com/subscribe-newsletter/ Herb Reiter, Contributing Editor [email protected] Dr. Phil Garrou, Microelectronic Consultants 3D InCites: The First Decade was of NC, USA published by: Creative/Production/Online

3D InCites, LLC , Erik Jan Marinissen, Rose Rover Principal Scientist at IMEC, Belgium 45 West Jackson St. Suite 700 Production Manager Phoenix, AZ, 85003 , Peter Ramm, Ph: 602.443.0030 Taylor Lineberger Fraunhofer EMFT, Germany Lead Designer Copyright ©2019 by 3D InCites,

4 The First Decade 3D InCites Magazine 5 6 The First Decade A Message from the Queen of 3D

research institutes have made to bring about the commercialization of 3D and heterogeneous integration technologies. This year marks the 7th year of the awards program. Our statue graces the award cases of Amkor Technology, Inc.; Brewer Science; Bob Patti; Bryan Black; Deca Technologies; Dow Corning (now Dupont); Dusan Petranovic; E-System Design; EV Group; and Fogale Nanotech (now UnitySC); Fraunhofer IZM; Fraunhofer Cluster for 3D Integration; FRT, the Art of Metrology; Gill Fountain; GLOBAL- FOUNDRIES; KLA; Kobus (now part of PlasmaTherm); imec; Mentor, A Siemens company; OmniVision; Novati Technologies; Paul En- Has it already been 10 years since behind 3D integration in a uniquely quist; Phil Garrou; Semblant/HZO; my first business partner, Leo Ar- personal way.” It’s what sets us SPTS; Sorin CRM; SSEC (now cher, and I started 3D InCites? apart from the other industry publi- Veeco);TSMC; Xilinx; and Xperi. cations, and we live by it. The past When we first conceived of the idea 10 years have been full of pivotal Thanks to your sponsorship and in 2009, I had no idea what I was moments for the companies and donations, we’ve made significant getting myself into or that 10 years people responsible for developing contributions to the IEEE Women later, 3D InCItes would be so well 3D and heterogeneous integration in Engineering Scholarship, SEMI recognized in the industry. technologies, and 3D InCites has High Tech U, the IMAPS Founda- been lucky to grow up alongside it. tion, G1ve-A-Buck, and Phoenix Leo and I parted ways in 2011, and Children’s Hospital. in 2012, I partnered with Martijn We were there when the EMC3D Pierik and Dave Richardson of Consortium put TSVs on the What does the future hold? 3D in- Impress Labs (now Kiterocket). roadmap, and drove cost reduction tegration has finally hit the big time, Bolstered by the support of these efforts to bring them to commercial- and we’ll continue to bring you the two partners and a web design and ization. We were there when imec, latest developments. Some of them development team, I was able to CEA-Leti, SEMATECH, Fraunhofer are in this issue. In October 2018, focus on creating valuable content EMFT, Fraunhofer IZM-ASSID, and Phil Garrou joined us as a contrib- and building a following. I remem- others developed back-end pro- uting editor, bringing with him his ber how excited I was when, in cesses that are now mainstream. well-known blog, re-christened our first year, we hit 116 registered Packaging InCites from the Leading members. Ten years later, we log in We were there when companies Edge. He joins Herb Reiter, our EDA over 80K users annually. like Alchimer, ALLVIA, NEXX Sys- expert, as a regular contributor. tems, Replisaurus, Tezzaron, and We’ve also launched the SemiSister Putting this 10th Anniversary issue Ziptronix were just getting started. project to support gender diversity together has been a nostalgia trip We were there for the launches of and inclusion efforts in the semi- for me, from searching through the Deca Technologies, Invensas, KO- conductor industry. archives and photos, to reading all BUS, and UnitySC. We remember the contributions from our friends in when Alchimer became Aveni, and In 2019, the 3D InCites leadership the industry. For that is how I think when Replisaurus went the way of changed again. Dave Richardson of all of you: not just readers, but a the dinosaurs; and when Ziptronix has gone on to pursue other inter- community of colleagues. was acquired by Invensas, and then ests, leaving Martijn and me at the became Xperi. We remember when helm of this particular ship. We are 3D InCites has always been more Applied Materials and TEL almost excited for what the next 10 years than just another source of technol- became Etaris, and then didn’t. has in store, and we hope this issue ogy news and information. Perhaps takes you on your own walk down Rajiv Roy, FormFactor, said it best In 2013, we created the 3D InCites memory lane. in a testimonial: “As a community, Awards to recognize the contri- 3D InCites brings to life the people, butions people, companies, and the personalities, and the minds

3D InCites Magazine 7 Hybrid Bonding: From Concept to Commercialization

By Françoise von Trapp just an oxide bond,” explained Oxide to oxide initial Fountain. “ZiBond requires the wa- Hybrid bonding is quickly becom- bond at room temperature fer or die surface preparation to be ing recognized as the preferred done in such a way that you reach permanent bonding path for form- a certain bond strength at a certain ing high-density interconnects in temperature.” Exactly what those heterogeneous integration appli- parameters are is part of the secret cations, from 2.5D to 3D stacking sauce. ZiBond is the dielectric bond with or without through silicon that forms the basis for DBI. vias (TSVs), as well as MEMS and III-V applications. In this exclusive Ziptronix and the Road to DBI interview with Gill Fountain, Xperi, winner of the 2018 3DInCites Armed with the ZiBond patent, Engineer of the Year award for his Fountain, Enquist, Tong and several work in this area, we embark on the other colleagues founded Ziptro- journey of how one hybrid bonding nix in 2000 as a spin-out of RTI. technology came to be. Heating Closes Dishing Gap What was Fountain’s vision for the (Metal CTE > Oxide CTE) company next? To combine the di- What Do We Mean by electric bond with embedded metal Hybrid Bonding? to simultaneously bond wafers and form the interconnects. A quick Google search shows that the semiconductor industry has He gives Enquist most of the credit. used the term “hybrid bonding” “Paul was the guy with the vision. I loosely to refer to any alternative to was just the guy in the lab turning thermocompression bonding that the cranks,” he says. combines metal interconnect with some other form of bonding. In I compared them to Woz and Jobs. some cases, it includes adhesives, He laughs and says, “Paul is a bril- such as work done by imec and its liant guy with a lot of good ideas. partners, and by a team at Dalian He has a feel for what would be University of Technology in China.1 Further Heating Compresses good for the industry.” Metal w/out External Pressure In other cases, it involves various At the time, the holy grail of 3D interconnect metals such as copper stacking was how to stack parts (Cu), indium (In), and silver (AG). and form the interconnect as part One example is solid-liquid inter-dif- of the bond process at finer pitches fusion (SLID) developed by Fraun- than was currently possible using hofer Institute.2 Another example wire bonding. Early prototypes is a binary bonding approach that involved cleaning and mounting uses InAg combined with atmo- dies on wafers using ZiBond, and spheric plasma surface activation, Figure 1: DBI bonding process then forming the top connections developed by SET-NA.3 or through the back of wafer with “brute force” methods to connect For the context of this interview, needed a bonding solution that bond pad to bond pad. Fountain hybrid bonding is defined as a would allow for fine-line lithography noted that Sony dabbled in this permanent bond that combines after bonding. The pair turned to staple-like approach, but the struc- a dielectric bond with embedded Q.Y. Tong, described by Fountain as tures were big. They needed to find metal to form interconnections. It’s “the leading guru in wafer bonding”, a more compact and efficient way become known industry-wide as and then manager of RTI’s wafer to make these connections. direct bond interconnect, or DBI™ bonding lab. Together over the (Figure 1). next few years, they developed and Fast forward to 2005 and the emer- patented ZiBond®, an enhanced gence of DBI (Figure 2). The solu- version of direct oxide bond that tion was to start with an oxide bond The early days: involves wafer-to-wafer processing with embedded metal recessed into developing ZiBond at low temperatures (150-300°C) to it. Heat forces the metal together initiate high bond strength rivaling because it expands more than the As Fountain tells it, the DBI story silicon. oxide, causing it to bond, explained began 20 years ago in the labs at Fountain. Initially, nickel was the Research Triangle Institute (RTI), “What differentiates ZiBond from contact material used because it when his colleague, Paul Enquist, other direct oxide bonds? “It’s not polished well with oxide, and some

8 The First Decade particle-free clean surfaces. Addi- place while heating. DBI is limited tionally, the surface and oxide must only by the alignment capabilities be smooth, and the metal has to be of the bonding tool. 1.5µm pitch is slightly below the surface.” the tightest so far at the die level, but that’s because the tools can’t The team figured a few things go smaller, explained Fountain. out along the journey, like what Moreover, the final bond is stron- materials worked best for Cu and ger because unlike TCB, the bond barrier polish and played around forms at both the oxide and metal with pushing temperatures as low interfaces, not the metal only. Figure 2: 10um pitch Ni DBI daisy chain connection as possible to expand the process with Aluminum routing layer (Ziptronix 2010) window to more applications, such Other approaches to hybrid bond- as memory and compound semi- ing that call for adhesives or mixed conductors. metals don’t form as strong a bond as a single metal, explained Foun- “We found that we could readily tain. Adhesives can cause reliability address engineering challenges as- issues due to thermal cycling. Addi- sociated with cleaning and dama- tionally, the bond is hermetic, which scene utilizing the existing equip- positively impacts the reliability of ment sets in foundries today,” noted the end device. Fountain. “Damascene copper is their bread and butter. To complete the fabrication process with a sur- DBI’s Journey to Adoption Figure 3: 2µm pitch Cu DBI wafer to wafer stack face that can be bonded seems like (Ziptronix 2011) a natural progression.” Despite its elegance, it took a while for DBI to take off. Fountain attri- are still using it. The first applica- Advantages of DBI butes that mainly to the industry’s tions to implement DBI were small resistance to change. Early adopt- Fountain says DBI overcomes many pitch parts for focal plane arrays. ers had a need that wasn’t being of the process challenges that They had to reach sub 10µm pitch met in other ways. For example, plague TCB, such as alignment, with 3µm diameter pads. Sony was building its image sen- and bond strength at tighter pitch- sors with adhesives and reached Addressing the Challenges es. The initial bond forms instanta- distortion limits with lithography. neously, the alignment of the parts As foundries don’t like to work with work well, and they don’t slip or “We put a lot of work into this tech- nickel, it was important to get Cu to move as the bond is strengthened nology because we wanted to see work with the process. The biggest during the low-temperature anneal- it become a useful platform for the challenge involved surface cleaning ing process. Moreover, the anneal- industry. It made sense to me that and achieving surface topology ing process can be done in batches Moore’s law would be expanded by (Figure 3). later, which speeds up the process going vertical. Having efficient ways and improves throughput. to combine things would be the “Adhesives are tolerant of particles,” way of the future,” noted Fountain. explained Fountain. “DBI requires With TCB, parts have to be held in “We were a bit ahead of our time,

3D InCites Magazine 9 and it took a while to get traction with the technology. But now we are seeing more and more adopters in the industry.”

The Journey Continues

Several licenses and an acquisition in 2015 by Tessera Technologies (now Xperi) later, Fountain and his team continue to improve DBI, not only to better understand the polishing processes but to achieve ever-changing device requirements so that it can handle a wide range of applications and pitch sizes.

Most recently, Fountain and his colleagues are working on scalable high-volume die-to-wafer bonding, working with different pitch and pad sizes to accommodate high-speed pick-and-place tools that have only 7-9µm alignment accuracy, and a double-sided die preparation pro- Figure 5: 10µm pitch Cu DBI after 2000 temperature cycles of -40°C to 150°C (Xperi 2018) cess to enable sequential stacking for the memory market. dent that it can and ticked off the something that is valuable to a reasons why: It’s compatible with company like Sony just blows my “DBI worked easily at smaller foundry processes, and parts can mind,” he added. pitches and pad sizes because Cu be prepared for bonding right off dishing isn’t an issue. With larg- the line in the fab or OSAT. It can Yes indeed. Now I know why Gill er pad sizes it’s more difficult to handle fine or large features (Figure Fountain was voted Engineer of the get appropriate dishing and a flat 5). Its reliability is good for thermal Year. Well done. ~ FvT oxide surface,” explained Fountain. cycling, high-temperature storage, “We’ve expanded the size of pads and high humidity, which is why it’s References we can polish to 15-20µm.” Metrol- suited to automotive applications. 1. M. Yao, J. Fan, N. Zhao, “Simplified low-tem- ogy for surface topography check perature wafer-level hybrid bonding using has been key to this development pillar bump and photosensitive adhesive for “It’s got a lot of potential. It’s what three-dimensional integrated circuit integra- work, he added, crediting his atom- I’ve known and grown up with my tion”, Journal of Materials Science: Materials in ic force microscope as the core tool whole career. I have a lot of confi- Electronics, January 28, 2017 1149-1150 for this work (Figure 4). dence in it. I’ve seen it do amazing 2. P. Ramm, Understanding Heterogeneous 3D things and have high hopes for its Integration, 3DInCites, January 16, 2015 The Million Dollar Question use in the future,” said Fountain. 3. E. Schulte, M. Lueck, A. Huffman, C. Gregory, Will DBI become process of record K. Cooper, D. Temple, Interconnect structure “The fact that a little place in North for room temperature 3D IC stacking employing binary alloying for high-temperature stability. (POR) across all 3D IC stacking Carolina could have come up with approaches? Fountain is confi- Proc. IW

4-high cross section 50um die stacked 4-high

50um 200um

Figure 4: high DBI Die to wafer stack with 50µm thick die processed at Xperi

10 The First Decade METROLOGY TMAP NST AXIO

for Adv. Packaging for hybrid bonding Review and and MEMS Metrology

ODIN WOTAN THOR 4 SEE

F/B MICRO AOI F/B MACRO AOI Edge AOI Full Inspection system developed for Wafer manufacturers and Power Semi manufactures.

www.unity-sc.com 3D InCites Magazine 11 Advanced Packaging: An IFTLE Historical Perspective

By Dr. Philip Garrou, Microelectronic Consultants of NC

On this 10th Anniversary of 3DInCites, I thought it would be a Figure 1: Packaging evolution through the decades good idea for Packaging InCites from the Leading Edge (IFTLE) to look back at advanced packaging’s aged chips are interconnected, From wire bond to flip chip evolution through 50 years and see have not been able to keep pace. how we came to be where we are. Thus, the package must also serve Packaging technology continued as a “space transformer” (i.e. an to evolve through the decades to The point of the package “interposer” ) to bridge the gap meet miniaturization requirements, between the connection pads on while at the same time offering From the beginning, packaging has the chip and the connection pads more input/output (I/O) by moving been subservient to the integrated on the PCB, which are usually from peripheral wire bonded (WB) circuits (ICs) that they contain. As miss-matched by at least an order technology to area array connec- ICs became more complex, so too of magnitude. tion technology. Packages initially did the packaging and interconnect used WB, and thus the leads exist- technologies that allowed the chips As shown in Figure 1, as we ap- ed only on the chip’s periphery. The to be connected and create circuits proached the 21st century, chip package size was thus determined to accomplish specific tasks. interconnection evolved through by the required number of leads three distinct generations. Initially and their pitch. The chip’s package must always chips were mounted on lead frames provide: and the leads inserted into holes As ICs evolved, more I/O were on the PCB and soldered in place. required then could be accom- • Circuit protection / handling In the surface mount technology modated on the periphery (at a (SMT) era in the 1980s-90s, the usable pitch), which necessitated Form factor for testing • leads were bent into the horizon- a change from peripheral to area array formats, affording many more Heat dissipation tal plane, so the chips could be • soldered to connection pads which I/O at the same pitch. During the • Signal and power distribution were formed on the PCB, to make SMT era, this led to the commer- assembly much more cost efficient cialization of the ball grid array (Figure 2A-C). (BGA) package which functioned to While the dimensions on ICs have continued to shrink year over year in accordance with Moore’s Law, dimensions on printed circuit boards (PCBs), where the pack-

Figure 2: Peripheral Lead frame packages evolve to the BGA

12 The First Decade Figure 3: SMT lead frame packages evolved to the WLP. fan out the IC pitch to an area array (Figure 2D).

Ideally, the IC package should be small and add as little additional interconnect length as possible (to minimize electrical performance degradation). Flip chip (FC) interconnect technology enabled smaller overall package sizes, an area array interconnect footprint, and improved electrical performance. Figure 4: Chips-first and chips-last fan-out packaging

The concept of interconnecting a chips are bumped with the correct die is connected after the intercon- chip with solder bumps in an area size and pitch bumps to allow them nect is formed (Figure 4). array can be traced back to IBM’s to be directly mounted onto PCBs introduction of their system 360 without further packaging. Packaging goes vertical mainframe computer in 1964. For For option two, the chips are several decades after, flip chip was Since all I/O in WLCSP had to exist stacked and connected vertically. confined to high-end main frame under the chip, the package tech- Figure 5 shows the first wave of computer companies like IBM, nology soon became I/O limited. vertical stacking, which used WB NEC, Fujitsu, and Hitachi because Once miniaturization reached chip to stack chips on a common base. it was limited to ceramic packaging size it had two options for future The second wave stacked pack- due to the mismatch between the advancement. age-on-package (PoP) and the coefficient of thermal expansion 3rd wave, seeking to miniaturize (CTE) of Si and the PCB substrate For option one, the industry de- as much as possible, connected [3 ppm/°C vs. 16 ppm/°C (FR4)]. veloped a series of packages that were called “fan-out”. Fan-out WLP die-to-die directly through thinned In 1992, Tsukada of IBM Japan (FOWLP) is “re-configured” by plac- silicon, resulting in die-to-die inter- published reports that bumped ing known-good ICs face down on connect lengths that could be as chips could be reliably attached a foil and over-molding them. These small as 50µm. directly to printed wire board molded wafers are then flipped and laminate if the chips were under- processed in the wafer fab with 3DICs arrive on the scene filled. This announcement drove redistribution layer (RDL)/ball placement and diced. Alternatively, the The 3rd wave of vertical stacking the packaging community to take a became known as 3DIC, which, by hard look at flip chip technology in interconnect is created first, and the a broader application space. By the mid-1990s Motorola had introduced flip chip on board (FCOB) into the StarTac handset.

By the mid-1990s the miniaturization required by cell phones and other portable products created demand for a “chip scale package” (CSP) also called wafer level chip scale package (WLCSP), or more simply, the wafer-level package (WLP). In WLP technology small Figure 5: Chip packaging goes vertical

3D InCites Magazine 13 Figure 6: Miniaturization of vertical interconnect.

Figure 7: Samsung compares PoP to 3D with TSV.

definition, required through silicon suited for memory stacks where vias (TSV), thinning down to 50µm those criteria could be easily met. and a die-to-die area array connec- Hynix and Samsung introduced

tion technology. As bump connec- memory stack products in 2014- Figure 8: 2.5D product introductions tion pitch gets tighter the technolo- 2015. High bandwidth memory gy required a move from tin/lead or (HBM) was adopted as an Industry die-to-die stacking. By 2015 Sony lead-free solder bumps to so-called standard by JEDEC in 2013. announced the separation of the copper pillar bumps (CPB), where sensor and the circuitry and in 2017 While waiting for 3DIC logic, an solder is placed on the tip of a Sony announced the industry’s first impatient industry developed “2.5D” plated copper pillar (Figure 6). For 3-Layer stacked CIS (90nm-gen- technology where a memory stack finer pitches, thermo-compression eration backside-illuminated CIS could be connected on a high den- bonding (TCB) must replace mass top chip, 30nm generation DRAM sity (<1um L/s) silicon interposer to reflow. At sub 30µm pitch, we will middle chip, and a 40nm genera- other chip functions. The first such likely need a direct Cu-Cu bonding tion image signal processor (ISP) commercial product was developed technology to avoid solder shorting bottom chip). and lower signal degradation. by Xilinx and TSMC in 2011-2012 where a mega-FPGA was broken Most technologists currently agree What created high demand for up into four segments to increase that 2.5D and 3DIC solutions will be 3DIC were studies, such as one yields and then reassembled on a key technologies for future devel- done at Samsung (Figure 7) where high-density silicon interposer. opments in areas such as artificial identical systems were compared Intelligence (AI), HPC and robotics, The graphics module market has in PoP and 3DIC. The 3DIC solution just to name a few. showed significant size reduction, also been active in 2.5D with AMD and Nvidia introducing products in power savings and 8X increase in The chiplet concept bandwidth. 2015-2016 and Intel introducing a high-performance compute module A new approach to chip design is While it was clear that 3DIC result- (HPC) in 2015 (Figure 8) also making use of 2.5D technol- ed in the best possible miniatur- ogy. In the same way that Xilinx ization and best possible electrical 3DIC has also been active in the broke up their large FPGA into four performance, it required that chip CMOS Image sensor (CIS) area. In smaller “chiplets”, which could be sizes match, and I/O be standard- 2008 Toshiba commercialized the subsequently reconnected, large ized. It was obvious that it was best first CIS technology using thinned die and backside TSV, but no Continued on page 60

14 The First Decade OVERLAY BUMPS / COPLANARITY HYBRID TECHNOLOGY CRITICAL DIMENSION

TOPOGRAPHY FILM THICKNESS

STEP HEIGHT

SAMPLE THICKNESS / TTV BUMPS / COPLANARITY FILM THICKNESS / LAYER STACK DEFECT INSPECTION

BOND LAYER ROUGHNESS WAFER THICKNESS / IR NANOTOPOGRAPHY

3D InCites Magazine 15 Why Today’s Advanced Packages Need Better Inspection

By Françoise von Trapp

It’s almost ironic. As CMOS scaling (aka: Moore’s Law) has slowed due to the increased complexity and cost of achieving smaller nodes, the focus has shifted to advanced packaging and heterogeneous integration to meet demands for microelectronics devices targeting Figure 1: Defect challenges associated with advanced WLP processes, particularly fan-out-wafer-level packag- the internet of things (IoT) market. ing (FOWLP) These devices perform a variety different thickness wafers, as well approach to fan-out wafer level of functions (sensing, process- as reconstituted wafers (Figure 1). packaging (FOWLP), there are ing, remembering, transmitting) in typically three layers of RDL and smaller spaces using less power. As Hiebert explained it, defect 2-5µm line/space requirements,” Consequently, advanced packages inspection is particularly important said Hiebert. “this calls for up to 16 are therefore designed with finer during wafer level packaging pro- inline inspection steps.” features that require higher densi- cesses for quality control, process ty metal patterns, and multi-layer control, and engineering analysis. It These come at different points redistribution layers (RDLs). helps identify excursions while they throughout the process, the most can still be reworked and repaired, critical are after the lithography de- And suddenly, advanced packag- and again to identify defects that velop step, and again after the etch es have become as complicated can’t be fixed but can cause more process in base-metal etch. and valuable as the chips they are problems if they are allowed to designed to integrate and protect. With higher value comes a higher concern for improved reliability and yields. As a result, foundries who have expanded their advanced wafer level packaging (AWLP) capabilities and outsourced assembly and test service (OSATS) providers are demanding more sensitive, inspection, metrology, and data analysis— and more accurate identification of bad parts. Not quite the level of inspection used in the front end… but something fairly close.

I interviewed KLA’s Lena Nico- laides, Stephen Hiebert, and Pieter Vandewalle to learn about the company’s recent developments in metrology and inspection for AWLP Figure 2a: KLA introduced and final package inspection, two new inspection solutions designed to address some defect targeting advanced WLP types that have become more prevalent as advanced packages have become more delicate. continue through the processes. Defect inspection plays a similar Through in-line monitoring, causes role in test and assembly, although The role of defect inspection of defects can be characterized, the focus is on outgoing quality control, and not necessarily pro- Defect challenges for WLP include and the processes tweaked, with cess control. What’s different for smaller killer defects due to feature the goal of improving final yields. the newest wafer level packages, sizes, nuisance defects due to Additionally, increased package explained Vandewalle, is that previ- complex, dense metal patterns, complexity calls for additional ously wafer level packages did not and high warp wafers and film inspection steps. “In a chips-first go through the same test and in- frame carriers for accommodating

16 The First Decade spection as legacy packages, such as lead frame and substrate-based packages. But now, high-end node chips manufactured with low-k materials, which are more brittle and subject to defects (especially after dicing), require advanced inspection, especially to capture chipping, hairline cracks, and laser groove Figure 2b cracks.

“One reason we decided to pursue this market was that there is no good technology outside of an R&D environment, designed to capture these types of new defects,” he explained. “So, we invested in new IR-based technology for the production environment.”

KLA solutions

More than three years in development, KLA recently launched two new systems, the Kronos™ 1080 and the ICOS™ F160, targeting some specific needs of advanced wafer level, 2.5D and 3D integrated packages (Figure 2).

Building on lessons learned with back-end players could traditionally process control through multi-mode their front-end systems, as well achieve,” she explained. “We de- optics and sensors and advanced as their existing packaging offer- signed these systems’ architecture defect detection algorithms. Its ings, CIRCL™-AP, and the ICOS™ and algorithms for a superior cost proprietary FlexPoint™ technolo- line, the company worked in of ownership, ability to find defects gy focuses the inspection system close partnership with its existing while offering increased throughput on key areas within the die where customers to identify the gaps in and overall yield improvement.” defects would have the highest current inspection strategies, and impact (Figure 3). develop these systems, explained AWLP process inspection Nicolaides Final package Inspection The Kronos 1080 system is de- “Our customers who lead in scaling signed to inspect AWLP process Vandewalle described the chal- technology came to KLA looking steps, providing information on the lenges in final package inspection for sensitivity beyond what the full range of defect types for inline that the ICOS F160 is designed to

Figure 3: Kronos 1080 inspects the incoming wafers, performs in-line inspection at specific inflection points when wafers can be reworked, and then is used for outgoing quality control

3D InCites Magazine 17 address, namely low-k cracks on sidewall and laser grooves that are difficult to detect. The system’s purpose is to be used in high-volume manufacturing to separate out the bad parts and keep the good.

In designing the ICOS F160, Van- dewalle said the focus was finding a solution to address dicing cracks caused by an aggressive dicing practice. Existing approaches relied on either optical or open/short tests, but none was good enough to capture critical defects. He said that as a result, the packages fail in the end-use device, and mobile and wearable companies are suffering from the slip-through.

The ICOS F160 features IR inspection, which provides robust detection of invisible killer crack defects for fan-in WLP, memory and bare die. In combination with 6-side optical inspection with pre- and post-placement inspection, the

ICOS F160 enables high die sorting Figure 4: ICOS F160 key technologies to address high volume die sort challenge. accuracy. Additionally, the system’s flexibility allows it to support a variety of workflows, including wafer- sion. Because advanced packaging said Nicolaides. “After analyzing the to-tape and tape-to-tape. Lastly, technologies are so much more requirements of the diverse pack- fast conversions, automatic calibra- varied than front-end processes, age designs, we focused on defect tion, and precision die pickup ad- the greatest challenge for KLA was sensitivity and inflection points to dresses the needs of high-volume developing systems next-gener- leverage our optical expertise.” manufacturing (Figure 4). ation inspection systems that are both flexible and high-performing. The result of that focus has been Where the action is realized in the addition of these two “There’s always a trade-off. The systems to their product portfolio. While CMOS scaling may continue, more flexible you make some- ~ FvT advanced WLP is clearly where the thing, the more challenging it is to action is, driven by the IoT explo- achieve optimized performance,”

18 The First Decade Diversification of Markets Calls for Hybrid Metrology with Multi-Sensor Technology

By Françoise von Trapp Metrology for metrology tool providers are used Advanced Packaging to serving. People used to think about metrology for front-end process control “For the past two years, we’ve had “With MicroProf® AP, we succeed and inspection in semiconductor a strong demand for tools that to accommodate measurement manufacturing only. As wafer level perform different metrology tasks,” requirements for different process- packaging (WLP) and heteroge- noted Fries. “Inspection used to be es, and we are able to handle both neous integration (HI) approaches the standard, but now metrology is wafers and panels, thinned and became more advanced, metrology becoming a must-have.” He went bonded wafers, and film frames,” processes began creeping into on to explain the impact the lack of noted Fries. back-end process control, where mainstream processes is having on measurement becomes trickier metrology solutions providers. Additionally, he says he doesn’t and more diversified. I spoke with expect the players to settle on one Thomas Fries, CEO of FRT, winner Despite continued efforts to scale approach for all, because different of the 2018 3D InCites Equipment CMOS structures to smaller nodes, applications call for different device Supplier of the Year Award. We metrology needs are fairly straight- architectures, which in turn require talked about how technology forward thanks to standardization different processes. He does, how- diversification is here to stay, and of tools and processes. This is ever, expect a narrowing of options. how hybrid metrology solutions not the situation for metrology in using multi-sensor technology are the advanced packaging space. “For FRT this is a fantastic situa- becoming necessary. Measuring total thickness variation tion,” said Fries. “Our early decision (TTV) on a wafer is not the same as to focus on building tools with mul- measuring TTV with a very high lat- tiple sensors and to program our eral resolution. Additionally, through own software in-house is paying off. silicon vias (TSVs), Cu bump or We are perfectly set up for doing pillar heights, as well as thinning, hybrid metrology with multi-sensor bonding and stacking are bringing technology, which is what is need- new metrology needs compared to ed for these complex processes.” classical process steps. The hybrid metrology solution Diversity changes everything So what exactly is hybrid metrol- The dawn of fan-out (FO) process- ogy? Fries explains that for FRT, it es both at the wafer and panel means using its multi-sensor con- level has added more diversity to cept so that in one recipe, different metrology needs. Add to that 2.5D properties on a device can be auto- and 3D heterogeneous integration, matically measured. Up to ten fully and now chiplet technologies and integrated sensors act as one to the diversity of the space con- automatically embed different infor- tinues to broaden. This is mation and create new information not the that isn’t directly available. volume-driven market tier-one Fries explained further: In the same tool, you can now, for example, measure the height of a Cu bump Figure 1: Thomas Fries, against the oxide in silicon in the CEO FRT, accepts the same machine. The step height of 3DInCites Award outside the FRT cleanroom the Cu is measured optically, and a film thickness sensor is used to measure oxide thickness. By subtraction, the film thickness, the height of the Cu above the oxide can be determined.

Additionally, with the company’s third generation of tools, the up-to-date, in-house developed software, achieves 64-bit status.

3D InCites Magazine 19 ® FRT recently launched a new wafer MicroProf AP metrology tool, the MicroProf® AP, designed for advanced packaging. It allows fully automated processing of 300mm FOUPS/FOSBs and 300 mm/200 mm/150mm open cassettes. The system can handle SEMI standard wafers, highly warped wafers (e.g. eWLB), bonded wafers, wafers on tape, TAIKO, bare and thinned wafers, and even fan-out wafers. Moreover, the tool can be configured for processing frame cassettes and handling of panels. The handling part features a robot with end-effector, two load ports including mapper and RFID reader, pre-aligner and optional OCR reader stations. It can be used for all metrology tasks within the advanced packaging process, e.g. measurement of photo resist (PR) coatings and structuring, through silicon vias (TSVs) or trenches after etching, μ-bumps and Cu pillars, as well as for the measurement in thinning, bonding and stacking processes.

As standard configuration, the MicroProf® AP is equipped with a granite base setup, with a three- point sample fixture or a vacuum RT practices the Art of Metrology chuck. Besides that, numerous features can be added or retrofitted on site at a later time.

This so-called hybrid metrology “The market is interesting and gives The best of both worlds tool is the perfect fit for diversified us lots of options. But it’s important markets, says Fries. “It paradoxical- that we focus on niche markets and What Fries likes best about FRT is ly solves what the customer wants: not try to do everything,” he said. having the flexibility and capability a standard tool that can follow an “The newest, hottest applications to serve both niche and high-vol- established roadmap with on-site call for new processes and metrol- ume markets. The company’s upgrades and can also handle di- ogy tools and have to be flexible to hybrid metrology and inspection verse process steps and the ability adapt to new process quickly. This solutions suit the current climate of to customize solutions,” he said. isn’t what the tier-one suppliers application diversity perfectly. focus on. They aren’t keen on serv- Serving niche markets ing niche markets because the low Usually, a company decides to volumes don’t make it worthwhile.” pursue tier-one or niche customers. Fries firmly believes that the key This is not the case for FRT. Even to success does not lie in trying As a result, he says the competitive though they focus on serving the to be all things to all people. With overlap is diminishing. “We don’t niche markets, their toolbox allows this in mind, his strategy is to focus meet most of those competitors them to support both, combining on three growing specific markets: in the market anymore,” notes the best of both worlds. advanced packaging, MEMS, and Fries. “There’s room for all of us to LED applications. succeed.”

By the magic of FRT’s software developed in- Measure the Immeasurable house, it is possible to measure things that previously couldn’t be measured. The configuration of various measurement tasks using different sensors to run consecutively within a measurement sequence is simplified. Add to that, this software provides comprehensive capabilities, from manual measurement on the device to fully automated measurement with one button operation and integration into production control systems, e.g. via a SECS/GEM interface.

By using a hybrid metrology concept - this multi-sensor metrology tool enhances the precision of measurements on samples where a single sensor or measuring principle is just not enough. Depending on the task, this may include measurements with different topography and (film) thickness sensors that are fully automated by a single recipe.

20 The First Decade 3D Test: No Longer a Bottleneck! By Erik Jan Marinissen – imec, Leuven (Belgium)

When I joined imec in October 2008 to work on test and design-for-test (DfT) of 3D-stacked integrated circuits (ICs), there were only a few test folks active in that emerging field. Consequently, misconceptions about 3D test were om- ni-present. In the November 18, 2008 issue of Semiconductor International, Alexander Braun wrote: “At a symposium yesterday on 3-D integration, leading expert Philip Garrou detailed the rise of the technology as well as the challenges facing it, including test, yield, and design. (…) Test, again, will be a significant problem. Memory can be stacked as known good die, because the memory chips can be tested, but years from now, as different functions are pulled apart to stack them, there is no clear way to test them because they do not form a complete circuit. This will hold up things like the full partitioning of chips.”1 3D InCites’ tenth anniversary is a good occasion to report on the state of 3D testing and publicly declare that it's no longer a bottleneck for 3D integration.

Structural Modular Test needs to be tested, and hence present, operational, and correctly the test needs to be very efficient; interconnected. We refer to this as ‘Test’ is an overloaded term. While taking no more than a few sec- a structural test (as opposed to a some people might think of design onds per chip in a fully automated functional test). verification (on a simulation model) process. or design validation (on the real For a structural test, testing a chip), this article is restricted to During test, stimuli are fed into the single die that only implements a electrical testing for manufacturing chip and corresponding responses partial function of a multi-die stack defects, typically in a high-volume on the chip outputs are compared is no problem at all. This modular setting. At this stage of product to expected responses to deter- approach to test development and development, we assume chip mine ‘pass’ or ‘fail’. Automatic test execution has become common designs are correct. Chip manufac- pattern generation (ATPG) tools, practice in the industry. turing processes are defect prone available from all major EDA suppli- as they consist of large numbers of ers, try to cover as many potential Today’s core-based system-on- high-precision steps. Unavoidably fault locations as possible with a chips (SOCs) are routinely tested in things go wrong every now and minimum of test patterns to reduce a modular fashion: core-by-core, then, leading to spot defects such test time and associated cost. sequentially, or at the same time.2 as shorts and opens. For 3D integrated circuits (3D ICs), ATPG tools do not utilize applica- for which the various stacked dies For a large chip manufactured tion knowledge of the device-un- might be designed and/or manu- using advanced technology, the die der-test (DUT), but instead base factured by different parties, modu- yield might be 80%, while custom- themselves on the DUT’s structure: lar testing (here: die-by-die) makes ers typically tolerate defective chips the gate-level netlist with inter- even more sense. The benefits in quantities of no more than 100 connected library-cell instances include: defective parts per million (dppm). (AND, OR, flip-flop, etc.). Consequently, a test needs to be The resulting test patterns a very effective filter for defective have no relation with the chips. Because every transistor or mission-mode (‘functional’) interconnect segment on a chip operation of the chip, but can suffer from defects, each chip check if these cells are

Figure 1a: Example test flow for n=3: maximal 11 die tests and 5 interconnect tests. Figure 1b: Equations for t(n) as function of the number of dies in the stack n. Figure 1c: Number of test t(n), for increasing number of stacked dies n. Figure 1d: Number of alternative test flows f(n), for increasing number of stacked dies n.

3D InCites Magazine 21 • Targeted test pattern genera- reduces the number of feasible f(n) as function of the number n of tion, tailored to the circuit type tests. A test flow consists of an stacked dies.3 (e.g., logic or memory) and func- execution decision (yes/no) for each tion, preferably by the team also test at each feasible test moment. If The large numbers of alternative responsible for the design a die stack has a total of t(n) tests, test flows necessitate computer this allows for f(n)= 2t(n) alternative support. The 3D-COSTAR software • Freedom to (re-)schedule the test flows. Note: this definition of tool, developed by TU Delft and various die tests if manufactur- f(n) does not account for alternative imec, makes a cost analysis of a ing yields so require (test engi- test schedules due to reordering of user-specified manufacturing and neers like to put tests that are tests at a particular test moment. test flow.4 The tool considers costs more likely to fail early in their proper to design, as well as five test suite, to reduce the per-die Figure 1(a) illustrates the test flows manufacturing operations: average test time by applying for a relatively simple stack with ‘abort-on-fail’) only three dies, resulting in 16 tests 1. Wafer processing (11 die + 5 interconnect tests), and • Re-use of tests in case design therefore a total of 216 = 65,536 2. Stack assembly modules are reused alternative test flows. 3. Test First-order fault diagnosis and In practice, some test moments • 4. Packaging yield attribution (because: if the might not permit probe access, and test for a particular module fails, this reduces the number of feasible 5. Logistics that module most likely contains tests and test flows. For example, the root cause) for imec’s FC-FOWLP test chip These operations are considered consisting of seven dies, from the not perfect and are modeled with Test Flow Optimization theoretical 68 tests only 33 tests an associated yield in percent. For are practically feasible; which still A major difference between testing test, ‘yield’ is defined as 100% mi- implies a whopping 233 ≈ 8.6 ⅹ 109 2D and 3D ICs is the potential nus the test escape rate (in dppm). alternative test flows. complexity of the test flow. At which 3D-COSTAR calculates the lump- moments in the manufacturing flow sum costs per operation, where all Figure 1(b) shows the generic costs are attributed to those stacks do we execute a test for what stack equations for t(n) as function of the component? Conventional 2D chips that pass the entire flow and are number of stacked dies n. Figures shipped to the customer. The tool typically have two test moments: 1(c) and 1(d) depict t(n) respectively first while still in their wafer (wafer can analyze the effect of varying test, a.k.a. e-sort), to avoid package costs for defective dies, and then again after assembly and packaging (final test), to guarantee the outgoing product quality toward the customer. 3D ICs have many more test moments, tests, and hence test Essenal test and measurement technologies flows. For an n-die stack, we have for Advanced Packaging and more... prior to stack assembly n possible test moments during which we can execute a pre-bond test on a die. After every stack assembly operation, we have a new test moment, in which each die and interconnect layer in the stack built up so far can be tested. We refer to these test moments as mid-bond tests (for partial stacks) and post-bond tests (for complete stacks). There are n n ∑ i=2 (i) die tests and ∑ i=2 (i-1) interconnect tests possible during these test moments. After packaging, the final test can contain n-die tests and (n-1) interconnect tests. In total, an n-die stack has 2n test moments during which a grand total of n 2n-1+ ∑ i=2(i) die tests and n n-1+∑ i=2 (i-1) interconnect tests might occur. In practice, there might be no physical test access during certain test moments, which

22 The First Decade Figure 2: ‘Vortex-2’ test system in imec’s Fab-2, based on FormFactor’s CM300 probe station (a), has been used for probing large-array 40µm-pitch µbumps with advanced probe cards. FormFactor’s Pyramid® RBI probe cards (b) left small probe marks on ø25µm Cu µbumps (c), and Technoprobe’s TPEG™ T40 probe cards (d) left barely visible probe marks on ø15µm Cu/Ni/Sn µbumps (e). an arbitrary number of parameters Probing Challenges frame can be loaded manually.6 The (in lock-step) along one or two in- and Solutions Tokyo Electron WDF™-12DP probe dependent axes, as variations of a stations even have an automatic user-defined base case. The output For most product scenarios, loader for such large tape frames.8 of the analyses is an estimation realistic yields require a combina- of product quality (defective chips tion of pre-bond, mid-bond, and Probing ultra-thin wafers on a that nevertheless pass the test, in post-bond testing. This prevents flexible tape. dppm) and the cost per shipped manufacturing defects from being Wafer thinning is commonly stack, sub-divided over the subse- discovered too late in the stack-as- performed on dies used in multi- quent manufacturing operations. sembly flow thus requiring the en- die stacks: from 780µm down to tire stack to be scrapped, including ~200µm to fit the stacked dies into Test Access perhaps other (defect-free) dies. a standard-height package cavity Whereas test access contact for or, when TSVs are employed, even The main challenges of 3D testing final test is made through a test thinner to expose the TSVs at the are related to test access: deliver- socket, the pre-, mid-, and post- wafer back-side (at imec: 50µm). ing test stimuli to where they can bond tests all depend on probe Stretched UV-curable dicing tape, detect the presence of a defect, technology. For multi-die stacks, laminated over a tape frame, is and the test responses in the the following probing challenges commonly used as a temporary opposite direction. Test access have been identified and resolved in carrier to prevent ultra-thin wafers comprises two components: collaboration with our partners.5 from sagging and curling. external test access, i.e., from the test equipment to the chip I/Os and Probing on large tape frames. The forces exercised by probe back, and internal test access, i.e., Stack-assembly flows for multi-die needles should be sufficiently high from the chip inputs to the actual stacks frequently use tape frames to guarantee an acceptable low on-die defect location and back to as a temporary carrier: for diced contact resistance between each the chip outputs. wafers, for aggressively thinned- probe tip and its corresponding down wafers, for pick-n-placed dies probe pad. However, when we do With external test access, several and die stacks, etc.6 Out of neces- this on an ultra-thin and flexible challenges and their solutions re- sity, a tape frame is larger than the wafer atop flexible dicing tape, we lated to probing on ‘naked’ (= not- wafer it holds; for a ø300mm wafer, should avoid probe forces that yet-packaged) dies or die stacks the outer dimension of the frame is cause permanent or even tempo- are described below. Internal test ø400mm.7 rary stress-induced electrical or access is handled by on-chip mechanical effects and damage. DfT hardware. The conventional Imec worked with Cascade Micro- (‘2D’) DfT has been extended with tech (now FormFactor) to specify At imec, we have done numerous 3D-specific features, and those are and implement adaptations to experiments with probe cards that described at the end of this article. the CM300 probe station, so that require different probe forces: con- ø300mm wafers on a large tape ventional cantilever, FormFactor’s

3D InCites Magazine 23 Pyramid® and Pyramid® RBI (Rock- tine basis. Recently, we reported partly at imec), and tested success- ing Beam Interposer) MEMS-type on a case study where all probing fully a demonstrator IC containing probe cards, and Technoprobe’s challenges described above and the proposed 3D-DfT.13, 14 ARIANNE™ and TPEG™ probe their proposed solutions, were ap- cards. We recommend a low-force plied in a combined fashion.5 The EDA tool flows were made probe card in this situation. available as a rapid adoption kit 3D-Design-for-Test (RAK) to Cadence customers, used Probing large arrays of fine- Architecture for several TSMC test chips, and pitch micro-bumps. released as TSMC Reference Flow The interconnect between stacked For transportation of stimuli and for CoWoS and 3D-IC. We extend- dies consists of large arrays responses within the die (stack), ed the basic architecture with pro- (>1,000) of Cu and Sn micro-bumps we need on-chip DfT. Convention- visions for memory-on-logic stacks; at ultra-fine pitch: 40µm. Imec has al 2D-DfT includes internal scan logic dies to be complex SOCs developed a unique test system chains, test data compression to with a hierarchical design and test to characterize probe cards that handle large dies, core-test wrap- approach, containing embedded IP claim to be capable of probing pers around embedded cores and cores and test data compression; such micro-bump arrays. It consists other design units that will be test- for multi-tower stacks to support of a FormFactor CM300 probe ed as stand-alone units, and built-in at-speed test of the inter-die inter- station with hard-docking National self-test hardware for embedded connects; and to create realistic Instruments test head with 1,216 memories. The term ‘3D-DfT’ refers test conditions by controlling the parametric tester channels.9 to on-chip DfT features that are switching activity of dies and cores explicitly added to handle 3D ICs. neighboring to the current mod- Imec has in-house manufactured ule-under-test.15, 16, 17, 18 test wafers with only micro-bumps A 3D-DfT architecture should (>10 million micro-bumps at 40µm support a per-die modular test 3D-DfT Standardized: pitch on a ø300mm wafer) in var- approach and therefore requires IEEE Std P1838 ious metallurgies. This set-up has wrappers at die level, such that been successfully used to charac- the various dies and their inter-die To guarantee interoperability of the terize advanced micro-bump probe interconnects can be tested inde- 3D-DfT architecture across the cards which imec co-developed pendently from each other. Where- various dies in a stack, especially if with leading suppliers: FormFac- as conventional 2D core wrappers these dies are designed by different tor’s Pyramid® RBI and Techno- (as specified by IEEE Std 150012) teams or companies, a standard- probe’s TPEG™ T40.10, 11 have one test input and one test ization effort was needed. This was output port, a 3D-DfT die wrapper done under the umbrella of IEEE Probing singulated dies and die should support multiple test ports. Standards Association, as other stacks on a flexible tape. DfT standards reside there as well. The challenge is that the probe A die has its test data to and from targets might have translated or the test equipment enter and exit In 2011, I founded a standardiza- rotated from their original wa- via its primary test port. In case one tion working group under IEEE fer-map position, such that blind or multiple other dies are stacked sequence number P1838. Stan- index stepping by the probe station directly on this die, it will also have dardization is intrinsically a slow is no longer possible. This happens a corresponding number of sec- process, but after eight years, the when probing on diced wafers or ondary test ports, which each serve draft standard is finally nearing diced stacks on dicing tape, due as a plug for the primary test ports completion. At the end of 2018, to the flex-n-stretch forces of the of one of these stacked dies. In this the ballot group has been formed dicing tape). way, test stimuli can enter the stack and in 2019 the actual ballot will through the primary test port of the take place, hopefully leading to an Another application is pick-and- base die, be transported up in the approved standard still in the same place of die-to-die stacks on a stack, possibly through other dies, year. IEEE Std P1838 standardizes carrier substrate, as the pick-and- to reach the destination die where per-die 3D-DfT features, such that if place tool might be insufficiently they execute their defect detection compliant dies are brought together accurate for subsequent probing.8 work; likewise, test responses need in a die stack, a basic minimum of Together with our partner Form- to be transported from the DUT cooperative test access is guaran- Factor, we have developed and through other dies in the stack teed to work across the stack.19 successfully demonstrated soft- down to the external stack I/Os. ware that determines the individual IEEE Std P1838 consists of three misalignment per die or die stack at Imec defined and patented a main components: a die wrapper the start of the wafer probe session 3D-DfT architecture that meets register (DWR), a serial control and then compensates for it while these requirements, initially for sin- mechanism (SCM), and a flexi- probing.8 gle-tower logic-on-logic die stacks ble parallel port (FPP). DWR and (Figure 3). With Cadence Design SCM are 3D extensions of existing Originally deemed impossible when Systems we developed EDA tool standards IEEE Std 1500 and IEEE we started to work on this topic in flows for DfT insertion and test gen- Std 1149.1, respectively. The FPP, 2011, today imec is probing 40µm- eration; and we designed, manu- a novel feature of P1838, is an op- pitch micro-bump arrays on a rou- factured (partly at GlobalFoundries, tional, scalable multi-bit (‘parallel’)

24 The First Decade Figure 3: ‘Vesuvius-3D’ two-die stack containing a 3D-DfT demonstrator14 (a), overview of the IEEE Std P1838 3D-DfT architecture (b), and detail view of P1838’s serial control mechanism on a single die with two secondary ports (c)19.

test access mechanism that offers volumes of products with won- delivered, adequately and, while the higher bandwidth compared to the derful new performance/storage/ first products are hitting the market, one-bit (‘serial’) mandatory part of bandwidth features on the market, just on time! P1838.20 if these products are not individually tested for defects. Customers do If you want to read more about 3D Conclusion not accept that. (test) challenges and solutions: they are described in detail in the DfT and test engineers know the The mere fact that the test com- book “Design, Test, and Thermal limits of their work. Our industry is munity started working on 3D Management”, edited by Paul D. not making chips because the test ICs was a clear sign that release Franzon (NCSU), Erik Jan Marinis- community has developed a fancy of actual 3D products was immi- sen (imec), and Muhannad S. Bakir test solution for them; customers nent. With the solutions described (Georgia Institute of Technology). would not care. They are interested in this article, most of the test in more performance, more storage challenges related to 3D ICs have This book is Volume 4 in the well- capacity, and higher bandwidth, been addressed, such that we can known book series “Handbook of benefits which can be achieved conclude that ‘test’ is no longer a 3D Integration”, published by Wi- with 3D ICs. But, on the other bottleneck for market introduction ley-VCH and available from March hand, our industry cannot put high of 3D ICs. The test community has 2019 onward.

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3D InCites Magazine 25 About the Author Daniele Acconcia, Raffaele Val- fine-pitch micro-bump probing lauri (Technoprobe), Paul Mooney, (https://forums.ni.com/t5/NI-Blog/ Eric Pradel, Yoichi Shimizu (Tokyo Changing-the-World-with-Sci- Electron), Sandeep K. Goel (TSMC), ence-and-Engineering-2017-Engi- Sergej Deutsch (TU Braunschweig), neering/ba-p/3615313). Said Hamdioui, Motta Taouil, Jouke Verbree (TU Delft), Hailong Jiao (TU Erik Jan Marinissen received the Eindhoven), Konstantin Shibin (TU Emerging Technology Award 2017 Tallinn), and Michael Wahl (Univ. from the IEEE Standards Associa- Siegen). tion “for his passion and initiative supporting the creation of a 3D Test Part of this work was performed in Standard” (https://standards.ieee. the project ESiP, ‘Efficient Silicon org/about/awards/etech). Multi-Chip System-in-Package Integration – Reliability, Failure Anal- References

ysis and Test’, funded by the ENIAC 1. Alexander Braun, ‘3-D Integration Lacking in Joint Undertaking (http://www.eni- Design and Test Support’, Semiconductor ac.eu). This project was winner of International, November 18, 2008 Erik Jan Marinissen is principal sci- the ENIAC Innovation Award 2013. entist at imec in Leuven, Belgium, 2. Erik Jan Marinissen and Yervant Zorian, ‘IEEE Part of this work was performed in 1500 Enables Modular SOC Testing’’, IEEE the world-leading independent R&D Design & Test of Computers, Special Issue the project SEA4KET, ‘Semicon- center in nanoelectronics technol- on ‘IEEE Std 1500 and Its Usage’, Volume 26, ductor Equipment Assessment for No. 1 (January/February 2009), pp. 8-17, DOI ogy. His research on IC test and 10.1109/MDT.2009.12 Key-Enabling Technologies’ (http:// design-for-test covers topics as www.sea4ket.eu), sub-project 3. Arnita Podpod, Dimitrios Velenis, AlainPhom- diverse as 3D-stacked ICs, CMOS 3DIMS, 3D Integrated Measurement mahaxay, Pieter Bex, Ferenc Fodor, Erik Jan below 10nm, silicon photonics, and Marinissen, Kenneth June Rebibis, Andy Miller, System, which received funding Gerald Beyer, and Eric Beyne, ‘High Density STT-MRAMs. Marinissen is also from the European Union’s Seventh and High Bandwidth Chip-to-Chip Connec- visiting researcher at Eindhoven tions with 20µm Pitch Flip-Chip on Fan-Out Programme for research, techno- Wafer Level Package’, Intnl. Wafer-Level University of Technology in the logical development, and demon- Packaging Conference (IWLPC’18), San Netherlands. Previously, Marinissen Jose, CA, USA, October 2018, DOI 10.23919/ stration under grant agreement No. IWLPC.2018.8573262 worked at NXP Semiconductors IST-611332. and Philips Research in Eindhoven, 4. Mottaqiallah Taouil, Said Hamdioui, Erik Jan Nijmegen, and Sunnyvale. Marinissen, Sudipta Bhawmik, ‘Using 3D-CO- Awards Related to This Work STAR for 2.5D Test Cost Optimization’, IEEE In- ternational 3D Systems Integration Conference Marinissen is (co-)author of 250+ (3DIC’13),San Francisco, CA, USA, October Erik Jan Marinissen received the 2013, pp 1-8, DOI 10.1109/3DIC.2013.6702351 journal and conference papers Meritorious Service Award from the (h-index: 43) and (co-)inventor of Test Technology Technical Council 5. Erik Jan Marinissen, Ferenc Fodor, Arnita 18 patent families. He has received Podpod, Michele Stucchi, Yu-Rong Jian, of IEEE Computer Society “for sig- and Cheng-Wen Wu, ‘Solutions to Multiple numerous awards for his work and nificant services as Program Chair Probing Challenges for Test Access to Multi-Die is very involved in IEEE conferences Stacked Integrated Circuits’, IEEE International of the IEEE International Workshop Test Conference (ITC’18), Phoenix, AZ, USA, and standards. Among them, he on Testing Three-Dimensional October 2018 served as editor-in-chief of IEEE Std Stacked ICs (3D-TEST) since 2010”. 6. Erik Jan Marinissen, Bart De Wachter, Teng 1500 and as founder/chair (currently Wang, Jens Fiedler, Jörg Kiesewetter, and vice-chair) of the IEEE Std P1838 Karsten Stoll, ‘Automated Testing of Bare Mottaqiallah Taouil, Said Ham- Die-to-Die Stacks’, IEEE International Test Working Group on 3D-SIC test dioui, and Erik Jan Marinissen Conference (ITC’15), Anaheim, CA, USA, access. October 2015, Paper 20.2, DOI 10.1109/ received the Technology Transfer TEST.2015.7342412 Award 2015 from HiPEAC for the Acknowledgments 3D-COSTAR Test Flow Optimiza- 7. SEMI G74-0669 Specification for Tape Frame for 300mm Wafers. Semiconductor Equipment tion Tool (https://www.hipeac.net/ I thank many colleagues and and Materials International, San Jose, CA, USA, news/6774/hipeac-tech-transfer- May 1999 partners for their fruitful coopera- award-2015-winners-announced/). tion: Alkis Hatzopoulos, Leonidas 8. Tokyo Electron Notification, ‘Tokyo Elec- Katselas (Aristotle Univ. of Thessa- tron (TEL) Introduces a Dual Purpose Imec received the Research Insti- 300mm Dicing Frame Prober’, November loniki), Teresa McLaurin (Arm), Vivek 2008 (see http://www.tel.com/news/top- tute of the Year 2017 award from ics/2008/20081104_001.html) Chickermane, Brion Keller, Christos 3DInCites (https://www.3dincites. Papameletis (Cadence Design com/3d-incites-awards/2017-3d-in- 9. Erik Jan Marinissen Ferenc Fodor, Bart De Systems), Tobias Burgherr (FHNW), Wachter, Jörg Kiesewetter, Eric Hill, and Ken cites-awards-winners/). Smith. ‘A Fully Automatic Test System for Char- Eric Hill, Jörg Kiesewetter, Ken acterizing Large-Array Fine-Pitch Micro-Bump Smith (FormFactor), Sandeep Bha- Probe Cards’. In Proc. IEEE International Test Ferenc Fodor, Bart De Wachter, Conference Asia (ITC-Asia), September 2017, tia (Google), Pieter Bex, Eric Beyne, Erik Jan Marinissen, Jörg Kie- DOI 10.1109/ITC-ASIA.2017.8097130 Bart De Wachter, Ferenc Fodor, sewetter, and Ken Smith received 10. Erik Jan Marinissen, Ferenc Fodor, Bart De Mario Konijnenburg, Arnita Podpod, the Engineering Impact Award Wachter, Jörg Kiesewetter, Ken Smith, and Michele Stucchi (imec), Yu Li, Ming Eric Hill, ‘Evaluation of Advanced Probe Cards 2017 from National Instruments for Large-Array Fine-Pitch Micro-Bumps’, Shao (KU Leuven), Chun-Chuan Chi in the category Electronics and Chip Scale Review magazine, Volume 21, No. (NTHU), Adam Cron (Synopsys), Semiconductors for large-array Continued on page 60

26 The First Decade Special Section: The Past, Present and Future of 3D Integration

On this, the occasion of the 10th Anniversary of 3D InCites, we asked our advisory board and other members of the industry to reflect on the past 10 years of the 3D integration journey, and answer two questions:

What was the single most pivotal event (good or bad) in the last 10 years that Looking into your crystal ball, where impacted the commercialization of 3D will 3D and heterogeneous integration 1 integration technologies? 2 technologies take us in the next 10 years? The responses we received ranged from insightful comments and personal reflections, to longer editorial contributions and analyses, both market and technical. Every contribution offered insight and perspective, so we chose to create this special section featuring them all. Enjoy!

3D InCites Turns 10: A Brief say, time flies! Taking a step back, I The Birth of 3D Analysis of the 3D Journey have to admit a lot of progress has been made since my first atten- This may not be considered ‘3D By Yann Guillou, Trymax dance as a young engineer to the integration’ by many people (includ- EMC 3D workshops back in 2008. ing me) but the CMOS image sen- At that time, we were discussing sors (CIS) that use via-last through how to form a via, how to fill it, how silicon via (TSV) interconnect tech- to use a temporary wafer carrier to nology were a very significant step process thin wafers…etc. in the commercialization of 3D. The Industry started to discover layers We are definitely more mature now could be stack on top of each other (not old!) and I’m convinced 3D with direct connections, and with InCites contributed to the progress much higher performances than die by sharing knowledge across the stack using wire bonds. This was industry. the starting point.

I’m honored to have been part of The teenage years their advisory board since 2010 under the enthusiastic leadership of Stacking memory dies and application process engines in high- I cannot believe 3D InCites is Franҫoise. Following is my simple end cell phones (now known as already turning 10! As wise people analysis of our 3D journey so far. smartphones) was identified as

3D InCites Magazine 27 a potential killer application to upon the manufacturer but can be deliver high bandwidth at lower summarized as: 1) adding func- power consumption and with very 3D Powered: From Image Sen- tionality; 2) decreasing form factor; small vertical dimension. How- sors to Edge Computing 3) enabling flexible manufacturing ever, thermal budget constraints options; and 4) facilitating optimiza- and business model/supply chain By Paul Werbaneth, Nor-Cal tion for each die in a 3D stack.” limitations killed the high hopes. Products, Inc. Hopefully, Xilinx and AMD made Who talks on their phone them in a slightly different way. anymore? However, the volume they manufactured cannot be compared to Sure, people like their smartphones how things would have been if a for texting, talking, and surfing the flagship smartphone manufacturer internet, but people really like their had decided to embark on using smartphones for recording videos wide IO memory with processor. In and snapping still photos, and the meantime, cell phones started when you build a better camera using TSMC’s integrated fan-out into a phone you’ve built a better (InFO) in a package-on-package phone. Engadget UK ranks the (PoP) configuration, which was most important smartphone fea- already a great achievement with tures this way: significant benefits. The widespread deployment of 1. Design and build quality 3D stacked CMOS Image Sensors Screen (CIS) in consumer electronics, 2. namely smartphones, by handset Great camera makers domestic (Apple, iPhone) 3. and overseas (Samsung, Galaxy), 4. Headphone jack is certain proof that 3D integration technologies pivoted over the last 5. Battery life ten years from being something useful only for fairly esoteric appli- 6. Processor power cations and high ASP products, to being a technology that reached 7. Price the right market, at the right cost, A picture’s worth a thousand at the right time, in volumes high words, and even if Andy Instagram enough to push yields up, costs or Sally SnapChat don’t know it, 3D down, and, in Sony’s case particu- stacked CIS have made their social larly, put money in the bank. media feeds insanely great. An exploding market

According to Yole Developpement, as reported by Peter Clarke, “The (CIS) market was up 19.8% from $11.6B in 2016 mainly driven by smartphones and the desire to add improved cameras. However, Yole believes the CMOS image Endless opportunities sensor has a bright future driven I still believe that system-on-chip by new applications in autonomous (SoC) disintegration with IP blocks vehicles and industrial and machine designed at their optimized tech- vision. By 2023 Yole predicts the nology nodes and then stacked on annual market will have climbed to top of each other could happen. more than $23B, a compound an- This is the next step after the new nual growth rate of 9.4% from 2017 system-in-package (SiP) develop- to 2023.” That’s a lot of Simoleans. ment we see now, and it should And that’s a lot of CIS. Is AI the next stop for 3D ICs? be part of the heterogeneous As Coventor reports, “A 3D-stacked integration roadmap. The recent Where will 3D and heterogeneous image sensor consists of a back- announcement of Intel’s Foveros integration technologies go in the side illuminated (BSI) image-sensor in December 2018 confirms this is next 10 years? How about leaping die, face-to-face stacked on a likely happening. from big silicon in data centers to logic die. The motivation to invest porting small silicon for on-the-fly Let’s see what 2019 brings to us! in stacked chip BSI CIS develop- decisions at the edge? ment has been varied depending

28 The First Decade We already know about high-band- capabilities, and routinely build width memory (HBM) integrated probe cards with probes as small with graphics processor units as 20µm, ~1/5 of a human-hair di- (GPUs) for high-performance com- ameter. Our MEMS probe engineers puting applications, and in autono- humorously said, “our job is to split mous vehicles, but if the direction a hair daily!” IBM is heading pans out, analog artificial intelligence (AI) chips using While the technical solutions for 3D 8-bit precision in-memory mul- and heterogeneous integration have tiplication with projected phase- been demonstrated, the commer- change memory may be supplant- cial bottleneck remains. Today, the ing trillion transistor GPUs in going adoption of 3D integration is still from “narrow AI” (puppy or muffin?) limited to a few performance-hun- to “broader AI” (reading medical gry applications such as data cen- images, for example). ter and artificial intelligence (AI), not plishments and milestones. A few widely used for consumer-driven Since “existing hardware can’t noteworthy events include the first mobile applications. efficiently handle the largest neural commercialization of 2.5D FPGA networks that researchers have integration by Xilinx and TSMC In the next 10 years, we need to built,” we’re probably going to be in 2011, mass production of high drive a higher level of back-end heterogeneously packaging more bandwidth memory (HBM) in 3D manufacturing automation to re- devices, together with memory, stacks by AMD and Hynix in 2015, duce the total cost of the 3D stack. running those 8-bit precision cal- and the latest Intel announce- For example, many improvement culations, and deploying heteroge- ment of Foveros 3D chip stacking opportunities exist in the areas of neously integrated SiP everywhere technologies in 2018. One common singulated die handling, testing, we need ubiquitous intelligence in driver behind these innovations is transporting, as well as process the world. to leverage advanced packaging control software and data analytics, technologies to supplement the to advance the yield of the singulat- slowing of Moore’s law for transistor ed thin-die and the ultimate stack. scaling. 3D Integration’s Thousand My crystal ball sees a fully-auto- Mile Journey From a probing technology per- mated and high-throughput die spective, the adoption of advanced assembly and test floor at OSATs By Amy Leong, FormFactor packaging (copper (Cu) pillar, TSV, and foundries in the next 10 years, etc.) has driven rapid pitch reduc- gradually moving away from wa- tion and a corresponding density fer-based processing as the adop- increase for probe cards. Over the tion of heterogeneous integrations last 10 years, the minimum grid-ar- increases. ray probe pitch has reduced from 150µm to 40µm, while the total probes per card has increased from ~10K probes to over 100K probes. 3D Enables More than Moore These trends have breached some By Paul Lindner, Executive interesting thresholds: Technology Director, EV Group • The diameter of a probe becomes smaller than a human hair ~100µm, it is at or beyond the positioning accuracy of When we look back at the last most human hands. 10 years, it’s really been a series of baby steps to move the com- • The manual probe assembly mercialization of 3D integration (~1 min. per probe) will result technologies forward. There is no in longer probe card assembly single pivotal event that catalyzed time than wafer fab cycle-time the 3D evolution. Like the Chinese of ~45 days (65k mins). philosopher Lao Tzu said, “do the difficult things while they are easy In 2013, FormFactor was the and do the great things while they industry’s first test provider to are small. A journey of a thousand bring the automated vertical MEMS miles begins with a single step.” probe assembly capability to build fine-pitch, multi-site probe cards Our challenging journey of 3D (MF100_Probes_RTsm.jpg). Today, integration has been marked we continue investing significantly Looking back at the last 10 years, it by many incremental accom in MEMS probe and automation is very difficult to choose one single

3D InCites Magazine 29 event that was the most pivotal Processing BSI CIS also triggered the scaling race to come back and for commercializing 3D integration the adoption of fusion bonding in enable high-performance devices technology. There have been many high-volume manufacturing, as well on larger nodes at lower cost. The prior events that have driven 3D as enabled hybrid bonding, which next 10 years will change the way integration and aligned the whole will both be fundamental building we design and build systems, using industry in migrating from mono- blocks for future 3D system on 3D in significantly more applications lithic 2D to heterogeneous and 3D chip (3D SoC) as well as 3D IC with than was the case during the past integration. sequential processing, including 10 years. layer transfer or backside power From my perspective, the most distribution. path-breaking event was the rise of the backside illuminated CMOS im- I think we are just beginning to ex- A Shift in Value from Single to age sensor (BSI CIS) into consumer perience the acceleration of 3D and Multi-die ICs devices about 10 years ago. To our heterogeneous integration in a lot of knowledge, this was the first 3D different applications and markets. By Herb Reiter, eda2asic integrated high-volume device. Where individual devices have been adapted to 3D integration with a But why has BSI CIS been so suc- lot of effort and engineering power cessful on the market, while other in the past, 3D is imperative in the devices have also demonstrated next 10 years. With both “More performance improvements utilizing than Moore” and “More Moore” 3D integration? In my opinion, BSI having a clear roadmap toward 3D CIS represents the first time that integration, design kits and design the sweet spot of performance, tools are under development right cost and form-factor were met in now and will be rolled out shortly. 3D integration. Without 3D inte- Flexibility will be key for a fast- gration, pixel scaling as low as paced industry with shorter and 1µm today, with superior sensitivity shorter consumer product lifecy- and speed, would not have been cles. Furthermore, 3D will enable feasible. players that have dropped out of

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Distributed and supported in North America by The single most pivotal event to tions, integrated in multi-die recognized this opportunity and impact the commercialization of ICs, to reliably control power already introduced DRAM “memory 3D technologies was TSMC’s electronics, increase systems’ cubes.” Combining multiple die in introduction and volume manu- efficiency, safety, and security. one high-pin-count package or die facturing of its integrated fan-out stack, they offer very large memory (InFO) packaging technology. This While user-friendly operating sys- capacity. event demonstrated that multi-die tems and application-specific soft- integration can be cost-effective for ware will of course continue to gain By mounting such a memory cube high-volume applications. importance in the semiconductor on an interposer, side-by-side with and electronic systems world, the a logic die ,or making them part of Since its deployment in 2015, every interface to the real world – which a 3D IC vertical stack, effectively new generation of iPhones has in analog, highly complex, and elliminates the “memory wall”. used this technology and the sever- continuously changing – demands al hundred billion iPhones shipped cost-effective and reliable hard- have proven it to be reliable. ware, a.k.a. multi-die ICs.

Eliminating the Memory Wall

By Jan Vardaman, Techsearch International, Inc.

Photo Credit: SK Hynix Based on many years of contribut- High bandwidth memory (HBM) is ing to the roll-out of ASIC tech- one of the most important 3D IC nology and process design kits developments in the last 10 years. (PDKS), as well as reference flows Over the last decade, stacked for enabling the transition to the fa- DRAM with TSVs has transi- bless and foundry business model, tioned from a handful of research I expect that the value-shift from programs to rapidly increasing single-die ICs to multi-die advanced volumes. IC packaging technologies will continue and bear fruits in these major Tezzaron has provided small application areas: quantities of 3D ICs for high-speed The adoption of 3D ICs allowed memory applications since 2005. Smart IoT edge nodes will need • for the elimination of the “Memory Micron, Samsung, and SK Hynix many more cost-effective multi- Wall” using a new memory archi- began producing DRAM stacks die ICs to process data locally tecture and through silicon via with TSVs in late 2014 and early and provide fast and intelligent (TSV) technology. 2015.Micron began shipments of responses to changing envi- its Hybrid Memory Cube (HMC) ronmental parameters, system While individual ICs became faster in 2015. DRAMs and the logic wear-out and/or operation with each process node, the com- controller were interconnected with changes required. munication between the chips was TSVs. HMC was packaged in a ball- constrained by limited pin counts, Data and compute centers grid array (BGA) and tested before • power-hungry I/Os, and PCB-space assembly on the board. will continue and significantly limitations. Assembly of multiple die expand how they leverage the into onepackage enables extremely The HMC is used in Intel’s Knights enormous performance-per wide busses between them, short- Landing. The silicon-on-insulator Watt advantages of multi-die ens latency, and expands band- (SOI) logic layer was fabricated by ICs to cut their response times, width between logic and memory, GLOBALFOUNDRIES (which pur- operating cost, and space while cutting the power dissipation chased IBM’s fab) and the memory requirement. by up to two orders of magnitude. was fabricated by Micron. `A wide range of transportation • The large memory vendors Micron Micron used a thermo-compres- and industrial equipment will (including Elpida), SK Hynix, and sion bond (TCB) process with a utilize sensors, actuator, data Samsung, as well as the spe- non-conductive film (NCF) underfill converters, and digital func- cialty memory house Tezzaron, for its die stacking in the HMC.

3D InCites Magazine 31 practitioners. The Toshiba CMOS References image sensor announcement, From 3D Pioneers to 3D Robots with its backside TSV to signifi- [1] http://electroiq.com/insights-from-leading-edge/2016/02/iftle-272-2015-3d-asip- cantly downsize the size of image part-1-pioneer-awards-sony-3d-stacked-cis- By Dr. Phil Garrou, IFTLE, sensors, brought this technology latest-on-spil-acquisition/ Microelectronics Consultants mainstream and caused the tidal of North America wave of research and product in- [2] https://www.electronicsweekly.com/ news/products/sensors-products/toshi- troductions that were to follow. For ba-image-sensor-camera-modules-2007-10/ those who don’t remember these early days, this was the work of [3] Takahashi, K. , “Through Silicon Via and Kenji Takahashi.3 3-D Wafer/Chip Stacking Technology”. 2006 Symposium on VLSI Circuits, 2006, p. 89. Where will 3D and heterogeneous integration technologies take us [4] http://electroiq.com/insights-from-leading-edge/2017/01/iftle-319-mike-ma-to- in the next 10 years? In reality, amkor-3d-asip-part-2-image-sensing-sony- most can only predict the future in tessera-smic/ hindsight (and you can quote me on that). If you don’t believe me check the market prognosticators projec- tions for 3DIC adoption in the 2008- Thank 2.5D Interposers for the 2012 timeframe. Some actually Success of 3D ICs predicted that the first applications would be flash memory! By Mark Scannell, CEA-Leti

It is clear to most of us who have Right now, 2.5D/3D IC technology been following the 3DIC area for the is still too expensive for adoption in past decade plus, that the origins of standard consumer applications. this technology come from the early Qualcomm and many others spent (1980s-1990s) work of Mitsumasa a lot of time and money trying to Koyanagi in Japan and Peter Ramm lower the price point, but in the end in Europe.1 If you’re asking what the were not able to. It has certainly defining event was that propelled it found a niche in stacked memory, from obscurity to becoming a buzz- FPGA modules and graphics mod- word of the 2000’s, I’d have to say ules, but those are high-end costly it was the Toshiba announcement in applications. Current predictions Oct of 2007 of the production of the appear to favor future adoption in “chip scale camera module”, which high performance computing (HPC) and artificial intelligence (AI), which would revolutionize image sensor Would it be flippant to say that 2 seem to be logical applications, but production as we knew it. most pivotal event that impact- we will see. ed the commercialization of 3D I certainly have been impressed by integration technologies, may have Sony who has burst to the head of been the commercialization of 2.5D the class in terms of image sensors, technologies? Arguably, 3D and which now contain thinning, stack- silicon interposer are very different ing and TSV. Sony management technologies, with a common de- has indicated that they will require nominator that happens to be the this technology to advance their through silicon via (TSV). robotics platform.4 So… if I had to Until Xilinx announced its Virtix-7 place a bet on my answer at this 2000T in or around 2011, skepti- point, I would have to say robotics. cism was the other common de- nominator. 3D memory cubes were The scientific community had certainly in the ether at the time, agreed that true 3D IC would but there was still much debate require (3) things: (1) chip thinning; about the cost and commercial (2) chip stacking and (3) connection viability of TSV technologies. through the silicon with the through Tasked as I was then with promot- silicon via (TSV). While thinning and ing 3D integration technologies, stacking technology was already in I was struggling to sell the larger production and only needed minor picture of overall system perfor- advancements to be used in 3D mance benefit versus, say, the ICs, TSV was an obscure tech- direct single-step cost adders such nology only used by some MEMS as metalizing a via or temporary

32 The First Decade handling of thin wafers or other whatever, I think it’s fair to expect such ‘inconvenient’ processes. there will always be a demand for improved performance (specifically Ironically, yield was an often-used memory bandwidth) with reduced argument to rationalize that the energy consumption and reduced cost of 3D would always be pro- cost. Traditionally, in terms of hibitive. The notion of known good timing, the improved performance die (KGD) was considered difficult leads and the reduced cost follows. to measure, and how to accom- I say that because it conveniently modate yield multiplications related allows me to ignore cost for what Photo credit: DARPA to stacking, remained a sticky I’m about to forecast (experience Of course, D2W hybrid bonding will question. tells me all I have to do is hang require some further development around until a future Xilinx-equiva- and collaboration before being Then suddenly, along comes lent comes up with that solution!?). Xilinx with their silicon interposer, sufficiently mature for industrial of which the TSV cost adder was Quantum computing is certainly a scale chiplet integration. Whatever paid for by none other than yield hot topic but let’s put it aside for performance the chiplet programs enhancement. Rather than building the moment. As a rather preten- are achieving today, or planning to a single, very low-yielding large tious professor once said to me; achieve, one could assume that 28nm chip, Xilinx ‘simply’ (I use “there are two kinds of people – the performance would be further the word loosely) built smaller and those who understand quantum increased with hybrid bonding. The thus better yielding 28nm chips and mechanics, and those who don’t”. Foveros technology seems to be assembled them on an interposer. relying on face-to-face, 36µm pitch The system performance benefit I must admit, I’m attracted to µ-bump interconnects. However, ended up being financed by the die-to-wafer hybrid (D2W) (a.k.a. with hybrid bonding this pitch can very same yield that was supposed direct) bonding. The wafer-to-wafer be reduced to 5µm. to be the problem. I say Xilinx, but version (W2W) works very well. It’s of course, TSMC deserve their my understanding that W2W hybrid Many issues remain, not limited to share of the credit too. bonding is more or less restricted dicing a perfect wafer surface (i.e. to imager applications most likely hybrid bonding requirement per- due to the requirement that both fect!) in a way that the die surface is dice must have the same size. D2W as perfect after dicing as it was be- however removes the equal die-size fore. Then picking and placing that requirement, which in theory could perfect die surface on an equally bring the performance benefits of perfect wafer surface with, by the hybrid bonding to almost any 3D way, very high alignment accuracy system. And the performance ben- and high throughput. If Intel can live efits of hybrid bonding are not to be with the alignment accuracy versus For me this was a pivotal moment ignored: decreased interconnect throughput compromise of 36µm because suddenly the hypothesis pitch, shorter interconnects, faster pitch interconnects, maybe we’re that TSV technology would always communication, reduced loss, etc. not actually that far from a 5µm be too costly to commercialize was accuracy/throughput compromise? clearly disproven. I must admit, I All of this sounds familiar because never anticipated that yield im- it’s basically the justification for any We know that D2W is possible in provement would be the elusive interconnect improvement ever principle, and D2W electrical results initial justification for TSV integration proposed, including TSV’s back in have been demonstrated to be as costs – I was looking far and wide, 2011 – so it cannot be completely good as W2W results. In any case, and elsewhere. irrational to at least consider this there is no fundamental reason approach (right?). D2W bonding that the electrical results should be So now, after publicly admitting could also enable, for the want of a different. that I never saw that one coming … better description, ‘partitioned-sys- I’m expected to look into the same We will need to develop a ‘clean’ tems’ like the current interposer crystal ball and have you believe dicing process along with some systems but with chiplets instead of that I can see what’s coming next? sort of auto-alignment system to chips, and active silicon interposers fix throughput. Who knows, maybe instead of passive ones. Well, for what it’s worth … the hybrid bonding with collective Indeed, Intel has just announced auto-alignment will end up being The (very reliable?) crystal ball its Foveros 3D integration scheme, lower cost than, say, µ bumps + underfill or thermal-compression Data generation, collection, analy- which seeks to achieve competi- alternatives? sis, storage and management (and tive advantage by partitioning logic chips and stacking the resulting dare I say abuse?) will continue to There you have it, my clear-as-mud chiplets on top of each other. My increase. Whether it’s due to the crystal ball forecasts the introduc- organization, CEA, and others, famous Internet of (every and any?) tion of D2W hybrid bonding at an such as DARPA, are also working things (IoT), autonomous driving, industrial level, within 10 years …or on such initiatives. high performance computing or thereabouts.

3D InCites Magazine 33 a named device, they can provide oped that eliminate many of the a pad layout design and desired emerging failure modes seen with Heterogeneous Integration functionality and device dimension the thin copper traces on the redis- Calls for Increased Materials to their suppliers and ask for that in tribution layer. Reliability 18 months. The use of wide I/O memory By Dr. Andy C. Mackie, PhD, Secondly, there is no longer a stacks on 2.5D substrates for Indium Corporation need to rely on specialty system- advanced processor applica- on-chips (SoCs) so you don’t have tions needs strong, reliable solder the headache of building mixed joints. Although the memory dies technologies (like Si and III/V) in the themselves are being increasing- same tool. At SMC 2018, Micron’s ly stacked using non-conductive John Smythe put this as “running film by Southeast Asia memory peanut butter in a chocolate fab.” manufacturers, a very low-residue no-clean flip-chip flux is now exten- Finally, if dies are built separately sively being used for memory stack then packaged together, well-char- attach onto the 2.5D interposer. acterized fabrication processes will lead to high-yield for individual die; and known-good-die are then used in the final assembly. Extending Moore’s Law through Advanced Packaging When it comes to wafer-level pack- Automotive reliability is a pivotal aging (WLP) and panel-level pack- By Carl McMahon, Genmark concern for heterogeneous inte- aging (PLP), there are still many Automation gration technologies, especially as issues in fan-out PLP co-planarity emerging mission profiles for elec- for larger packages. The need tric and autonomous vehicles push for technologies such as Deca component lifetimes out by two to Technologies Adaptive Patterning™ three times or more over standard pad registration software is a tacit testing regimes. There has been acknowledgment that polymer cure increasing realization of the impor- in these advanced packages needs tance of chip-package interaction much more attention than is pres- (CPI) as a source of reliability issues ently being given. in semiconductor assembly. Pin- ning it down to a single date as the We can expect to see near-term key event, the release of JEDEC JE- developments in modeling of P156A in March 2018, was a good the polymer curing process, and start in this direction, as it shows a specialty heating systems being major deviation from the old but still developed as a result, especially for useful Arrhenius/activation energy the huge panels (>50x50cm) being TALK NERDY discussed in various consortia. kinetics models. Be part of the 3D Exacerbating the problem is the Higher frequency RF devices will be The performance and productivity fact that coreless and thin sub- especially sensitive to any devi- of microelectronics have increased strates, thin (2.5D) interposers, ation from the original I/O layout. InCites Community continuously over the last 50 years and large thinned die have be- For ball-attach on these packages, due to the enormous advances in come prevalent in the advanced specialty fluxes have been devel- TO US lithography and device technology. processor market; there is no Today, these technologies are be- single “solid/inflexible” part of the coming prevalent in 3D packaging, package against which everything which further enables advances else moves. Therefore, the thermal Learn more: in integrating various technologies CONTRIBUTE and mechanical stresses present (logic, memory, RF, sensors, etc.) in are mutually interdependent and www.3DInCites.com a small form factor. advanced stress modeling and ENGAGE increased understanding of CPI There are concerns with the failure mechanisms will be needed. sustainability of shrinking devices beyond 5nm and the costs associ- ADVERTISE Heterogeneous integration is here ated with it. Advanced packaging to stay for a few reasons. First, it al- compliments current technologies, lows a more modularized approach which in turn allows ‘Moore’s law’ to system design. Rather than to extend for several generations. original equipment manufacturers (OEMs) having to ask subcontrac- From Genmark’s perspective, guid- tors for a specific component or

34 The First Decade ed by over 30 years of experience, driven by the need to lower costs 10 years, the recent acquisition by the migration to Si or Si-type sub- and improve performance for WLP Nidec-Sankyo gives us the ability strates for 3D packaging allowed companies. to provide our technologies across much of current semiconductor a broader range of companies. technology to be adapted for their Cleanliness requirements in ad- Nidec-Sankyo has a global reach processes. This is particularly true vanced packaging is now similar and technology platforms that for automation, where mainstream to any of the leading-edge IDM Genmark can leverage to constant- automation designed for integrated companies. However, in the area of ly innovate new solutions within the device manufacturers (IDMs) can be substrate handling lies some of the 3D packaging space. modified for substrates used in 3D most difficult challenges because wafer-level packaging (WLP). the exclusion zone for substrate We see requirements for ‘smarter’ handling is greatly reduced. This, handling solutions, building 3D Data from Genmark show that 10 in turn, has led to the rise of ‘no- software models of applications years ago, we sold to companies touch’ end effectors, based on before releasing to the customer. who were working on develop- Bernoulli principles. Genmark is Developing the applications ‘virtual- ing more efficient, cost-effective, one of the very few companies that ly’ can speed up product launch to high-volume 3D packaging tech- can run a 100% ‘no-touch’ handling an industry that has no established nologies. Since then, we have been process on to panels up to 450mm. single substrate size. Coupled with involved with these and many other The focus for us now is to work this are both thickness and material companies at the forefront of pack- with our customers on improv- type challenges which requires aging. Companies and research ing throughput and performance novel handling regimes. Nidec-San- institutes worldwide have demon- of these technologies, ultimately kyo’s teams and Genmark’s strated 3D integration processes. enabling the production of more together have already created new Genmark’s development of the cost-effective products. handling technologies which will CODEX stocker to serve the glass benefit all of our advanced packag- wafer segment of the market was Looking forward to Genmark’s next ing customers.

TALK NERDY Be part of the 3D TO US InCites Community

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3D InCites Magazine 35 10 Years of Invent, Innovate, Implement at EV Group By Françoise von Trapp

Left to right, Clemens Schütte, Werner Thallner, Françoise von Trapp, Herman Waltl, Paul Lindner, and Thomas Uhrmann.

Of all the companies that have sup- solutions are as old as the market, invited to tour the ongoing expan- ported 3D InCites over the past 10 back when they were referred to sion at corporate headquarters in years, none has been more consis- as tape mounting systems, notes Schärding, Austria four times. The tently involved, both as contributor Paul Lindner, executive technology first time was in 2010; the year of and sponsor, as EV Group. In fact, director at EV Group. the company’s 30th anniversary. without EVG’s belief in our mission I returned in February of 2012, and their sponsorship the first three “We are a technology provider,” January 2014, and most recently in years, 3D InCites would not exist he said, “The equipment industry November 2018. today. Therefore, it seemed fitting has to be. There are no high-per- to honor them with the cover story formance chips without the right Since 2009, the manufacturing area for this 10th anniversary edition. tools.” Additionally, he said, it takes grew from about 3,100 to 7,100m2, a combination of processes, ma- the machining center from approx- Since the beginning of 3D integra- terials, and equipment to achieve imately 1,900 to 3,600m2, and the tion, EVG has been there. They success. The burden of optimizing cleanroom area from approximately were the first to invest in R&D for those processes falls to the tools. 1,200 to 2,800m2, says Clemens image sensors. They implemented “Equipment has to continually im- Schütte, director of marketing and the first fusion bond and the first prove and optimize,” said Lindner. communications. layer transfer for sequential 3D stacking. Visits to EVG Headquarters In the same period of time, the number of employees worldwide The inventors of temporary bond/ In the past 10 years, EVG has increased from 430 (Sep 30, 2009) debond (TB/DB) processes, their grown exponentially. I have been to more than 860 today.

36 The First Decade EVG Minis kindergarten / childcare Manufacturing II facility and for final assembly Cleanroom IV INNside restaurant

EVG Expansion Timeline:

2011 2012 2013

2013 2016 2017 2018/19

New office building Machining New test New Manufacturing and reception area Center II room building III building

3D InCites Magazine 37 ment accuracy has been improved from 500nm to 50nm; That's 10X in 10 years.

“That’s better than Moore’s Law,” noted Thallner. “While speed and accuracy are both important for 3D and we are working on both, alignment is more critical. Verification of alignment directly after bonding is critical for high yield too. We are the only company that offers alignment verification integrated in the fusion bonder.”

Two robots keep the wafers moving. The floor in the test room is raised so that connections can be made under the floor.

The latest construction, dubbed Manufacturing Building III, will connect manufacturing with final Werner Thallner shows me around the construction site for EVG’s latest expansion, called assembly and test so that there Manufacturing III. is no need for customers to walk outdoors. In addition to expanded Triple I Today – November 2018 to machine parts that larger tools manufacturing and warehouse require for handling a variety of space, there will be a designated My most recent visit to EVG substrate sizes, such as for panel packaging area designed specif- included a construction site tour level packaging for fan-out wa- ically for cleanroom equipment. and lunch with members of EVG’s fer level packaging, or flat panel Shipping and receiving will be cen- leadership team including Werner displays. tralized in a restricted area, as the Thallner, Paul Lindner, Hermann company is authorized to inspect Waltl, and Thomas Uhrmann, as On this particular day in the class-1 tools for shipping. well as Clemens Schütte and Klaus clean test room, a next-generation Doblmann from the marcom team. fusion bonding system (Gemini FB In Growth Mode XT) configured for hybrid bonding In the four years since I last visited of image sensors and stacked flash These days, the company is fully EV Group, a new machine shop memory was being put through its immersed in all aspects of hetero- and test room building were added. paces. This tool features cleaning geneous integration. Its tools and The new machine shop was built and plasma activation modules processes support all the elements around the old one, doubling its used for preconditioning wafers of bonding and lithography. size to 3600m2. It features a new before bonding, and the latest More than Moore is on the rise, CNC milling machine large enough SmartView NT3 aligner, its align- says Lindner, and the company’s

Excerpt from “Triple I” at Work – September 8, 2010

EV Group sums up its philosophy and mission in three words: “Invent, Innovate, Implement”. Whatever market EVG enters into, the company’s goal is to be the first to explore new techniques and serve next-generation applications of micro and nano-fabrication technologies. The list of industry firsts supporting this is long and includes such notable achievements as developing the first backside lithography system for MEMS, the first wafer bonding systems that would set the industry standard, the first nano-imprint system, and the first automated SOI bonding system. As Hermann Waltl, executive sales and customer support director, pointed out, the “Triple I” philosophy isn’t merely a marketing tagline – at EVG it’s a way of life and the Markus Wimplinger shows Françoise von Trapp a company’s secret to success. 300mm bonded wafer on tape carrier.

38 The First Decade With such a banner year under their belt, the promise of steady Excerpt from Triple I future growth, and the desire to ramp up the company’s status to that of a Tier 1 supplier, it was time to pull out the plans to expand at Work, The Sequel: the facility. February 2012 According to Werner Thallner, executive operations and financial director, advanced planning to design the expansion and secure government approval and building permits allowed for rapid implementation of the project once they pulled the trigger. “Literally, about one hour after I made the decision to ramp up and build the building, the builders arrived and started building the building. Within 4 ½ months – on December 1, we moved in and began production.”

The newly constructed four story building with two-story manufacturing floor doubled the size of the current manufacturing space and meets the cleanliness requirements of a Tier 1 manufacturer (class 100K). Additionally, the building features an overhead train to make it easier for moving tools around, and hydraulic ramps to make it easier for technicians to work on the tools, thereby improving the working conditions.

Thallner also said that integrated test rooms were built that can go down to Class 1K. With the test rooms, the concept was to separate testing from manufacturing to address the security needs of customers to split up technologies of different customers to prevent them from seeing what each other is doing.

Paul Lindner shows Françoise von Manufacturing II for final assembly and The new manufacturing floor in action. Trapp a 450mm wafer used to test its cleanroom IV expansions. 400mm SOI wafer bonding platform.

Triple-I approach – Invent, Innovate, It’s important to start as early as Implement – is paying off as all the possible and scale the process. markets they touch are in growth You can’t make a ‘side entry’ into Submicron Accuracy Bonding mode, from advanced fan-out a market when it ramps to high wafer level packaging (FOWLP), volume and expect to succeed.” EV Group is perhaps best known interposer and 3D integration, to for its advancements in permanent compound semiconductors and For example, the company has wafer bonding tools, where it is a MEMS, photonics, biotech, and flat more than 20 years invested in TB/ market leader. panel displays. DB R&D and has been through all the technology changes, from Uhrmann says new application “It’s been a long journey from the thermoplast and mechanical drivers like artificial intelligence first lithography line for 3D pack- debonding, to zone bond invented and machine learning require high aging to industry adoption; a lot together with Brewer Science. The levels of computing at the edge and longer than we expected,” noted different TB/DB methods suit differ- cloud. This calls for high-density Lindner. “And the nano-imprint li- ent applications, and EVG supports interconnects that are bonded at thography business took more than them all. pitches of 2µm or smaller. As a 15 years from invent to implement. result, interest is growing for fusion

The latest CNC machining tool is twice the size of the other machining tools in EVG’s machine shop.

3D InCites Magazine 39 cleanroom space, a training center The idea, explained Lindner, is to Excerpt from for internal and customer training, produce process results equivalent an R&D center specifically for new to customer operations, and is The EVG Story tool design and developments, an driven so that they can create more on-site restaurant for employees automated systems that accurately Continues… and an on-site kindergarten. determine known throughput and cost of ownership (CoO). EV Group February 2014 Additionally, they upgraded the old- has also grown its international er cleanrooms to a newer standard footprint, with EVG China and EVG Paul Lindner, EV Group’s executive and class-10 cleanliness to make Taiwan now fully established to technology director, filled me in on them state-of-the-art and closer to serve those regions with increased what’s new since my last visit in what customers are running with re- process support and technical 2012, such as the 21000m2 addition gards to temperature and humidity support for its install base. that includes new offices, double the control.

The new kindergarten and Innside restaurant.

and hybrid bonding processes. fusion bonding system, GEMI- mated fusion bonding system, is NI® FB XT, supports applications designed to support a broad range Understanding the growing requiring higher alignment accu- of fusion/molecular wafer bonding importance of alignment accura- racies, such as memory stacking, applications, including engineered cies for fine-pitch applications, its 3D systems on chip (SoC), back- substrate manufacturing and 3D latest-generation SmartView® face- side-illuminated CMOS image integration approaches that use to-face bond alignment system sensor (BSI-CIS) stacking, and die layer-transfer processing, such as features 50nm alignment. partitioning. monolithic 3D (M3D). With this tool, EVG brings wafer bonding to the Armed with the SmartView NT3 The company’s latest tool introduc- front end. system, EVG’s flagship automated tion, the BONDSCALE™ auto- In addition to wafer-to-wafer hybrid bonding, EVG is also working in collaboration with imec to develop wafer-to-wafer processes, to be able to increase throughput, in addition to achieving 50nm alignment accuracy.

The Road to 3D TSV Adoption

After lunch, Uhrmann and I sat down to reminisce about the past 10 years, and specifically the longer-than-predicted road to 3D TSV adoption. Beyond the well-known cost challenge, there were other technology issues that delayed progress.

One of the biggest challenges was regulating the keep-out zone around devices to reduce impact of TSV-induced stress. “Managing the stress in a 3D wafer is not a piece Paul Lindner explains the features of EVG systems. (L-R) Lindner, Clemens Schütte, Françoise von Trapp, Hermann Waltl. of cake,” noted Uhrmann. Bow and

40 The First Decade Chatting with Paul Lindner, Werner Thallner, and Hermann Waltl in the new manufacturing area.

Excerpt from Triple I Prevails at EV Group – February 2014

We took a group tour of the new class 100 cleanroom, where I was able to see some of the tools we’d discussed in action. For me, since I had first seen the first prototype of the EVG850TB/DB XT HVM temporary bond/debond system on the manufacturing floor when I visited in 2012, seeing the same tool in action in the cleanroom completed the story for me. The fact that it also won the 3D InCites Award for equipment made it that much more exciting.

Markus Wimplinger, corporate technology development and IP director, put the tool through its paces, demonstrating the high throughput operation with 9 process modules. The in-line metrology feature for inspecting adhesive thickness is probably one of the coolest features of this tool, because it can quickly measure up to 300,000 separate points on a wafer, which delivers more accurate results with more data to help in process optimization. “It’s critical to scan at very high resolution. You can fool yourself about total thickness variation (TTV),” explained Wimplinger. “Ours is the only one that can Checking out the EVG850TB/DB XT HVM temporary bond/debond measure 100% of the wafer at high resolution in less than 90 system in action. seconds.”

3D InCites Magazine 41 strain caused by how the wafers The semiconductor industry is phones, changed the entire indus- react to copper called for process notoriously slow to adopt new tech- try. And now artificial intelligence adaptions for the whole fab supply nologies. As long as 2D approach- that enables cloud and edge com- chain, from substrate changes to es worked, there was no reason puting are driving performance re- etching and deposition processes, to change, explained Uhrmann. It quirements even higher, while also to debonding methods. wasn’t until there was no other way driving down-power requirements. to achieve performance require- Did the development of FOWLP ments, that 3D TSV was adopted. “This is what is pushing advanced slow down progress for 3D TSVs? Uhrmann credits the smart phone packaging. We need flexibility that Uhrmann says no. To the contrary, — and particularly the iPhone 3S you can’t get with just chip design,” he says he thinks fan-out technolo- — for ramping BSI-CIS into volume says Uhrmann. “It’s not just about gies put advanced packaging – in- production. Next came memory logic anymore, it’s all about sys- cluding 2.5D and 3D TSVs – on the stacking, using TSVs in DRAM tems. Advanced packaging is how prime stage. It became clear that stacking to achieve high-bandwidth you smartly connect dies. 3D will heterogeneous integration through memory (HBM), but that took lon- be everywhere for More than Moore advanced packaging was the way ger to achieve. technologies.” When that happens, forward to achieve more functional- you can be sure EVG will be ready ity and performance. Small devices, such as smart for it.

Werner Thallner joked that the new building is connected to the old one using “through concrete vias”. “That’s bonding in action.”

42 The First Decade Advanced Heterogeneous Packaging Solutions for High Performance Computing

By Ron Huemoeller, Mike Kelly, Curtis Zwenger, Dave Hiner, and George Scott, Amkor Technology, Inc.

Heterogeneous integrated circuit has permitted a two-fold leapfrog in silicon interposers but really (IC) packaging has made a full in what was possible previously, ushered in the modern hetero- entrance into the high-perfor- specifically: a memory bandwidth geneous surge. The implications mance packaging arena. The target improvement thanks to high band- were profound, as the highest applications are broad, running the width memory (HBM) introduced bandwidth DRAM (HBM) available gamut from artificial intelligence by Samsung and Hynix, and the were designed exclusively for (AI), deep learning, data center ability to provide more off-package silicon interposer applications. This networking, super computers, and signaling capacity. new performance level was only autonomous driving. In fact, a new available in 2.5D TSV packages: generation of deep learning AI, leading central processing units HETEROGENEOUS (CPUs) for datacenter servers as well as new performance-leading PACKAGES HAVE CPUs for the latest blade servers OVERCOME have literally been made possible by these remarkable IC package THE EXISTING constructions. LIMITATIONS These cutting-edge technologies are leading the way for incredible OF MONOLITHIC Figure 2. Three key elements of advanced 2.5D packaging technology advancements. Moreover, they INTEGRATION AND all have a common characteristic: first in ultra-performance graphics, high-speed, high-performance ICs. SIGNIFICANTLY then deep-learning accelerators and now in datacenter network- Investment agency Goldman Sachs INCREASE THE ing switches and server CPUs. Group has predicted that global The main requirement for silicon AI hardware microchips including CAPABILITIES AND interposers is that the HBM device CPUs, graphics processing units uses an ultra-wide 1024-bit parallel (GPUs), application-specific inte- PERFORMANCE bus requiring signal routing traces grated circuits (ASICs), field-pro- OF TODAY’S of 2µm width or smaller. This is grammable gate arrays (FPGAs) 8-10 times the routing density of an and others, will grow at an annual ELECTRONIC FCBGA substrate. compound rate of more than 40% in the coming years (Figure 1). PRODUCTS. Amkor’s TSV reveal process and chip-on-wafer (CoW) packages Heterogeneous Packaging have been in high-volume manu- Approaches facturing (HVM) for three years. The assembly processes are high-yield- FCBGA MCM ing flagships of the new ultra-clean K5 facility in Song-Do, South Ko- Heterogeneous digital integration rea, near the Incheon International using flip chip BGA (FCBGA) pack- Airport. Figure 2 shows the key ages has been occurring for years elements of a typical implementa- and the variety of approaches has tion of this packaging technology. been nearly endless. The intra-die Figure 1. Worldwide AI computing hardware total available market (TAM). Source: Gold- routing capability for multichip HBM: Just the Beginning man Sachs 2018 modules (MCMs) is good, and as long as the layer count to achieve Processors used in conjunction In deep learning, continuous this can be accommodated, it will with HBM in 2.5D TSV packaging advancements in algorithms and continue to be a viable approach constructions came first, but this big data accessibility combined for many devices. is viewed as just the beginning. with high-performance compute Today, the expense of 7nm and engines based on heterogeneous TSV upcoming 5nm design will sharpen IC packaging are driving the giant the focus for the content placed leap forward for this technology Through silicon via (TSV) develop- into the system-on-chip (SoC), wave. The package construction ment took several years to perfect ASIC or the processor. Leading

3D InCites Magazine 43 Figure 3: A high-density fan-out solution

advancements beyond single HDFO Packaging for optimization, and rule-checking SoC approaches are in-package need to advance. Addressing these combinations of the processor and HDFO packaging is being devel- challenges, Amkor has already multiple discrete I/O die and even oped as another crucial pillar for developed outsourced semicon- multiple processor chips in an effort heterogeneous integrations to ductor assembly and test (OSAT), to increase the core count and lower the cost of high-performance industry-leading process assembly discrete I/O die. Several current heterogeneous applications. This design kits (PADKs), and a design examples of these have been proto- fine-line redistribution layer (RDL) flow to achieve electronic design typed and announced. approach is capable of 2µm line/ automation (EDA) connectivity with space and 4-layer counts to provide Cadence and Mentor Graphics. One of the key intersections be- the inter-die routing. In this case, tween new levels of device per- the copper/organic dielectric RDL The kits are introduced during formance and heterogeneous IC layers are fabricated on a glass or the design stage and achieve a package structures is the intra-die silicon carrier and then the wafer is synchronous debugging design signal routing capability. The 2.5D populated with functional die and environment to carry out com- interposer offers a copper back- molded in a manner very similar to parisons between schematic and end dual-damascene technology 2.5D designs (Figure 3). layout diagrams and to perform all with excellent fine-line capability design rule checks (DRCs). This and reasonable electrical signaling For the 2.5D package design plan, process achieves rigorous design performance for short runs. Today, the design flow and design meth- verification and sign off. In addition, 2.5D TSV is the proven path for odology are very different from by extracting the design, interposer HBM integration into your product traditional package designs. For and substrate models, and imple- designs. example, an HBM2 DRAM having menting co-design and co-sim- 4,000 bumps, and a main chip ulation, design-for-performance Another up and coming technolo- maybe having tens of thousands (DFP), design-for-cost (DFC) and gy uses the so-called “dies-last,” of bumps and multiple chips, are design-for-manufacturing (DFM), high-density fan-out (HDFO) connected through an interposer. are also achieved. Figure 4 shows approach. To do this, the design, simulation one example of a simulated eye-di- agram, with the HBM data bus operating at 2 GHz frequency.

Summary

Heterogeneous packages have overcome the existing limitations of monolithic integration and significantly increased the capabilities and performance of today’s electronic products. As silicon integration faces additional and even more difficult challenges, the next step towards heterogeneous packaging will fulfill an even greater role to take end products to ever higher levels. The packaging solutions are available today to make the next generation products a reality.

44 The First Decade CoolCube™: Much more than a True 3DVLSI Alternative to Scaling

By Jean-Eric Michalette, For systems requiring high perfor- 3D sequential integration. Either CEA-Leti mance, advanced 3D technolo- from a manufacturability, reliability, gies such as hybrid bonding and performance, or cost point of view, Almost four years ago, we pub- monolithic 3D are considered to be on a 300mm FDSOI advanced plat- lished an article titled “CoolCube™: the only ways to push computing to form, experimental data from Leti A True 3DVLSI Alternative to higher levels, given desired targets has now demonstrated the ability Scaling” on 3D InCites. It described for memory capacity, memo- to obtain: the concept of stacking layers of ry bandwidth, power efficiency, transistors sequentially on top of reliability, and cost. For systems re- • Low-resistance poly-Si gate for each other and documented the quiring heterogeneous applications, the top field effect transistors research effort happening at Leti to those technologies provide multiple (FETs) develop a feasible process inte- opportunities to enable efficient gration scheme and a comprehen- edge computing of sensor data. • Full low-temperature raised sive product design frame. Now, source and drain (LT RSD) four years later, we can say that Towards 500°C device, epitaxy including surface pioneering this concept has put Leti and below preparation in a very good position to lead the next few decades of innovation in 3D sequential integration aims to • Stability of intermediate back- microelectronics. provide a concept for stacking end-of-line (BEOL) between devices with a nanometer scale tiers with standard ultra-low-k In reality, the limits of 2D scaling resolution, allowing low aspect ratio (ULK) copper (Cu) technology described three years ago remain, and small 3D‐contact fine‐grain and are even more present than interconnects. It requires limiting • Stable bonding above ULK before, calling for a new approach the thermal budget of the top tier • Efficient contamination contain- that includes 3D capabilities. Fewer processing to a low temperature ment for wafers with Cu/ULK than four fab companies are pro- (less than 500°C) to ensure the intermediate BEOL, enabling ducing 2D technology below 10nm. stability of the bottom devices. their re-introduction into the Cost-of-ownership for those nodes front-end-of-line (FEOL) for top are skyrocketing to such levels Leti’s 3D sequential integration FET processing where only a few ICs can assure a concept is called CoolCube™. After more than ten years of research, return on investment. Even if several • SmartCut™ process above a Leti is now able to present break- applications require such advanced CMOS wafer technologies, most companies are through proof points in several now looking to enable innovative areas that were previously consid- Leti’s work has focused on func- 3D stacking flows (Figure 1). ered as potential showstoppers for tionality demonstrations of the

Figure 1: Two 3D VLSE complementary approaches by CEA – Leti

3D InCites Magazine 45 CoolCube concept. However, Cost Figures complexity factors, doubling ex- some performance measurements pensive process modules, doubling already enable validation of the Beside process integration re- lead-time, etc. concept for certain electrical device search, Leti has also studied the specifications: cost figures of 3D sequential inte- To establish parameters, Leti gration. If such integration is widely developed a unique analytical cost • At 500°C, compared to a seen as a technological push, the model to benchmark any technolo- high-temperature process economic benefit is not evident. gy node or 3D integration scheme scheme, no degradation of compared to 2D. Based on die bottom MOSFETs has been Most initial reactions towards this area, yield and mask count, this measured. concept is to anticipate a clear model considers benefits of the drawback for digital applications: concept including time-to-market, • On 2D readout and on 3D full stacking, we demonstrated the capability to form the junctions at low temperature without any performance degradation (Ion, Vt) for the top layer N or P devices. Slight degraded values are not due to mobility but to access resistance, something greatly improved by replacing the nitride spacer. • For bottom level transistors, we observed no change in terms of reliability. Top level transistors meet lifetime requirements at 5 and 10 years, additional gate stack solutions investigated on Figure 2a: Stacked planar device processing and TEM analysis. short-loop lots are promising to improve the reliability level to be measured on the full-3D CoolCube (Figure 2).

Leti generated a portfolio of almost 50 patents around the CoolCube concept, the first one issued in 2008. However, Leti is no longer the only technology research organization working on 3D sequential integration. NARLAB, located in Taiwan; and imec, in Belgium, are also presenting papers on this subject at major conferences, increas-

ing momentum of the concept for Figure 2b: 3D sequential integration: the ultimate vertical density the future of microelectronics.

Figure 3: The model shows for digital products based on homogeneous stacking of N/N nodes that 3D sequential integration provides significant cost savings

46 The First Decade The Largest Advanced System-in-Package

Event in the World SiP 2019 is a continuation of IMAPS SiP Conference which ﬁ rst started in June 2017 as the ﬁ rst System-in-Package (SiP) conference fully dedicated to covering all aspects related to SiPs - market trends, system integration/miniaturization, and new technology innovation enablers to meet current and future SiP challenges. June 25-27, 2019 Monterey Marriott 350 Calle Principal Monterey, California USA www.advancedsip.org

For more information about IMAPS and other 2019 events, visit www.imaps.org.

52nd International Symposium on Microelectronics

September 30 - October 3, 2019 Boston, Massachusetts

• Returning to favored Boston for the ﬁ rst time in over a decade, with local activities and networking events More information available at • Over 125 papers across 5 tracks, plus the ever-popular www.imaps2019.org interactive poster session The 52nd International Symposium on • 16 Professional Development Courses Microelectronics is organized by the • Two days of exhibits featuring the newest and best International3D Microelectronics InCites Magazine Assembly 47 technologies in the microelectronics supply chain and Packaging Society (IMAPS). volume ramp-up, or new functions to another, slight variations of the CoolCube devices and MIVs are integration. results are obtained but the trend is inserted between the M4 and M5 the same. Reusing validated IP on metal levels in a standard 10ML A main outcome of the study re- older than 28nm nodes is compat- 28nm FD-SOI process from ST- veals that smart tiers/blocks/func- ible with advanced node 3D inte- Microelectronics. A unified design tional partitioning will be key to fully gration and shows both cost saving environment based on an incre- benefit from 3D sequential integra- and dies supply improvement. mental technology data base (ITDB) tion without any design evolution or framework is available to design circuit architecture changes. We also recognize that 3D se- test chips in a routine multi-project quential technology is suitable for wafer (MPW) at ST Microelectron- Re-using 2D standard IP blocks applications that require heteroge- ics’ advanced fab. Both the active and depending on the applications, neous functions. Smart partitioning layers and the whole metal stack there is a need to structure top and between the two devices layers are managed using similar tools bottom tiers following the different may reduce process options and and methods already well-known block configurations: save cost. in 2D design: spice models, pcells, design rules check (DRC), layout Data IPs (computing path), • Mixed-signal applications such as versus schematic (LVS), parasitic Memory (SRAM/ROM): High smart sensor, actuator, and inter- extraction (PEX) of both layers, and performance but wire conges- face (visible and IR imaging, nano global post-layout simulation (PLS) tion electromechanical systems (NEMS) (Figure 4). array, and LED) are particularly Clock tree: Keep accuracy and • interesting; 3D HD interconnects Spice models use data measured good circuits placement, very (MIV) and fine-grained partitioning acquired on CoolCube process sensitive to BEOL loading drastically reduce the footprint and development engineering lots. save power. Logic I/O, Analog/RF and pas- Both 28nm FD-SOI and CoolCube • technology stacks are merged to sive: Dedicated process options 3D sequential technology is also required perform technology computer aid- very promising in computing ed design (TCAD) simulations and systems. In this case, the parti- Service functions (as test / to align top layer RC parameters • tioning can be done between logic power management): Less extracted at the design level using and other hardware IPs such as performance-driven but close Mentor Graphics Calibre XACT tool. SRAMs, rapid IOs, signal convert- imbrication with Data IPs ers, test infrastructure, and power On the CoolCube layer, a standard- For evaluation, two main imple- management. cell-based digital design is available mentations are tested: Node N over using classical logic synthesis (Syn- Node N and Node N-1 over Node A complete EDA environment to opsys DC-Compiler 1-2016.03) and N. Both implementations are com- design 3D test chips on Cool- place and route tools (Cadence In- pared to a 2D Node N configura- Cube technology novus 16.20). In the context of logic on IPs (SRAMs or other) MIVs are tion. Although it exhibits additional During the last four years at Leti, a managed automatically by the tools process complexity with an impact 2-layer technological and applica- (power distribution from thick metal on yield or cycle time, for example, tion design environment has been layers to bottom IPs, signal inter- for digital products based on ho- developed to design and fabricate connects between bottom IPs and mogeneous stacking of N/N nodes, real circuits as demonstrators of top standard cells). 36 standard the model shows that 3D sequential this 3D sequential integration. The cells are today available, allowing a integration provides significant cost recent H2020 3D-Muse project lead first routine circuit design: savings (Figure 3). These savings by Leti started in January 2018. It are essentially due to the area re- will allow us to deliver a first proof Inverters: IVX9, IVX18, IVX35, duction and the increased number of concept. • of dies per wafer. From one node N IVX71

Figure 4: The CoolCube design process flow (L). Who does what in the collaboration with Leti and ST Microelectronics

48 The First Decade • Buffers: BFX9, BFX18, BFX35, to adjust the threshold voltage after characterization (based on spice BFX71 fabrication; specific fillers (FILLERP- simulation with layout) FPx-CO3) ensure DRC clean design • Logic gates: NAND2X7, when the ground plane is opened • Place and route flow using Ca- NAND3X5, NOR2X6, NOR3X4, due to the presence of MIVs. dence Innovus with LEF techno XNOR2X9, XOR2X9, AOI12X6, (techno and routing informa- AOI211X9, AOI22X6, OAI12X6, Design flows and tion including MIV rules), QRC OAI211X11, OAI22X6 methodologies techfile (3D stacking definition, RC data generated from ICT file) • Flip-flops: SDFPQX9, SDF- Since the article we published four and LEF files (SC layout abstract PRQX9 years ago, the Leti design team has view) also worked on a set of methodol- • Balanced cells: CNIVX10, ogies to properly design a circuit A first evaluation has been done to CNIVX21, CNIVX41, CNIVX62 using the CoolCube concept. For compare thermal performances of and latch: CNHLSX10 for gat- a PLS and PEX module, a deck of different 3D technologies, some- ed-clock tree MIPT format files is available that thing that is always put forward contains the description of the when we talk about 3D. To com- • Decoupling cells: DECAP8, top-level stacking (FEOL/BEOL), pare TSV+µ-bumps, hybrid bonding DECAP16 bottom level considered as sub- and CoolCube, we use a simple strate (emulation), and also includes method that defines a represen- Filler cells: FILLERPFP1, FILLER- • technology information such as tative set of experiments, different PFP2, FILLERPFP4, FILLERP- metal resistivity, contact resistance, technology parameters (number of FP1-CO3D, FILLERPFP2-CO3D, etc. and corner type. layers, 3D interconnection pitch, FILLERPFP4-CO3D; materials, etc.), a different power The output is a netlist including Well-tap cell: FILLERSNP- scenario, and thermal dissipation • resistor-capacitor (RC) parasitic WP-FP4_GP are available in- scheme. The thermal model used elements and standard cell charac- cluding classical views for P&R, is the SAHARA tool from Mentor terization. CoolCube circuit design Verilog and spice simulation, Graphics. The results show a better uses signoff 2D tools, reuses 2D ATPG… thermal coupling for hybrid bonding power mesh and clock tree, and and CoolCube, a reduced hot-spot • A first set of I/O pads com- co-optimizes cell density from one effect, but also a strong sensitivity patible with CoolCube is also tier to the other. Digital flow & CAD to interconnect density and die available to build an I/O ring tools are regular tools such as: thickness. and develop any test chip in a Synthesis flow using Synopsys package • A second MPW was launched to DC Compiler with LIB & DB examine multi-tier embedded mem- The common ground plane is used files (function/timing) and cell ory / multiple array on periphery

Figure 5: The 1st and 2nd MPWs resulted in the determination of the reduced cost to interconnect architectures and tools, IPs, and intermediate MPW focus

3D InCites Magazine 49 partitioning to look at the advantage common platform for multi-applica- support. Leti is now implementing of 3D compared to a 2D architecture tion-driven technological develop- the first application engagements in (Figure 5). ments. Leti’s strength has been to industrial product roadmaps to get the full benefit of the technology. The bottom level was dedicated to all decoding logic, drivers, I/Os, and A first application of the concept redundancy. The top level was a FOR SYSTEMS will be to enable partitioning up to 128x128 SRAM array connected by the transistor device scale (Figure MIVs. Three scribe lines have been REQUIRING HIGH 6). When imaging N/P or P/N FET designed, including a 2D reference PERFORMANCE, stacking, enormous gain is obtained 16kb SRAM with 32-word redun- by boosting each FET performance dancy blocks, and two 3D 16kb ADVANCED 3D independently on each level. Each SRAM with 32-word redundancy FET polarity would pick up the block either using MIVs or single 3D TECHNOLOGIES best possible channel material, TSVs. gate stack, stressors or contact SUCH AS HYBRID metallurgy. A 3D fine connection at The objective will be a first tape out the device level will provide device at IP level (building block) but early BONDING AND level outperformance (current/ca- results from layout show a 40% pacitance) and will spare front-end footprint reduction, with ~100000 MONOLITHIC 3D players numerous expensive lithog- transistors on top cold process, and raphy steps and process selectivity 2068 MIVs – Density: 37600 MIVs / ARE CONSIDERED challenges vs. planar 2D schemes. mm². Based on the same methodologies, a 2nd test chip resolving a TO BE THE ONLY This Holy Grail requires redesign of 32-bit RISCV (RI5CY) SoC will be all libraries and standard cells with a embedded in the 3D Muse MPW in WAYS TO PUSH limited area gain, much below 50%, order to perform a real case bench- considerably reducing the area gain mark between 3D and 2D. COMPUTING TO for SRAM, for example. HIGHER LEVELS. Test cases, applications, and Leti is also relying on a CMOS over CMOS approach as we have seen future work gather a full ecosystem of partners earlier. The first ideas are coming for around its program, including mate- After more than ten years of re- new digital architectures including rials companies, tool suppliers, EDA search and development, Leti sees logic-on-memory for data-intensive providers, fabless and fab com- the CoolCube concept becoming a computing (data analytics or data panies, test, and characterization

Figure 6: N/P or P/N: the integration engineer’s holy grail

50 The First Decade Figure 7: Smart sensing in a matrix retrieval), and of course for neuro- processor in the next ten years, non-volatile memories, mask and morphic convolutional neural net- based on the CMOS silicon spin PDK, models/simulations and test/ works for deep learning and artificial technology developed by the Greno- characterization activities. He joined intelligence accelerators. ble team including CEA Leti, CEA CEA-Leti in 2013 as Microelectron- Inac and CNRS Néel Institute. Much ics Business Development Manager Both test cases are dominated by less advanced than the supercon- after a 20-year career in technical memory and wires, organized as a ducting devices, silicon spin qubit and management positions at Altis parallel matrix of computational data reveals itself to be as performing but Semiconductor and IBM Microelec- loading, with performance obviously much more scalable thanks to VLSI tronics. enhanced by the density of contacts 300mm process integration. Then, allowed by the CoolCube integra- the only way to conceive a system Prior to joining CEA-Leti, he was tion. It really can be seen as an architecture for a quantum proces- technology transfer officer at Uni- extension of 3D hybrid bonding for sor is to use 3D technology, at a versity of Lyon (France). He was close memory/logic entanglement pitch density level made possible member of the board of Manesman and disruptive design approaches. by using CoolCube 3D sequential Business Angels, an investment integration. network for high tech start-ups in The first industrialization for Cool- Paris (France). Jean-Eric Michallet Cube will probably come from smart received the M.S degree in Micro- sensing in a matrix. First applica- electronics from ENSERG Institute tions will be driven by image sen- (Institut National polytechnique de sors, µdisplay panels, NEMS mass Grenoble, France), an Executive spectroscopy, biological nanowires MBA and a Master’s degree in sensing or DNA computing. International Management from Dauphine University Paris (France)/ Partitioning the application at the UQAM Montreal (Canada) and a elementary sensing spot increases Management Certificate, Sustain- the sensing area while also permit- ability and Social Responsiveness ting a smart 3D in-element process- from ESDES Lyon. ing for sensing adaptation, calibra- tion, pre-processing, etc. CoolCube Acknowledgments offers each sensor element to be addressed individually with more Thank you to the following persons than one tiny contact, inducing less from Leti, for their contributions to parasitic effect, better signal devel- this article: François Andrieu, Perrine opment and optimization between About the Author Batude, Laurent Brunet, Séverine the analog and the digital stages. Jean-Eric Michallet manages the Chéramy, Gérald Cibrario, Claire Microelectronics Components Fenouillet, Richard Fournel, Xavier Lastly, CoolCube will be one of Department at CEA-Leti, cover- Garros, Didier Lattard, Sébastien the major enablers to allow Leti to ing advanced CMOS, advanced Thuriés, Maud Vinet develop a multi-thousand qubits

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52 The First Decade

A M ERI C A S • C H I N A • E U R O P E • J A P A N • K O R E A • S O U T H E A S T A S I A • T A I W A N Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging

An interview with Anil maintain superior yields. From a last 10 years. For example, manu- Vijayendran, Veeco Instruments surface preparation perspective, facturers have relied heavily on wet there are more cleaning steps with benches for PR strip and etch pro- As the semiconductor industry shifts a greater attention to defectivity. cesses. We’ve also seen the shift to focus from CMOS scaling to hetero- Specific to wet processing, the last single wafer equipment to improve geneous integration, the importance 10 years has seen a greater number process control. Wet benches, while of surface preparation and wafer of strip, wet etch, and plating steps less expensive, cannot meet the cleans during semiconductor device with a greater focus on dimensional stringent uniformity and undercut manufacturing is migrating from control as this packaging method requirements of advanced package front-end wafer processing to back- has become more prevalent. techniques that single wafer equip- end wafer level packaging process- ment can. But, as mentioned before, es. This is due to a combination of A key challenge to the adoption these single wafer tools must deliver high-reliability applications, such as of WLP is cost. As such, suppli- competitive CoO. This has led to a autonomous vehicles, 5G, artificial ers have been tasked with work- greater focus on filtration, reduced intelligence (AI), and the internet ing closely with fabs to meet the chemistry usage and chemical mon- of things (IoT), and the high-den- technical requirements of evolving itoring to minimize operational cost. sity requirements of the advanced packaging designs while still driving packaging technologies being used. lower cost-of-ownership. This From a chemistry and materials For higher density fan-out wafer partnership is dependent on refined view, the new advanced packag- level packages (FOWLP), 2.5D and hardware, chemistry and process ing methods have introduced new 3D integration technologies, proper to achieve sustainable high-volume bumping and barrier materials preparation of the wafer surface, manufacturing (HVM) results. Over – moving from traditional solder and ongoing clean steps throughout the past decade, we have also seen to materials such as gold, nickel, the process flow, can greatly impact increased focus on environmental and titanium. Other shifts included the reliability of the device for which health and safety (EHS) by decreas- transitioning from a fluxing process that chip package is destined. ing adverse impacts of the chemical to a fluxless process as dimensions formulations used. shrink in 2.5D and 3D packaging ap- To get a clearer picture of how this plications. These changes required impacts semiconductor equipment 3D InCites: How have these new chemistries and methods and materials suppliers, 3DInCites trends affected the wet process- of delivery that maintain suitable spoke with Anil Vijayendran, vice ing equipment and materials throughput and are cost competi- president of marketing at Veeco market? tive. Moreover, chemistry manufac- Instruments, Precision Surface Pro- turers have invested significantly to cessing Division. Vijayendran: The equipment and optimize formulations that improve materials industries have experi- process characteristics such as 3D InCites: What do you see as enced significant change over the material selectivity. From an EHS the major trends in the advanced packaging space, especially in the context of surface preparation methods over the last 10 years?

Vijayendran: During this time the industry has seen a push toward wafer-level packaging (WLP) to meet growing performance demands in input/output (I/O) density, speed, form factor. Starting in 2009, the earliest form of fan-out wafer level packaging (FOWLP) was put into production. Now, more designs are being introduced by outsourced semiconductor assembly and test (OSAT) providers and foundries to address a growing application base.

WLP requires a higher degree of control and process capability to

3D InCites Magazine 53 standpoint, there has also been a also change from silicon to a glass Vijayendran: Looking ahead, we shift away from manually operated or polymer compound. Equipment will see continued consolidation in equipment and refinement in airflow must be able to handle these differ- the industry. Device manufacturers design with wet process tools, ent materials and in many cases on will push OSATs for more technical thus reducing worker exposure by the same tool. From a dimensional advances to enable further perfor- changing the tools performing the standpoint, as the I/O count increas- mance benefits to meet require- processes as opposed to changing es, the line/space (l/s) dimensions ments for 5G, AI and the IoT. The the solvents themselves. will shrink to 2µm while the number industry will be focused on how to of redistribution (RDL) layers in- improve process control at 2µm l/s 3D InCites: What challenges creases. Surface processes must be and below. Undercut control and have packaging houses and able to maintain dimensional control defectivity will become more im- equipment manufacturers and without damaging the substrate. As portant as defects could now kill the materials suppliers overcome in an example, for a 100µm bump, a package. Tools will become more the last decade? 1µm undercut has a minimal effect flexible as the number of processes, on performance. At 2µm l/s, a 1µm wafer types, and sizes increase. Vijayendran: A significant chal- undercut will be a performance Panel-level packaging may also lenge for the industry has been killer. Equipment and chemistry gain momentum for certain devices, to drive costs down while devel- manufacturers will be pushed to which could be a catalyst for a par- oping advanced technology that provide better process control to allel investment cycle in the industry. meets a wide range of application enable these smaller dimensions OSATs will need the flexibility to stay requirements. To overcome this moving forward. competitive and continue to push hurdle, packaging players have suppliers to offer more modular consolidated. The trend towards 3D InCites: What about cost solutions. Finally, OSATs and found- fewer, but larger-sized, packaging reduction trends and the impact ries will need to partner with more entities allows for a greater amount on the industry? global suppliers that have design of dedicated resources to focus and full process support capabilities on difficult technical problems. As Vijayendran: In recent years, it has as they look to build a competitive these technical challenges became been a constant battle to maintain supply of advanced packaging more complex, packaging houses performance and low cost. Yet for offerings. continued to partner with equipment these advanced packaging tech- and material suppliers that can tailor niques to become mainstream, About Anil Vijayendran solutions for their needs. This trend costs must continue to decrease. is especially prevalent today as One way could be through imple- larger equipment suppliers tradition- mentation of panel-level packaging. ally focused on front-end fabrication By increasing the substrate size, have receded from the advanced manufacturers expand the usable packaging market. Meanwhile, die per substrate. On paper, this nimbler, mid-sized global compa- may seem like a simple concept, but nies and local suppliers have built it is more difficult in execution. Pro- product offerings dedicated to the cess performance on rectangular advanced packaging market. substrates will be different than on circular substrates. Wet processes, 3D InCites: Looking forward, such as etch and clean, will not have what technical challenges do the same uniformity on rectangular new packaging techniques substrates as circular ones without present to the wet processing re-thinking the equipment capabili- market? ty, process, and design. Difficulties with uniformity are further magnified Anil Vijayendran is the vice president Vijayendran: As Moore’s Law by the sheer area of the panel as of marketing for Veeco’s precision slows, and the expense of de- well as warpage across the panel. surface processing business unit. vice scaling below 7nm becomes Handling such large substrates where he leads all end-to-end increasingly challenging, chip also poses significant challenges. product management and marketing manufacturers are looking to het- Robotic systems and system archi- efforts. erogeneous packaging techniques tectures must be modified to handle to achieve the performance benefit. the heavier substrate as well as the Prior to Veeco, Vijayendran was the Heterogeneous packaging involves warpage. Lastly, moving all equip- vice president of sales and mar- significant complexity such as ment suppliers to a new substrate keting for MiaSolé, and served as substrate and dimensional control, size is of critical importance. the director of business develop- which impacts wet processes. The ment and product management at substrate material can be severe- 3D InCites: Given these chal- Novellus Systems, a Lam Research ly warped (in some cases up to lenges, what is your prediction company. Vijayendran holds an 10mm), so the equipment must be for the wet processing equip- MBA from the University of Califor- able to handle this deflection while ment and materials market for nia, Berkeley, and an MS and BS in still maintaining process perfor- the next few years? chemical engineering from MIT. mance. The substrate type can

54 The First Decade Reliable Process Control Solutions for the Growing Power Device Market

By Dr. Dario Alliata, Unity-SC

The expected increase of power device markets — and more particularly insulated-gate bipolar transistor (IGBT) products for automotive and other applications — is pushing the semiconductor industry to adopt specific process solutions. The maturity of IGBT market, boosted Figure 2: Simultaneous thickness measurement of a four-layer stack at gate area. From top to by a booming demand for electrified bottom: Silicon/metal/adhesive material/glass carrier vehicles (EV) and hybrid electrified vehicles (HEV), and the consequent package size miniaturization targets In-line control of the device thick- need for improved manufacturing are met, while simultaneously ness and its integrity from defectivity yield to stay economically competi- enhancing the device performance perspective are a must to secure the tive, has forced several device mak- and reducing power loss. product functionality and prevent fu- ers to collaborate with their supply ture failures once in use on EV/HEV. chain in developing ad-hoc process In the typical process flow used for control solutions. IGBT fabrication, the backside thin- Thickness control ning is identified as one of the most For several years, Unity-SC has critical steps (Figure 1). Fabrication specifications for the collaborated with major IGBT thickness of the final package are makers to secure the most critical Back grinding is the most popular often connected to reliable perfor- fabrication steps in the manufactur- process method used to reduce mance. Consequently, measure- ing chain from the front-end down the wafer thickness because it is a ment methods with good Gage to the advanced packaging area. low-cost and high-speed technique. repeatability and reproducibility More specifically, the company However, the mechanical stress and (GR&R) at key device locations must has focused its efforts to develop heat applied during this process be chosen. non-conventional solutions for the generates damage that can be wafer thinning area. removed by using different methods In the example illustrated in Figure to improve the final surface finish. 2, the wafer is glued on a temporary In fact, thanks to the reduction in Nevertheless, any remaining defect support carrier during thinning. The wafer thickness, shorter wiring or on the backside surface may gener- thickness of four material layers is through silicon via (TSV) pitch can ate final defective dies. simultaneously measured by com- be reached and simultaneously bining two interferometric point sensors that use time-domain analysis to control all layers from both sides of the structure. The integrated visual capability of the measurement sensors allows the identification of the embedded target non-visible at the surface by looking for its pattern at sub micrometer precision through the silicon with near infra-red (NIR) microscopy.

The measurement capability is reached on a stack that includes transparent material like Si or adhesive, and opaque material like metals, where thicknesses for each layer may vary from a few microns up to almost a millimeter. On a metrology tool only capable of addressing one-layer thickness at the time with a dedicated technique, this would require stopping the wafer. Figure 1: Fabrication process flow of IGBT device

3D InCites Magazine 55 Today, however, the device maker size has the potential to introduce of the curvature image, while stains can choose metrology platforms latent defects that might cause and residues are extracted from the like the TMAP Series from Unity-SC, device failure even years later after reflectivity image. Additional infor- which combines complementary its fabrication. Traditional automatic mation on the wafer’s global integrity technologies and an optimized optical inspection systems are not are reachable from the topographic optical design to address metrolo- sensitive enough to catch killer de- map. gy control in one single step. This fects with very low optical contrast. translates to a considerable re- Additionally, the edge of the wafer duction in operational cost for the Unity-SC has developed proprietary can be inspected by 2D line scan device maker. detection technologies capable technology based on confocal of detecting all critical anomalies. chromatic imaging. The natural Using complementary information For example, phase shift deflection extended depth of focus provided gathered while measuring the thick- (PSD) is a powerful technique that by the chromatic lens is the perfect ness, the TMAP series can quantify guarantees detection of topographic tool to recognize chips, cracks, and the bow/warp and the total thick- defects in a height range of only few contamination located at the five ness variation (TTV) of the bonded nanometers, and at an inspection zones of the bevel area (top, top wafer and prevent the wafer from rate of 100wph. bevel, apex, bottom bevel, bottom), continuing through the production that can propagate on the wafer line if it is no longer within the spec- PSD is used to inspect the backside during process stress conditions surface and generate complemen- and damage the dies.

Handling challenges

Beside the measurement diffi- culty, another major challenge is wafer handling during the thinning process. In fact, when the wafer’s thickness is reduced from several hundred microns down to few tens of microns, the mechanical proper- ty of the silicon substrate prevents the wafer from being moved across multiple processing tools without ad hoc solutions. Any device maker is forced to finding the best approach to overcome the handling limitations at a sustainable cost. The wafer can be temporarily bonded on a silicon or glass carrier, it can be trans- formed to a Taiko wafer, or mounted on a dicing frame. Notch-detection on dirty bonded wafers and the need for partial or full contactless handling are examples of the additional capabilities faced by equipment manufacturers.

As supplier a of leading-edge inspection and metrology equipment worldwide, Unity-SC is committed to developing reliable solutions to meet any specific fab requirement. Figure 3: Quality control strategy and DOI detectable by 4SEE series from Unity-SC equipped Investments in internal development, with deflector module as well as mergers and acquisitions over the last two years, provides customers with the validity of our ifications. This avoids wafer break- tary whole wafers images, each one process control capabilities, and the age in the fab that incurs costly used to extract different digital optic uniqueness of our contribution to equipment downtime. identifiers (DOIs) and wafer macro properties (Figure 3). Topographic secure their fabrication processes. defects like comets, surface dislo- Backside thinning quality Today, with several 4SEE and TMAP cations, and star and hair cracks control systems in use at IGTB makers, and can be detected and separated from thanks to bilateral collaboration with The aggressive backside thinning grinding marks through automatic our partners, we are ready to serve process needed to reduce package defect classification (ADC) analysis almost any wafer thinning need.

56 The First Decade 3-D NAND – Where Haste You So?

By Andrew Walker, taining trillions of memory bits; And solving intractable problems through Schiltron Corp. a roadmap to hundreds of layers. increasingly cross-disciplinary approaches. The rate of innovation That’s where we are now with 3-D increases almost as a corollary to NAND. How did we get here so Moore’s Law. The history of Flash quickly? And what does the future memory is a history of the semicon- hold for this technology? ductor industry itself. For those who are curious, type the following into Ten years is a lifetime in silicon Google search: “tunneling through technology but as with all things barriers Andy Walker”. silicon, 3-D NAND is an “evolution- ary revolution”. It builds on what has So how did 3-D NAND get here? gone before. Nothing really “comes out of the blue”. A NAND string is a At a strategic level of course, it looks NAND string whether it be in 2-D or fairly straightforward. The rise of 3-D. It is just a series connection of “Big Data” and therefore the need field-effect transistors where each for “Big Memory” coincided with one has the ability to store electric 2-D NAND running out of steam. At Sixty-four towering spires in prod- charge that changes its threshold the next level, other considerations ucts; Ninety-six on the verge of voltage. Each building block of the come into play: the explosive rise manufacturing and counting; Single technology evolved from other build- of mobile applications; the need for chips with a trillion memory bits all ing blocks whose origins stretch speed to get to data; the absence of hovering above a piece of crystalline back across decades. moving parts to improve reliability. silicon that contains the control circuitry; Deep and narrow chasms be- Innovations that are regarded as And what does “running out of ing etched and filled using tools that breakthroughs at their moment of steam” really mean? 2-D NAND has were “out of this world” just a few introduction meld into the in- always been driven by lithography. years ago; Dedicated multi-billion creasingly complex fabric of the Reducing the cost per bit means dollar fabrication facilities churning history of technology. Technology shrinking the memory bit. The out millions of silicon wafers con- development drives ever onwards memory bits get closer together

3D InCites Magazine 57 is obvious but tricky since low-resistance metals cannot be used because of subsequent process temperatures.

Minimizing lateral dimensions has involved sharing vertical source connections with multiple vertical strings. Maximizing electrical bits per cell has taken 3D NAND from single-level cell (SLC), through multi-level (actually two) cell (MLC) and triple-level cell (TLC), to quadru- ple-level cell (QLC). It looks like the only way is up with manufacturers confidently projecting roadmaps to hundreds of layers.

To make a guess at what the future holds, we need to understand what challenges stand in the way of this glittering future and what the con- sequences are of certain technical choices. Figure 1 – Excerpts from the 3-D NAND papers from Toshiba in 2007 and Samsung in 2009 (© IEEE). When more layers are added, the NAND string gets longer, its elec- and increasingly electrically interfere What does the future hold? trical resistance increases, and the with one another. At the same time, electrical currents during read go The silicon memory industry has be- the amount of electric charge that down. Up until now, manufacturers come adept at squeezing out cost in each can store reduces, resulting have tried to minimize this effect whatever technology is in develop- in reliability issues. Heroic efforts by reducing the vertical distance ment. This translates to maximizing are made to “keep the show on the between wordlines. The 3D NAND memory bit density. road” and get to the next technology channel material is non-crystalline node. The cost of doing so increas- silicon, which has limited conduc- es each time with the result that the For 3D NAND, the ways to do this are: tivity and exacerbates the effect. technology “brick wall” is really the Research and development (R&D) gradual law of diminishing returns. • Stuff peripheral circuitry under- activity is already taking place to investigate channel materials with Going 3D to increase memory den- neath the 3-D memory array higher conductivities. Expect to hear sity was being worked on in parallel Minimize lateral cell dimensions more discussion of this topic as it as 2D NAND was shrinking. Thin- • film transistor (TFT) based 3D Flash • Maximize the number of electrical concepts using floating gates to bits per cell store charge were published in the 90s while the first charge trap TFTs using the Silicon-Oxide-Nitride-Ox- ide-Silicon (SONOS) approach came out in the early 2000s. And then in 2007, Toshiba (it always seems to be Toshiba) published their seminal paper on bit-cost scalable technology. Two years later, Samsung published their version called “Terabit Cell Array Transistor”. Figure 1 shows excerpts from those two papers. All Figure 3: The effect on P/E cycling endurance versions of 3-D NAND in production Figure 2: Cross section of Samsung 86 Gb of storing more electrical bits per cell. (Data today can more or less trace their 32-layer 2nd generation v-NAND (source: from Micron at www.micron.com/products/ heritage to these — except for Intel chipworks) advanced-solutions/qlc-nand). and Micron. These companies have favored the use of floating gates to • Stack more layers becomes critical to layer stack-abil- store charge probably due to long- ity. In addition, fancier stacking held engineering suspicions about It looks like the first three approach- approaches may come to the fore the manufacturability of charge trap es have been exhausted. Using that limit string lengths by slotting in approaches. silicon area underneath the array

58 The First Decade Figure 4 – Cell P/E endurances for various SSD products using either 3D NAND or 3D XPoint technology. DWPD and PBW are taken from publicly available data sheets. A WAF of 1.5 has been assumed for the NAND-based SSDs more bitlines vertically in the stack. tric” and “mixed” workloads. Storage endurances are possible. Samsung’s tiering, where MLC and TLC/QLC new “Z-NAND” is known to be SLC Another effect of longer (taller) NANDs are combined in a system, and is limited to below 100k cycles. strings is greater disturbs on each can also limit the program-erase Interestingly, 3D XPoint also seems cell during read and program. This (P/E) stress on the TLC/QLC parts. to be limited to way below this value, reduces the electrical “distance” at least for the products analyzed. between bits in the 3-D NAND. With Figure 2 shows the fundamental This seems at odds with the original more than one electrical bit per tradeoff that manufacturers are mak- promise of 3D XPoint and may be cell, this distance is already limited. ing is to lower acquisition cost ($/ intermediate products on the road to Expect to hear about the limits of GB) while raising TCO ($/(PetaBytes higher endurances. combining TLC/QLC with the tallest written). Market segmentation and 3-D NAND strings. storage tiering are used to limit the Since “Big Data” will only get bigger, TCO increase. write-centric workloads will increase Finally, expect more discussion in volume. For these, the TCO is ba- about cost, acquisition cost, total P/E endurance at system level uses sically inversely proportional to the cost of ownership (TCO), market terms such as drive-writes-per-day endurance. Expect more discussion segmentation, and storage tiering. (DWPD) and peta-bytes-written about acquisition cost versus TCO To understand why, look at Figure 2. (PBW). Figure 3 shows my conver- especially given the inexorable rise sions of these (taken from available of enterprise storage where sophis- NAND (both 2D and 3D) has inter- data sheets) to NAND cell endur- ticated TCO models tend to hold esting limitations when it comes to ance. Apart from possible arithmetic sway. Also, any 3D technology that cycling. The linear string of transis- error, the conversion depends on can use the 3D NAND ecosystem tors means that unselected devices something called the write amplifi- and can boost endurance by at least have to be turned on to read or cation factor (WAF). This basically an order of magnitude could gain program any particular cell. These means how many NAND writes are attention. actions disturb those devices. actually made at silicon level for Engineering minimization of these each time the system decides to In summary disturbs leads to thick dielectrics in write and is inherent to the NAND each transistor. This increases the architecture. My assumption for this The towering spires of 3-D NAND voltages needed and the damage is included. I have also included have shot up. But they need to keep and inadvertent charge trapping that calculations for 3D XPoint systems on shooting up to continue reducing result from program and erase. SLC as a comparison. cost per bit since all other avenues has the largest electrical distance for cost reduction look to have been between bits allowing more damage Several conclusions arise from this exhausted. Discussions will focus on to build up while QLC has the least. analysis. First, 3-D NAND remains channel materials, fancy 3-D inte- in an endurance straitjacket when gration schemes, ability to combine Manufacturers cope with this dra- compared to other non-NAND TLC/QLC with taller strings, and total matic effect by segmenting the mar- charge trap Flash approaches, cost of ownership. Interesting times ket into “read-centric”, “write-cen- where orders of magnitude greater indeed.

3D InCites Magazine 59 Historical Perspective continued from 14

chips with several functions on them could deliver “10nm CPUs”, which consulting company Microelectronic can be “disaggregated” or “disin- could have 14nm and 22nm chiplet Consultants of NC in the RTP NC tegrated” into separate functions. modules within them. So, memory, area. He retired from Dow Chemical These separated functions can be graphics, power regulation, and AI in 2004 as Global Director of Tech- fabricated at different scaling nodes function could all constitute separate nology for their Advanced Electronic to optimize final performance and chiplets, some of which could be Materials business unit. Phil has reintegrated onto a 2.5D silicon stacked with TSVs to a high-density served as Technical VP and Presi- interposer. This strategy also allows silicon interposer. dent of both IEEE EPS and IMAPS for IP reuse of such known good and is a Fellow of both organiza- chiplets in other designs. What does the future hold? tions. He has edited several microelectronic texts including McGraw The current DoD DARPA program, With an end coming to CMOS scal- Hill’s “Multichip Module Handbook” Common Heterogeneous Inte- ing, something new will be taking its and Wiley VCH’s “Handbook of gration, and IP Reuse Strategies place. It is not clear what that new 3D Integration”. He has won the (CHIPS), is attempting to standard- technology will be, but it is certain Milton Kiver Award for Excellence ize communication interfaces and that it will take more than a decade in Electronic Packaging (1994); the physical sizes to allow for prolifera- to implement. The new technolo- Fraunhofer International Adv. Pack- tion of this technology into both the gy will ultimately determine where aging Award (2002); the IEEE CPMT commercial and military worlds. packaging will go, but at this point Sustained Technical Achievement we can only all guess what that will Award (2007) , the IMAPS Ashman In fact, Intel, a leading member be. But, one thing we can say about Award (2000) and most recently the of the CHIPS program, recently chip packaging is, “we’ve come a American Chemical Society Award indicated that starting in 2019 it long way baby!” for Team Innovation (2017). His will separate various processor weekly publication Insights From components into smaller chiplets, About the Author the Leading Edge (IFTLE) has been each of which can be manufactured Dr. Phil Garrou is a subject mat- a weekly advanced packaging blog using an optimum (performance/ since 2010. cost) production node. Thus, Intel ter expert for DARPA and runs his

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6 (December 2017), pp. 16-20 (see http://fbs. letis, Tobias Burgherr, ‘Vesuvius-3D: A 3D-DfT Mumbai, India, November 2015, pp. 79-84, DOI advantageinc.com/chipscale/nov-dec_2017/#18) Demonstrator’, IEEE International Test Confer- 10.1109/ATS.2015.21 ence (ITC’14), Seattle, WA, USA, October 2014, 11. Ferenc Fodor, Erik Jan Marinissen, Daniele Paper 20.2, DOI 10.1109/TEST.2014.7035332 18. Leonidas Katselas, Alkis Hatzopoulos, Hailong Acconcia, and Raffaele Vallauri, ‘Leading-Edge Jiao, Christos Papameletis, and Erik Jan Wide-I/O2 Memory Probing Challenges: TPEG 15. Sergej Deutsch, Brion Keller, Vivek Chicker- Marinissen, ‘On-Chip Toggle Generators to MEMS Solution’, Semiconductor Wafer Test mane, Subhasish Mukherjee, Navdeep Sood, Provide Realistic Conditions during Test of Workshop (SWTW’18), San Diego, CA, USA, Sandeep K. Goel, Ji-Jan Chen, Ashok Mehta, Digital 2D-SoCs and 3D-SICs’, IEEE International June 2018, Paper 2.3 (see http://www.swtest. Frank Lee, and Erik Jan Marinissen, ‘DfT Ar- Test Conference (ITC’18), Phoenix, AZ, USA, org/swtw_library/2018proc/PDF/S02_03_Fodor_ chitecture and ATPG for Interconnect Tests of October 2018 SWTW2018.pdf) JEDEC Wide-IO Memory-on-Logic Die Stacks’, IEEE International Test Conference (ITC’12), Ana- 19. Erik Jan Marinissen, Teresa McLaurin, Hailong 12. IEEE Standards Association. IEEE Std 1500™- heim, CA, USA, November 2012, DOI 10.1109/ Jiao, ‘IEEE Std P1838: DfT Standard-under-De- 2005, IEEE Standard Testability Method for Em- TEST.2012.6401569 velopment for 2.5D-, 3D-, and 5.5D-SIC’, IEEE bedded Core-based Integrated Circuits. IEEE, European Test Symposium (ETS’16), Amster- August 2005, DOI 10.1109/IEEESTD.2005.96465 16. Christos Papameletis, Brion Keller, Vivek dam, the Netherlands, May 2016, DOI 10.1109/ Chickermane, Said Hamdioui, and Erik Jan ETS.2016.7519330 13. Cadence/imec joint press release, ‘Imec and Marinissen, ‘A DfT Architecture and Tool Flow for Cadence Deliver Automated Solution for Testing 3D-SICs with Test Data Compression, Embed- 20. Yu Li, Ming Shao, Hailong Jiao, Adam Cron, 3D Stacked ICs’, June 6, 2011 (see https://www. ded Cores, and Multiple Towers’, IEEE Design & Sandeep Bhatia, and Erik Jan Marinissen, cadence.com/content/cadence-www/global/ Test, Volume 32, No. 4 (July/August 2015), pp. ‘IEEE Std P1838’s Flexible Parallel Port and its en_US/home/company/newsroom/press-releas- 40-48, DOI 10.1109/MDAT.2015.2424422 Specification with Google’s Protocol Buffers’, es/pr/2011/imecandcadencedeliverautomated- IEEE European Test Symposium (ETS’18), solutionfortesting3dstackedics.html) 17. Konstantin Shibin, Vivek Chickermane, Brion Bremen, Germany, May 2018, DOI 10.1109/ Keller, Christos Papameletis, and Erik Jan ETS.2018.8400690 14. Erik Jan Marinissen, Bart De Wachter, Stephen Marinissen, ‘At-Speed Testing of Inter-Die Con- O’Loughlin, Sergej Deutsch, Christos Papame- nections of 3D-SICs in the Presence of Shore Logic’, IEEE Asian Test Symposium (ATS’15),

60 The First Decade 3D InCites Magazine 61 IN PICTURES 2009

62 The First Decade 2010

3D InCites Magazine 63 2011

64 The First Decade 2012

3D InCites Magazine 65 2013

66 The First Decade 2014

3D InCites Magazine 67 2015

68 The First Decade 2016

3D InCites Magazine 69 2017

70 The First Decade 2018

3D InCites Magazine 71 ADVERTISER INDEX

EV Group evgroup.com 2 Kiterocket kiterocket.com 5 Amkor Technology amkor.com 6 UnitySC unity-sc.com 11 FRT frtmetrology.com 15 Form Factor formfactor.com 22 TEL tel.com 25 Trymax trymax-semiconductor.com 30 3D Incites 3dincites.com 35 Imaps imaps2019.org 47 Semi semi.org 52 Genmark genmarkautomation.com 61 KLA kla.com 73

How it All Began: Even the Magic 8 Ball couldn’t have called it

the rebound of the semiconductor it’s subsidiary, Smart Equipment manufacturing industry. But even Technology (S.E.T) will collaborate my trusty 8 Ball couldn’t have with IMEC to develop die pick-and- predicted my fate a week later, place and bonding processes for when the decision was made to 3D chip integration using S.E.T.’s integrate Advanced Packaging into flip chip bonder equipment. This Solid State Technology. However, will invariably open doors for the as I’ve been told by many pioneers start-up’s proprietary technology, of emerging technology in the semi- electrochemical replication process conductor manufacturing industry, (ECPR). a down-turn in the economy is a great time to innovate. Thus the So that’s the type of content read- launch of this Blog. After all, career ers can expect to find on this blog. innovations count, don’t they? After all, industry innovators without deep pockets for advertisng still My final curtain call was an inter- need to get the word out about view with Replisaurus CEO, Jim their progress. The success of this Quinn and CTO, Mike Thompson, industry rests on the shoulders of In my last editorial as managing who talked about how the compa- such companies. I’m happy to do editor of Advanced Packaging ny is in a great position to hit the what I can to give them a leg up. magazine, I suggested we should ground running when the economy F.v.T. turn to the Magic 8 Ball to predict rebounds. Their big news was that

72 The First Decade 3D InCites Magazine 73 74 The First Decade