High-End Performance Packaging 2020

From Technologies to Markets

High-End Performance Packaging: 3D/2.5D Integration 2020 Market and Technology Report

Sample

 Table of contents 2 o Package ASP split by technology 85  Scope of report 4 o Market value split by technology 88  Report methodologies & definitions 6 o 3D SoC  Key features of this report 5 o 3D stacked memory  About the author 7 o 2.5D interposers  Yole Group of companies related reports 9 o UHD FO  Glossaries 11 o Embedded Si bridge  Companies cited in this report 12 o Chapter conclusion 94  3-Page summary 13  Market trends 96  Executive summary 17 o Cloud & edge computing 97  Context 66 o Cloud computing and networking 103 o Semiconductor industry – players pursuing Moore’s law 67 o High-Performance Computing (HPC) 111 o High-end performance packaging definition 71 o Artificial intelligence for autonomous vehicles 119 o Scope of report 72 o Chapter conclusion 125 o High-end performance packaging market segment 73  Commercialized products and its supply chain 127 o High-end performance packaging introduction 74 o Product launches 130  Market forecasts 75 o 3D stacked memories o Market Revenue 76 o (x)PU o Total market revenue o GPU for HPC o Split by end-market o Supply chain for high-end performance packaging 156 o Split by technology o Global mapping of high-end packaging o Market Units 80 o Global mapping based on technology o Total market units o Supply chain for high-end packaging products o Split by end-market o Latest progress of key players 175 o Split by technology

o Supply chain analysis in high-end performance packaging 188 o TSV process 254 o Packaging supply chain analysis o 3D stacked memory 260 o Analyst’s point of view on supply chain 192 o HBM o It is a new battlefield for technology supremacy o 3D Stacking (3DS) DRAM o Impact within big players o 3D SRAM o Impact on OSATs & substrate suppliers o 3D NAND o What is TSMC strategy exactly? o Others: HMC, DRAM stacked memory o Who are the winners/losers? o 2.5D interposer 284 o Chapter Conclusion 201 o Ultra-high-density Fan-Out (UHD FO) 295  IP Analysis: 3D SoC – hybrid bonding 203 o Embedded Si bridge 301 o Patent overview 204 o Other high-end packaging technologies 310 o Supply chain IP position (examples) 208 o Chapter conclusion 315 o Chapter conclusion 212  Report conclusion 318  Technology trends 214  Appendix 320 o Technology roadmap 215 o OSATs high-end packaging technologies 321 o Semiconductor packaging roadmap  Yole corporate presentation 330 o Advanced packaging roadmap o High-end packaging roadmap: iO pitch vs IO density o High-end packaging roadmap: application-technology o Key player’s technology roadmap 221 o Short description of chiplet 227 o 3D SoC 230 o Hybrid bonding 234 o Key players’ technologies: hybrid bonding for 3D SoC

The main objectives of this report are: • To identify and describe which technologies can be classified as ‘high-end performance packaging’ • To define high-end performance packaging • To analyze key market drivers, benefits and challenges of high-end performance packaging by application • To describe the different existing technologies, their trends and roadmaps • To analyze the supply chain and high-end performance packaging landscape • To update the business status of high-end performance packaging technology markets • To provide a market forecast for the coming years, and estimate future trends

Fan-out packaging markets are studied from the following angles: • Top-down based on end-systems demand Are your needs • Market valuations based on top-down and bottom-up models beyond this • Market shares based on production projections report’s scope? • Supply value chain analysis Contact us for a custom: • State-of-the-art technologies and trends • End-user application adoptions

• Yole Développement’s definition of high-end performance packaging • High-end performance packaging market segmentation • Market valuation in terms of package units, revenue and wafer production volumes • Market valuation of key high-end packaging technologies • Includes COVID-19 impact in all forecasts • High-end performance packaging market trends: end-system drivers • Commercialization of high-end performance packaging products • Global mapping of high-end performance packaging supply chain • Supply value chain analysis in high-end performance packaging • Application-technology roadmap of high-end performance packaging • Key Player’s technology roadmap of high-end performance packaging : Intel,TSMC and Samsung • IP Analysis: 3D SoC – hybrid bonding

High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 5 REPORT METHODOLOGIES & DEFINITIONS Yole Développement’s market forecast model is based on the matching of several sources:

Preexisting information

Market Volume (in Munits) ASP (in $) Revenue (in $M)

Information aggregation

Favier SHOO

Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting reports.

During 7 years at Applied Materials as a Customer Application Technologist in the advanced packaging marketspace, Favier developed an in-depth understanding of the supply chain and core business values. As an acknowledged expert in this field, Favier has provided training and held numerous technical review sessions with industry players. In addition, he has obtained 2 patents.

Prior to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity. Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans.

Favier holds a Bachelor’s in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore).

[email protected]

Favier Shoo Vaibhav Trivedi Santosh Kumar Emilie Jolivet Technology & Market Analyst Sr. Technology & Market Analyst Principal Analyst Division Director Semiconductor & Software

Experience: Experience: Experience Experience: 8 years in Technology, Packaging and 17 years in Emerging Semiconductors and 15 years in semiconductor industry 12 years in semiconductor industry Manufacturing Devices

At Yole: At Yole: At Yole: At Yole: Packaging, Materials & Manufacturing Packaging, Assembly and Substrates Is Principal analyst for the division and Manages Semiconductor and Software team analyst in packaging, assembly and substrates

Previous companies: Previous companies: Previous companies Previous companies: Applied Materials, REC Amkor, Intel MK Electron, CCI Inc EV Group, Solarforce, Freescale

Education: Education: Education: Education: Bachelor in Materials Engineering (Hons) MBA M.Sc in Materials Science and Engineering, MBA Minor in Entrepreneurship M.Sc in Materials Science and Engineering Electronics Packaging M.Sc in Electronic Materials

ADI, AMD , Amkor, Annapurna/Amazon, ARM, ASE, Atmel, Broadcom/Avago, Broadpak, CEA-Leti, Cerebras, Cisco, Cray , Cypress, eSilicon, Facebook, Fraunhofer IZM, Freescale, Fujitsu, GlobalFoundries, Gloway, Google, Hitachi, HLMC, Huawei, Ibiden, IBM, IME, IMEC, Infineon, Intel, JCET, Juniper Networks, Kyocera, Micron, Mitsubishi, Nhanced, Nvidia, ON Semiconductor, Oracle, Panasonic, PTI, Qualcomm, Rambus, Renesas, Rohm, Samsung, Sanyo, SEMCO, Sharp, Shinko, SK hynix, Skywater, SMIC, Sony, SPIL, STMicroelectronics, Tesla, Tezzaron, TI, Toshiba, TSMC, UMC, Xilinx, Xperi, YMTC

Number of Players with leading-edge manufacturing capabilities 26 ADI 25 AMD Atmel Cypress Freescale Fujitsu Moore’s law has guided 20 the global semiconductor Hitachi 18 industry for past decades HLMC (since 1965), improving IBM AMD both performance and Infineon Cypress cost through node scaling. Intel Freescale 14 14 15 Mitsubishi Fujitsu After 2002 (130nm), the ON IBM Fujitsu Fujitsu industry has been Panasonic Infineon GF GF consolidating extensively. Renesas Intel HLMC HLMC Limitations in scaling has 10 disrupted companies 10 Rohm Panasonic IBM IBM competing in this Samsung Renesas Intel Intel GF Only 3 players left business. Sanyo Samsung Panasonic Panasonic HLMC Number of Number Playersof 7 [2020] Sharp Sharp Renesas Renesas IBM 6 Presently, it is an SMIC SMIC Samsung Samsung Intel GF oligopoly market, with a handful of key players 5 Sony Sony SMIC SMIC Panasonic HLMC GF remaining. STM STM STM STM Samsung IBM Intel 3 3 TI TI TI TI SMIC Intel Samsung 2 Toshiba Toshiba Toshiba Toshiba STM Samsung SMIC Intel Intel TSMC TSMC TSMC TSMC TSMC SMIC TSMC Samsung Samsung ? 0 UMC UMC UMC UMC UMC TSMC UMC TSMC TSMC ? 130nm 90nm 65nm 45nm/40nm 32nm/28nm 22nm/20nm 16nm/14nm 10nm 7nm 5nm/3nm 2002-2003 2004-2006 2006-2008 2008-2012 2010-2012 2012-2014 2014-2016 2017-2019 2020-2022 2023-2025 Technology Node [Moore’s Law*] Year * Moore’s law states that the number of transistors in an integrated circuit chips doubles every 2 years Data referenced from Intel and WikiChip High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 10 HIGH-END PERFORMANCE PACKAGING DEFINITION Yole Développement’s definition of high-end performance packaging

Presently, there is no acknowledged mainstream definition for high–end performance packaging within IO Density vs IO Pitch (Log Scale) semiconductor industry. 131072/mm2 If distinct advanced packaging technologies, including High-End performance Packaging flip-chip, embedded die, 2.5D Si interposers, 3D-IC, 65536/mm2 fan-in, fan-out and hybrid bonding, are considered as high-end performance packaging, then this will be 32768/mm2 Hybrid Bonding: Next-Gen over generalizing high–end performance packaging. 16384/mm2 This is because not all advanced packaging technology is high performing. For example, flip-chip 8192/mm2 and fan-out packaging can exist both in high-end and 4096/mm2 Hybrid Bonding: Bumpless low-end applications. Flip-Chip: µbumps/Cu Pillars In order to prevent such confusion, Yole 2048/mm2 Développement clearly focuses and defines high-end performance packaging based on IO density and IO 1024/mm2 Embedded Si bridge: µbumps pitch. 512/mm2 Fan-Out (HD FO)

LogScale Flip-Chip: µbumps/Cu Pillars 256/mm2 Flip-Chip: µbumps/Cu Pillars --- DEFINITION --- 128/mm2 Flip Chip: Bump I/O Density* ( I/O per mm2) I/O ( per I/ODensity* 64/mm2 High-end performance packaging is defined as a 2.5D Si Interposer forefront packaging technology, which value- 32/mm2 adds device performance with high IO Density 16/mm2 Fan-Out (Core) Fan-In Fan-Out (UHD FO) 2 (≥16/mm ) and fine IO Pitch (≤130µm) 8/mm2 4/mm2 IC Substrate: BGA Balls 2/mm2 --- TERMINOLOGY --- IC Substrate: BGA Balls Flip Chip: QFN 1/mm2 In this report, “High-end Performance 1024,0µm 512,0µm 256,0µm 128,0µm 64,0µm 32,0µm 16,0µm 8,0µm 4,0µm 2,0µm 1,0µm 0,5µm Packaging” will be used interchangeable with IO Pitch (µm) “High-end Packaging” and “HEP” abbreviation Log Scale *I/O Density refers to total number of IOs per package platform area Plot is generated based Yole Développement’s and System Plus Consulting’s database, with reference to industry average value and assumptions.

Microprocessor performance (FLOPS) Mfg Cost (¢ per Million Transistors ) Design Cost ($M)

107 16 1,000 Transistor (k) 90nm 10¢/MTx 3nm $550M (?) 106 8 500 Single thread performance 7nm $300M 105 4 250

Frequency (MHz) 28nm 2.5¢/MTx 10nm $174M 104 2 125 Moore’s Law 16nm $106M 103 1 62 22nm $70M Typical power (W) 28nm $51M 7nm 0.5¢/MTx (?) 40nm $38M 102 0.5 30 Number of cores 90nm $15M 101 0.25 15

180nm 90nm 45nm 28nm 14nm 7nm 35Å 180nm 90nm 45nm 28nm 14nm 7nm 35Å 180nm 90nm 45nm 28nm 14nm 7nm 35Å

2002 2006 2010 2014 2018 2022 2002 2006 2010 2014 2018 2022 2002 2006 2010 2014 2018 2022

Clearly, transistor counts still follow the guidance of Moore’s Law. With the upcoming introduction of 7nm process nodes it is reasonable to assume that manufacturers will stay on the course for transistor counts growth for the next few years. In parallel, Manufacturing cost is still benefitting from Moore’s Law. However, the design cost has risen many times (e.g. 3nm design cost ~35-40X compared to 90nm) and monolithic SoC manufacturing has become extremely complex, leading to an increase in time-to-market. Moore’s Law is still alive but reaching technical limitations and losing its cost reduction appeal with increasingly heavy design cost. There are still demands to innovate for better performance which can justify the investment for the top manufacturers. However, it has become more challenging for these leading-edge manufacturers to generate revenues out of advanced nodes.

In this report, we will be using the term “slow down” when describing the status of Moore’s law

2.5D & 3D integration

High-end Mid/Low-end segment segment

HPC Networking Gaming Sensing Lighting

Data mining Artificial Super Data centers, Switch / MEMS & (crypto & CIS LED Intelligence computers hyper scale Router sensors other data)

High-end segment is defined as the market where an application is less sensitive to Mid/Low-end segment is defined by a good the cost, but requires reduced footprint in addition to high performance & reliability balance between cost sensitivity & performance

2019 2025

0.8% 0.1% Automotive Defense & & Mobility Aerospace 0.1% Defense & 11.6% Aerospace Mobile & Consumer

CAGR2019-2025 =32% $0.8 B $4.7 B

88.2% 58.4% 40.8% Telecom & Telecom & Mobile & Infrastructure Infrastructure Consumer

High-End Packaging Revenue ($M): End-Market

6000,0

5000,0 The high-end performance packaging 4000,0 market is expected to reach $4.7B by 3000,0 2025 from $884M in 2019, ($M) Revenue with a CAGR 2000,0 of 32%.

1000,0

0,0 2019 2020 2021 2022 2023 2024 2025 CAGR Total 884,8 1179,3 2182,1 2800,6 3284,2 3886,6 4781,9 32%

High-End Packages (M Units): End-Market 1600,0

1400,0

The 1200,0 production units of high- 1000,0 end packaging will rise at a CAGR of 38% 800,0 from 204.5M

Units in 2019 600,0 to 1409.2M Packages Units)No. of (M Units by 2025. 400,0

200,0

0,0 2019 2020 2021 2022 2023 2024 2025 CAGR Total 204,5 289,7 581,1 806,8 968,5 1156,0 1409,2 38,0%

Final assembly: OSAT | Foundry | IDM The final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by OSAT and Foundry (possibly IDM).

HBM xPU supplier: Foundry | IDM HBM packaging: IDM | Memory supplier The CPU or GPU die is manufactured by wafer The HBM stack (memory dies, logic die) is made by a foundry. xPU Memory manufacturer.

2.5D interposer: Foundry | IDM The GPU die is manufactured by wafer 2.5D INTERPOSER foundry. IC substrate: Substrate supplier IC Substrate The PCB package substrate is made by a substrate maker.

PCB Board

Yole Développement, 2020 FPGA Virtex Ultrascale + 16nm

FPGA DDR4 3D 128GB GPU Fiji POST FX10

GPU Pascal 100

2011 2014 2015 2016 2017 2018 2019 2020 ≥2021*

NPU on Technology interposer

3D/2.5D TSV DDR4 3D 128GB EMIB DDR4 3D 64GB Xeon Phi processor Co-EMIB based on Knight Landing processor Hybrid bonding

NEW Newly Added in 2020’s Report

Package design Interposer Chips supplier

xPU supplier Substrate Systems

Memory Packaging End-customers supplier

Package End- xPU Memory Interposer Substrate Packaging Chips Systems design customers

GPU HBM2 Interposer Substrate

Global Samsung UMC Ibiden foundries

14nm node Korea Taiwan Japan • AMD is willing to switch to 7nm node GPU’s. They announced the first 7nm GPU in October 2018. • AMD will switch from Global foundries to SPIL Taiwan  CoW chip last process TSMC to manufacture their 7nm GPUs as Global foundries halted the development of this advanced node.

High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 23 PACKAGING SUPPLY CHAIN ANALYSIS Go “head-to-head” or “along” with the Big Guys before the ship sails? IDM/Foundry

High-End Packaging

OSAT/Substrate

>>10,000 Hybrid Bonding: bump-less

Embedded Si bridge

300

) 2 3D stacked memories: TSV, micro-bumps 100

2.5D interposers

20 I/O Density* ( I/O per per ( mmI/OI/O Density*

UHD FO

300 200 100 50 <5 IO Pitch (µm)

Note: The data corresponding to the year 2020 is not complete More than 1,400 patents and patent applications since patent grouped in more than 400 patent families* search was done in Sep 2020. related to 3D SoC have been published worldwide

Since 2014, strong acceleration of TSMC

patenting activity * *

2011, acceleration of the patenting activity

families driven by image sensor applications

of patent patent of

(inventions) Number

2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 1st publication year

* A patent family is a set of patents filed in multiple countries to protect a single invention by a common inventor(s). A first application is made in one country – the priority country – and is then extended to other countries.

Die-on-IC 3D memory CIS (mainly memory-on-IC) (memory-on-memory)

The following table shows the main applications described in players patents. Segmentation does not take the players’ market position into account in this table. High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 27 2.5D INTERPOSER: INTEL Intel’s Foveros in Samsung Galaxy Book S (1/2)

Samsung Galaxy Book S Samsung Galaxy Book S Teardown PCB Board Intel Core i5-L16G7 3D Package

Cross Section (Optical View) of Intel Core i5-L16G7 3D package

Active Foveros

TIMELINE ≤2019 2020* 2021 2022 2023 2024 2025

TYPES OF YMTC Periphery + Array TECHNOLOGIES X-Stacking Hybrid Bonding

Intel HBM+GPU Embedded Si bridge Kaby Lake-G HPC (x)PU in Servers TSV, Micro-bumps Intel FPGA TSMC & Intel – 3D SoC Stratix 10 Intel FPGA + Chiplets 2.5D Interposers Agilex UHD FO NVidia GPU Interposer HBM2E A100

Stacked DRAM Samsung HBM 3DS Flarebolt

Google (x)PU Intel Exascale GPU - HPC Samsung HBM2E TPU V3 Ponte Vecchio: Co-EMIB Flashbolt Intel CPU + Active Interposer

I/O DENSITY I/O Intel Lakefield Foveros Core i5-L16G7

AMD GPU NVidia GPU Intel (x)PU Ethernet Switch Xilinx FPGA Vega Frontier Pascal 100 Broadcom (x)PU + HBM Tofino2 Virtex Ultrascale Jericho2 HPCs potentially for Tesla and Cerebras TSMC inFO_SoW HiSilicon CPU (Storage) Hi1610 (Now known as Kunpeng)

* From 2020 onwards, applications/technologies are presumed based on interviews with industry players and research. Non-exhaustive list of applications/technologies High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 29 TSMC TSMC-SoIC™

Monolithic SoC die TSMC’s SoIC Re-integration of partitioned SoC dies through stacking with core circuits chip

Source: TSMC Source: TSMC

TSMC’s SoIC is one of the key technology pillars which provides front-end, 3D inter-chip (3D IC) stacking by re- integrating partitioned dies from a single monolithic System on Chip (SoC). This technology advance towards the field of heterogeneous chiplets integration with reduced size, increased performance. TSMC-SoIC service platform meets the ever-increasing compute, bandwidth and latency requirements in cloud, network and edge applications. SoIC is applicable for both D2W and W2W schemes. Such dual scheme provides superb design flexibility in mixing and matching different chip functions, sizes and technology nodes. This also integrates active and passive chips into a new integrated-SoC system, which is electrically identical to native SoC, to achieve better form factor and performance. TSMC expects the resulting integrated chip outperforms the original SoC in system performance.

Latest technical breakthrough in 2020: Interposer size has been increased in the past few years to extend the technology envelope of CoWoS, from 800mm2 to 1200mm2 In 2020, TSMC and Broadcom have collaborated to enhance Chip-on- Wafer-on-Substrate (CoWoS) platform to support the industry’s first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC’s next- Source: TSMC CoWoS Production At Full Capacity As Demand Skyrockets – Nvidia, generation five-nanometer (N5) process technology. AMD, And More Trying To Get Their Hands-On Interposers. [Online]. Available: https://wccftech.com/tsmc-cowos-production-at-full-capacity-as-demand-skyrockets- nvidia-amd-and-more-trying-to-get-their-hands-on-interposers/ [Accessed: 24-Sep- 2020]. This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7x faster than TSMC’s previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory- intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes. Through the experience of multiple generations of development of the CoWoS platform, TSMC innovated and developed a unique mask-stitching process enabling expansion beyond full reticle size, to bring this enhancement to volume production. In this TSMC and Broadcom CoWoS platform collaboration, Broadcom defined the complex top-die, interposer and HBM configuration while TSMC developed the robust manufacturing process to maximize yield and performance and meet the unique challenges of the 2X reticle size interposer.

Novel Approach: FE + BE Integration into a single SoC-like chip

Source: “Ultra High Density SoIC with Sub-micron Bond Pitch,” 2020 IEEE 70th Electronic Components and Source: “System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration,” 2019 IEEE 69th Technology Conference (ECTC) Electronic Components and Technology Conference (ECTC)

TSMC’s SoIC enabling technology combines the Front-End + Back-End holistic An SoIC integrated chip not only looks just SoC but also behaves like an 3D heterogeneous integration. Such approach allows advantages to best SoC in every aspect in terms of electrical and mechanical integrity. It can optimized system PPAC for More Moore and More-Than-Moore. then be assembled using conventional packages or new advanced Such partition-reintegration is using a chip-to-chip interconnection with both packaging. For 2.5D interposer, for example, TSMC’s CoWoS or Fan-Out horizontal line/space and vertical bond pitch equivalent to global layers of Cu Packaging, for example, TSMC’s InFO. back-end-of-line (BEOL) interconnect. Front-End 3D SoIC can mix-and-match with Back-End 3D InFO/CoWoS This is an innovative wafer level Front-End 3DIC chip stacking platform. to gain best performance and cost benefits, like a "3Dx3D" system-level solution.

Second-generation EMIB • High-density interconnect at lower cost compared to Si-interposer • Flexible chip combination and reuse across different nodes • Disaggregated transceiver tiles and HBM memory Source: Intel

Enables monolithic fabric across full family Fabric ease of use while delivering multi-die heterogenous compute

Source: Intel

Source: Intel Source: Intel

This will be Intel’s first ‘exascale class’ graphics solution and is clearly using both chiplet technology (based on 7nm) and Foveros/die stacking packaging methods. Ponte Vecchio will also use Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology, joining chiplets together. Pulling all the chips into a single package is fine, meanwhile GPU-to-GPU communication will occur through a Compute eXpress Link (CXL) interface.

At Intel Architecture Day 2020, one of the highlights is hybrid bonding being investigated for Intel’s future…

“…This new technology enables very aggressive bump pitches of 10 microns and below, delivering much higher interconnect density and bandwidth, along with lower power…”

Source: Intel’s Newsroom. [Online]. Available: https://newsroom.intel.com/press-kits/architecture-day-2020/#gs.gcljq6 [Accessed: 23-Sep-2020].

Foveros: • 2.5D Si interposers • TSV • Face-to-Face (F2F) bonding

Source: Intel Architecture Day 2020 High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 36 SAMSUNG’S X-CUBE 'X-Cube’ is the industry-first 3D SRAM-logic working silicon at 7nm

In 2020, Samsung announces the immediate availability of its Silicon-proven 3D IC Technology, eXtended-Cube (X-Cube), for high-performance applications in mobile, wearable and HPC devices.

Typical Package 3D IC Package X-Cube 2D (Side by Side) 3D (Stacked) SRAM

SRAM

Logic Logic SRAM

Logic

Source: Samsung Source: Samsung The X-Cube is built on 7nm uses TSV technology to stack SRAM on top of a logic die, freeing up space to pack more memory into a smaller footprint. Enabled by 3D TSV integration, the ultra-thin package design features significantly shorter signal paths between the dies for maximized data transfer speed and energy efficiency. Desired specifications of memory bandwidth and density can be scaled vertically.

Samsung’s new HBM2E (commercially known as the Flashbolt) “E” stands for Evolutionary

Advantages of HBM2E over HBM2 • 33% better performance over HBM2 • Doubling the density to 16 gigabits per die. • DRAM transfer speeds per pin can reach 3.2 Gbps • Single Package capable of 210 GB/s and 16GB of capacity • Positioned for Al and ML applications

2.5D Integration (D2W) 3D Stack Memories (D2D) Source: Xperi

Source: Xperi

Source: Xperi D2W and D2D hybrid bonding applications are 3D memory stacking and 2.5D/3D high-performance computing • A single stacking solution for all DRAM products: 3DS, HBM2, HBM3, and beyond • Enables wide range, coarse interconnect pitch to 1µm pitch for next-generation DRAM and 2.5D/3D logic and memory integration • Allows integration of same or different die sizes • Interconnect layers add no stand-off height, requires no copper pillars or under-fill • Since no copper pillars or under-fill between the die in the stack, it enables better thermal performance

The periphery circuits Independent Wafers processing W2W Hybring Bonding The two wafers are which handle data I/O as connected electrically well as memory cell through billions of metal operations are processed VIAs (Vertical Interconnect on a separate “Periphery Accesses) that are formed Wafer” using the logic simultaneously across the technology node that whole wafer in one process enables the desired I/O step speed and functions.

Wafer Flipped Over Xtacking® Technology Flip-Chip could be done This modular approach also onto 3D NAND array opens possibilities for wafer. Periphery Wafer customized NAND flash CMOS wafer can be flipped solutions by the over to align the metal incorporation of innovative interconnections with functionalities in the Array NAND wafer. periphery.

Hybrid bonding is defined as a permanent bond that combines a dielectric bond with embedded metal to form interconnections It’s become known industry wide as direct bond interconnect or Direct Bond Interconnect (DBI®) from Xperi.

The term “Hybrid”, in this context, comes from the fact the interface has two types of co-planar materials, metal pads and dielectric surface.

Due to high-end performance application demands, industry players are now pursuing higher level of interconnect density. At system-level, three dimensional (3D) packaging has become a crucial platform to achieve this. Cu redistribution lines (RDLs) and Cu via are adopted for interconnects between chips. In addition, solder microbumps and through silicon vias (TSVs) are used as the vertical interconnects between the stacked chips. For partitioned 3D SoC to be packaged, the dimension of the interconnects is expected to drive towards 10 μm and beyond. However, there are some manufacturing limitation for solder bumps with the shrinkage of bump pitch. Bridging with neighbor bumps, and full intermetallic compounds joints are prone to necking or shorting, especially if bump pitch shrinks below 10 μm. In high-performance application, the interconnect IO pitch requirement is now shrinking below what can be achieved with Flip-Chip solder joints. Among the different packaging technologies being developed for heterogeneous integration of ICs, wafer-to-wafer (W2W) hybrid bonding is attracting interest due to its high integration density capability, allowing μm and sub-μm scale of interconnect pitches. It offers a z-axis direction of integration, enabling new 3D SoC architectures to benefit from improved interconnect density and reducing overall product x-y footprint. Therefore, hybrid bonding emerges as the solution for next-generation fine-pitch interconnects.

High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 42 YOLE GROUP OF COMPANIES RELATED REPORTS Yole Développement (x)PU: High-End CPU and GPU Status of the Advanced for Datacenter Applications Packaging Industry 2020 2020

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