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High-End Performance Packaging 2020 From Technologies to Markets High-End Performance Packaging: 3D/2.5D Integration 2020 Market and Technology Report Sample © 2020 TABLE OF CONTENTS Part 1/2 Table of contents 2 o Package ASP split by technology 85 Scope of report 4 o Market value split by technology 88 Report methodologies & definitions 6 o 3D SoC Key features of this report 5 o 3D stacked memory About the author 7 o 2.5D interposers Yole Group of companies related reports 9 o UHD FO Glossaries 11 o Embedded Si bridge Companies cited in this report 12 o Chapter conclusion 94 3-Page summary 13 Market trends 96 Executive summary 17 o Cloud & edge computing 97 Context 66 o Cloud computing and networking 103 o Semiconductor industry – players pursuing Moore’s law 67 o High-Performance Computing (HPC) 111 o High-end performance packaging definition 71 o Artificial intelligence for autonomous vehicles 119 o Scope of report 72 o Chapter conclusion 125 o High-end performance packaging market segment 73 Commercialized products and its supply chain 127 o High-end performance packaging introduction 74 o Product launches 130 Market forecasts 75 o 3D stacked memories o Market Revenue 76 o (x)PU o Total market revenue o GPU for HPC o Split by end-market o Supply chain for high-end performance packaging 156 o Split by technology o Global mapping of high-end packaging o Market Units 80 o Global mapping based on technology o Total market units o Supply chain for high-end packaging products o Split by end-market o Latest progress of key players 175 o Split by technology High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 2 TABLE OF CONTENTS Part 2/2 o Supply chain analysis in high-end performance packaging 188 o TSV process 254 o Packaging supply chain analysis o 3D stacked memory 260 o Analyst’s point of view on supply chain 192 o HBM o It is a new battlefield for technology supremacy o 3D Stacking (3DS) DRAM o Impact within big players o 3D SRAM o Impact on OSATs & substrate suppliers o 3D NAND o What is TSMC strategy exactly? o Others: HMC, DRAM stacked memory o Who are the winners/losers? o 2.5D interposer 284 o Chapter Conclusion 201 o Ultra-high-density Fan-Out (UHD FO) 295 IP Analysis: 3D SoC – hybrid bonding 203 o Embedded Si bridge 301 o Patent overview 204 o Other high-end packaging technologies 310 o Supply chain IP position (examples) 208 o Chapter conclusion 315 o Chapter conclusion 212 Report conclusion 318 Technology trends 214 Appendix 320 o Technology roadmap 215 o OSATs high-end packaging technologies 321 o Semiconductor packaging roadmap Yole corporate presentation 330 o Advanced packaging roadmap o High-end packaging roadmap: iO pitch vs IO density o High-end packaging roadmap: application-technology o Key player’s technology roadmap 221 o Short description of chiplet 227 o 3D SoC 230 o Hybrid bonding 234 o Key players’ technologies: hybrid bonding for 3D SoC High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 3 SCOPE OF THE REPORT The main objectives of this report are: • To identify and describe which technologies can be classified as ‘high-end performance packaging’ • To define high-end performance packaging • To analyze key market drivers, benefits and challenges of high-end performance packaging by application • To describe the different existing technologies, their trends and roadmaps • To analyze the supply chain and high-end performance packaging landscape • To update the business status of high-end performance packaging technology markets • To provide a market forecast for the coming years, and estimate future trends Fan-out packaging markets are studied from the following angles: • Top-down based on end-systems demand Are your needs • Market valuations based on top-down and bottom-up models beyond this • Market shares based on production projections report’s scope? • Supply value chain analysis Contact us for a custom: • State-of-the-art technologies and trends • End-user application adoptions High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 4 KEY FEATURES OF REPORT • Yole Développement’s definition of high-end performance packaging • High-end performance packaging market segmentation • Market valuation in terms of package units, revenue and wafer production volumes • Market valuation of key high-end packaging technologies • Includes COVID-19 impact in all forecasts • High-end performance packaging market trends: end-system drivers • Commercialization of high-end performance packaging products • Global mapping of high-end performance packaging supply chain • Supply value chain analysis in high-end performance packaging • Application-technology roadmap of high-end performance packaging • Key Player’s technology roadmap of high-end performance packaging : Intel,TSMC and Samsung • IP Analysis: 3D SoC – hybrid bonding High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 5 REPORT METHODOLOGIES & DEFINITIONS Yole Développement’s market forecast model is based on the matching of several sources: Preexisting information Market Volume (in Munits) ASP (in $) Revenue (in $M) Information aggregation High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 6 ABOUT THE AUTHOR Biographie & contact Favier SHOO Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting reports. During 7 years at Applied Materials as a Customer Application Technologist in the advanced packaging marketspace, Favier developed an in-depth understanding of the supply chain and core business values. As an acknowledged expert in this field, Favier has provided training and held numerous technical review sessions with industry players. In addition, he has obtained 2 patents. Prior to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity. Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans. Favier holds a Bachelor’s in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). [email protected] High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 7 ABOUT THE TEAM Packaging, assembly and substrate Favier Shoo Vaibhav Trivedi Santosh Kumar Emilie Jolivet Technology & Market Analyst Sr. Technology & Market Analyst Principal Analyst Division Director Semiconductor & Software Experience: Experience: Experience Experience: 8 years in Technology, Packaging and 17 years in Emerging Semiconductors and 15 years in semiconductor industry 12 years in semiconductor industry Manufacturing Devices At Yole: At Yole: At Yole: At Yole: Packaging, Materials & Manufacturing Packaging, Assembly and Substrates Is Principal analyst for the division and Manages Semiconductor and Software team analyst in packaging, assembly and substrates Previous companies: Previous companies: Previous companies Previous companies: Applied Materials, REC Amkor, Intel MK Electron, CCI Inc EV Group, Solarforce, Freescale Education: Education: Education: Education: Bachelor in Materials Engineering (Hons) MBA M.Sc in Materials Science and Engineering, MBA Minor in Entrepreneurship M.Sc in Materials Science and Engineering Electronics Packaging M.Sc in Electronic Materials High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 8 COMPANIES CITED IN THIS REPORT ADI, AMD , Amkor, Annapurna/Amazon, ARM, ASE, Atmel, Broadcom/Avago, Broadpak, CEA-Leti, Cerebras, Cisco, Cray , Cypress, eSilicon, Facebook, Fraunhofer IZM, Freescale, Fujitsu, GlobalFoundries, Gloway, Google, Hitachi, HLMC, Huawei, Ibiden, IBM, IME, IMEC, Infineon, Intel, JCET, Juniper Networks, Kyocera, Micron, Mitsubishi, Nhanced, Nvidia, ON Semiconductor, Oracle, Panasonic, PTI, Qualcomm, Rambus, Renesas, Rohm, Samsung, Sanyo, SEMCO, Sharp, Shinko, SK hynix, Skywater, SMIC, Sony, SPIL, STMicroelectronics, Tesla, Tezzaron, TI, Toshiba, TSMC, UMC, Xilinx, Xperi, YMTC High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020 9 SEMICONDUCTOR INDUSTRY Chronological order of players pursuing Moore’s Law Number of Players with leading-edge manufacturing capabilities 26 ADI 25 AMD Atmel Cypress Freescale Fujitsu Moore’s law has guided 20 the global semiconductor Hitachi 18 industry for past decades HLMC (since 1965), improving IBM AMD both performance and Infineon Cypress cost through node scaling. Intel Freescale 14 14 15 Mitsubishi Fujitsu After 2002 (130nm), the ON IBM Fujitsu Fujitsu industry has been Panasonic Infineon GF GF consolidating extensively. Renesas Intel HLMC HLMC Limitations in scaling has 10 disrupted companies 10 Rohm Panasonic IBM IBM competing in this Samsung Renesas Intel Intel GF Only 3 players left business. Sanyo Samsung Panasonic Panasonic HLMC Number of Number Playersof 7 [2020] Sharp Sharp Renesas Renesas IBM 6 Presently, it is an SMIC SMIC Samsung Samsung Intel GF oligopoly market, with a handful of key players 5 Sony Sony SMIC SMIC Panasonic HLMC GF remaining. STM STM STM STM Samsung IBM Intel 3 3 TI TI TI TI SMIC Intel Samsung 2 Toshiba Toshiba Toshiba Toshiba STM Samsung SMIC Intel Intel TSMC TSMC TSMC TSMC TSMC SMIC TSMC Samsung Samsung ? 0 UMC UMC UMC UMC UMC TSMC UMC
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