DOCSLIB.ORG

Sony IMX400 Tri-Stacked Image Sensor First Stacked CIS with Logic, Memory and Sensing Die IMAGING Report by Stéphane ELISABETH July 2017

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Sony IMX400 Tri-Stacked Image Sensor First Stacked CIS with Logic, Memory and Sensing Die IMAGING Report by Stéphane ELISABETH July 2017 Sony IMX400 Tri-Stacked Image Sensor First stacked CIS with Logic, Memory and sensing die IMAGING report by Stéphane ELISABETH July 2017 ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 1 Table of Contents Overview / Introduction 3 Manufacturing Process Flow 93 o Executive Summary o Global Overview o Reverse Costing Methodology o DRAM Front-End Process Company Profile 6 o DRAM Wafer Fabrication Unit o Sony o Logic Front-End Process o CIS Market Forecast o Logic Wafer Fabrication Unit o New generation of CIS? o Pixel Array Front-End Process o Sony XZs Teardown o CIS Wafer Fabrication Unit Physical Analysis 14 o DRAM/Logic Circuit Bonding Process Flow o Pixel Circuit Process Flow o Synthesis of the Physical Analysis o Pixel Array/DRAM/Logic Circuit Bonding Process Flow o Physical Analysis Methodology o Optical Process Flow o Module 17 Cost Analysis 105 Module Views & Dimensions o Synthesis of the cost analysis Module Opening: o Yields Explanation & Hypotheses Lenses, AF driver & Hall sensor, Plastic Filter o Circuits Wafer 110 Module Opening: Wire Bonding, BSI, TSVs Process Logic Circuit Front-End Cost Module Cross-Section : DRAM Circuit Front-End Cost Plastic Filter, Wire Bonding, PCB, FOV, Adhesives, FOV Pixel Array Circuit Front-End Cost o CIS Die 46 o Bonded Wafer 113 Pads, Pixels, Active Area Overview BSI & TSVs Front-End Cost Die View & Dimensions BSI & TSVs Front-End Cost per process steps Delayering: Color Filter & Microlenses Front-End Cost Pixel Array, DRAM, Logic Total Front-End Cost Cross-Section: CIS Back-End 0 : Probe Test & Dicing Die Bonding, TSVs, Die Process CIS Wafer & Die Cost Process Characteristics Estimated Price Analysis 121 Physical Comparison 87 Company services 125 o History of Sony’s CIS Module, Die area, PDAF, Pixel Area, TSVs ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 2 Executive Summary Overview / Introduction o Executive Summary • This full reverse costing study has been conducted to provide insight on technology data, manufacturing o Reverse Costing Methodology cost and selling price of the Sony IMX400. Company Profile & Supply Chain Physical Analysis • This innovative CIS will be the next generation from Sony. The CIS included a 22 Mpixels array, a 1Gb Physical Comparison DRAM die and a Digital Signal Processing on the same die footprint. This is the first tri-layers stacked CIS Manufacturing Process Flow that we can found on the market. In this configuration, Sony can provide a fast readout image sensor with no distortion when shooting fast-moving object thanks to the high capacity DRAM between the Pixel Array Cost Analysis circuit and the DSP circuit. • Using the Sony’s Exmor-RS and the Xperi’s Zibond technology, Sony managed to integrate the three dies in a single thin, small and cost-effective die sensor. Surprisingly, the die sensor a unique sort of TSV with multiple level to interconnected the dies. • This report includes a complete analysis of the Camera module from the Sony Xperia™ XZs, featuring camera module disassembly and die analyses, processes and cross-section. It also includes a comparison with Samsung Galaxy S7, Apple iPhone 7 Plus, and Huawei P9 telephoto camera modules. At the CIS level, it compares the IMX260, the IMX286, and the latest custom CIS for Apple from Sony’s portfolio. Finally, it contains a complete cost analysis and a selling price estimation of the CIS die. ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 3 Sony XZs Teardown Overview / Introduction Company Profile & Supply Chain o Sony Rear camera o Market Forecast Module o Next generation of CIS? o Sony XZs Teardown Physical Analysis Physical Comparison Manufacturing Process Flow Sony XZs Opened view Cost Analysis Front Camera Ambient Light Sensor Sony XZs Top Flex PCB – Bottom View ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 4 Synthesis of the Physical Analysis Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 5 Physical Analysis Methodology Overview / Introduction • Module is analyzed and measured. Company Profile & Supply Chain Physical Analysis o Synthesis • The module is opened to get overall dies data: dimensions, main characteristics, device markings. o Module o Pictures of selected area are made in order to understand the connections of the CIS. o Module Cross-Section o CIS Die o Cross section of Module to measure thicknesses and understand the assembly o CIS Cross-Section Physical Comparison • The CIS is separated to get overall die data: dimensions, main blocks, pad number and pin out, die marking. Manufacturing Process Flow o Removal of metal layers (step by step) to identify the dies and measure the minimum dimensions. Cost Analysis o Pictures of selected areas to identify the nature of the transistors. o SEM photographs to measure the transistors dimensions. ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 6 Module with Flex View & Dimensions Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 7 Module Opening – Plastic Filter Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 8 Module Cross-Section – Lenses Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 9 CIS Die – View & Dimensions Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 10 CIS Die – DRAM Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 11 CIS Die Cross-Section Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 12 CIS Die Cross-Section – Pixel Array Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 13 CIS Die Cross-Section – Pixel Array/DRAM Bonding Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 14 CIS Die Cross-Section – TSVs DRAM Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 15 CIS Die Cross-Section – TSVs Recap. Overview / Introduction Company Profile & Supply Chain Physical Analysis o Synthesis o Module o Module Cross-Section o CIS Die o CIS Cross-Section Physical Comparison Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 16 History of Sony’s CIS – Module Overview / Introduction Company Profile & Supply Chain Physical Analysis Physical Comparison o Module o Die Area o PDAF o Pixel Area o TSVs Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 17 History of Sony’s CIS – TSVs Overview / Introduction Company Profile & Supply Chain Physical Analysis Physical Comparison o Module o Die Area o PDAF o Pixel Area o TSVs Manufacturing Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 18 Global Overview Overview / Introduction Company Profile & Supply Chain Physical Analysis Physical Comparison Manufacturing Process Flow o Global Overview o Wafers Front-End Process o Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 19 DRAM/Logic Circuit Bonding Process Flow Overview / Introduction Company Profile & Supply Chain Physical Analysis Physical Comparison Manufacturing Process Flow o Global Overview o Wafers Front-End Process o Process Flow Cost Analysis ©2017 System Plus Consulting | Sony IMX400 – Tri-layer Stacked CIS 20 Pixel Array/DRAM/Logic Circuit Bonding Process Flow Overview / Introduction Company Profile & Supply Chain Physical Analysis Physical Comparison Manufacturing Process Flow o Global Overview
Load more

Recommended publications
  • Ar Vr Uhd Ip
    Issue No. 51 DVBSCENE March 2018 Delivering the Digital Standard www.dvb.org Promotions & Communication Module broadband Television Satellite Beam Hopping tion DVB World Hybrid casting a - t Emergency Warning System -based e T n L embers Targeted Advertising t il n F Second Generation M o TM Commercial Module I T 8k Broadcast VC DVB-C2 A - impleme Augmented Reality CI-Plus Bit-Rate M e elopme C r Steering Board w 25 Years v a a V VC ABR Multicast e implementation t>IP w A t s L f D T ’ a Technical Module e Satellite k e echnology ta so r c r S 4k T s Meetings ebinars a o y IP oo HbbTV OTT a V bitmap w D M W ansponders e HEVC t r t c T e Displ Terrestrial erien N TM-AVC vi in AR p Seminars r e S DVB IP DVB-T2 ome UHD onsensus Liaisons V C H k oding T r - ts C y of tion tion Transmission internet y 2018 n o a a t a QoS SMG Subtitling A os m p T w r - c y Systems eme ideo o M able t QoE t es f r C el V c ast ualtiy of Ex sics e in C T uali FTA llumin y c vi I Q h e N equi Q metadata VR HD R P ds echnology r Low latency IP oks T DVB-S2 IP cial o r Single Specication UHD Phase 2 eaming r B CS t tual Reali S Patent Pools tanda Multi DVB DASH Low latency DASH R r i S ilecasting onsumer D omme V F Consumer Electronics C STBs C Wideband SI T E Ultra High Definition Transport Stream Blue Study Mission Groups DVB-I Service Portal 05 Wideband Re-use 1 Future Forward DVB Internet TV Services CES Attention Grabbers DVB-I Client 08 Targeted Advertising DVB-I Client 10 NGA The open internet 12 Report from CM-VR including CDNs, Cable, Fiber, xDSL, DVB-I Client mobile access networks, 13 Other Realities WiFi, etc.
    [Show full text]
  • Blu-Ray Disc Association Begins Licensing
    Blu-ray Disc Association Begins Licensing For Next-Generation Broadcast Recordable Blu-ray™ Format New Recordable Format Enables Recording of Ultra HD Broadcast Content in Japanese Market LOS ANGELES – January9 2018 – The Blu-ray Disc Association (BDA) today commenced licensing of its latest expansion of the Blu-ray Disc format. The specifications for next-generation broadcast recordable Blu-ray format will allow consumers in the Japanese market to record, view and archive Ultra HD broadcast content on new BD-RE XL media, as well as on legacy BD-R and BD-RE discs. Blu-ray Disc’s large data capacity has made it a top choice for archiving personal video content. In Japan, where there are three times more Blu-ray recorders in homes than there are players, it’s widely used for recording and archiving broadcast content. According to JEITA, more than 2 million Blu-ray recorders were shipped in 2016 and a similar number is forecasted for 2017, while approximately 600,000 Blu-ray players were shipped during the same years. "Due to different business models and certain cultural aspects in Japan, Blu-ray recorder sales have outpaced player sales since the introduction of the format,” noted Victor Matsuda, Chair of BDA Global Promotions Committee. “Recording and archiving broadcast content is common in Japan and, with Ultra HD broadcast scheduled to launch there towards the end of 2018, adding Ultra HD recording capability was a given for the BDA and is an important benefit for Japanese consumers.” Highlights of the Ultra HD Blu-ray recordable specifications, which were completed in November of 2017, include: Recording and playback of Ultra HD broadcast streams at up to 100Mbps in new BD-RE XL media Recording of Ultra HD broadcast streams on legacy BD-R/BD-RE media New File system specifications for recording AV streams up to 100Mbps AACS2 recordable technology Support for HEVC and HDR (Hybrid Log Gamma) The new BD-RE-XL discs will allow for more than two hours of recording, even in the case of 100Mbps AV streams.
    [Show full text]
  • Since the Advent of Integrated Circuit Technology in 1958, the Integration Has Been Primarily Monolithic
    Opening Keynote #1 Extending Moore’s Law with Advanced Packages Abstract: Since the advent of integrated circuit technology in 1958, the integration has been primarily monolithic. Unfortunately, due to physical and economic reasons, the vast majority of analog chips, digital chips, and memory chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power, and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. Advanced packaging technologies, e.g. 3DIC, SSIT(stacked silicon Interconnect technology) etc., have been developed to extend scaling beyond the Moore’s Law to achieve higher transistor count, increased functionality and superior performance. Xilinx is the leading provider of all programmable FPGA (Field Programmable Gate Array) products. To achieve high performance, but low power and cost, Xilinx has developed an innovative SSIT technology that employs microbumps and through-silicon vias (TSVs) to integrate multiple FPGA die slices placed side-by-side on a passive silicon interposer, and successfully delivered the industry’s first 28nm homogeneous SSIT device. This technology is further developed for advanced technical nodes (20nm, 16nm and beyond) to allow integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The advance of packaging and assembly technology will be introduced, and the benefits of advanced packaging to the various products will be highlighted. Successful qualification of these products is driving the high growth in the applications e.g. cloud computing, embedded vision, industrial IOT, and 5G wireless etc.
    [Show full text]
  • Patent Landscape Shifts from M&A in the Semiconductor Industry
    ® Patent Landscape Shifts from M&A in the Semiconductor Industry George Park Great things 8 April 2021 happen when ideas prosper Property of IPValue Management Inc. – All rights reserved. The views expressed do not necessarily represent the views of IPValue. Semiconductor industry experienced a boom in M&A in the last two years Technology area of company or business Date deal Buyer Seller Deal Value unit being acquired announced Renesas Dialog Semiconductor $5.9B Internet of Things, Mixed Signal Feb-21 Qualcomm Nuvia $1.4B Custom CPU core design for servers Jan-21 AMD Xilinx $35B Programmable chips Oct-20 SK hynix Intel NAND/SSD business unit $9B NAND/SSD Oct-20 High-speed interconnect and mixed- Marvell Inphi $10B Oct-20 signal IC Nvidia ARM (owned by Softbank) $40B Processor design technology Sep-20 Analog Devices Maxim $21B Analog & mixed signal products Jul-20 AMS OSRAM €4.6B Lighting technology Dec-19 Apple Intel business unit $1B Smartphone modem Jul-19 MCUs, software, connectivity Infineon Cypress Semiconductor €9B Jun-19 components Marvell wireless connectivity NXP Semiconductors $1.76B WiFi and Bluetooth May-19 business unit ON Semiconductor Quantenna $1B WiFi Mar-19 Nvidia Mellanox $7B High performance networking technology Mar-19 Note: certain deals, including Nvidia-ARM, remain subject to governmental approval Source: IAM-Media; press releases Property of IPValue Management Inc. – All rights reserved. 2 SOXX Performance: Jan 2019 to Dec 2020 Source: Yahoo Property of IPValue Management Inc. – All rights reserved. 3 Total 2020 M&A deals in the semiconductor space has been estimated at ~$100B Source: Press releases Property of IPValue Management Inc.
    [Show full text]
  • XPERI CORPORATION (Exact Name of Registrant As Specified in Its Charter)
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, DC 20549 FORM 10-K (Mark One) ☒ ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2019 OR ☐ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 Commission File Number: 001-37956 XPERI CORPORATION (Exact Name of Registrant as Specified in Its Charter) Delaware 81-4465732 (State or Other Jurisdiction of (I.R.S. Employer Incorporation or Organization) Identification No.) 3025 Orchard Parkway, San Jose, California 95134 (Address of Principal Executive Offices) (Zip Code) (408) 321-6000 (Registrant’s Telephone Number, Including Area Code) Securities registered pursuant to Section 12(b) of the Act: Trading Title of each class Symbol(s) Name of each exchange on which registered Common Stock, par value $0.001 per share XPER The Nasdaq Global Select Market Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes ☒ No ☐ Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Securities Exchange Act. Yes ☐ No ☒ Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • Opening Keynote #1 Extending Moore's Law with Advanced
    Opening Keynote #1 Extending Moore’s Law with Advanced Packages Abstract: Since the advent of integrated circuit technology in 1958, the integration has been primarily monolithic. Unfortunately, due to physical and economic reasons, the vast majority of analog chips, digital chips, and memory chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power, and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. Advanced packaging technologies, e.g. 3DIC, SSIT(stacked silicon Interconnect technology) etc., have been developed to extend scaling beyond the Moore’s Law to achieve higher transistor count, increased functionality and superior performance. Xilinx is the leading provider of all programmable FPGA (Field Programmable Gate Array) products. To achieve high performance, but low power and cost, Xilinx has developed an innovative SSIT technology that employs microbumps and through-silicon vias (TSVs) to integrate multiple FPGA die slices placed side-by-side on a passive silicon interposer, and successfully delivered the industry’s first 28nm homogeneous SSIT device. This technology is further developed for advanced technical nodes (20nm, 16nm and beyond) to allow integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The advance of packaging and assembly technology will be introduced, and the benefits of advanced packaging to the various products will be highlighted. Successful qualification of these products is driving the high growth in the applications e.g. cloud computing, embedded vision, industrial IOT, and 5G wireless etc.
    [Show full text]
  • High-End Performance Packaging 2020
    From Technologies to Markets High-End Performance Packaging: 3D/2.5D Integration 2020 Market and Technology Report Sample © 2020 TABLE OF CONTENTS Part 1/2 Table of contents 2 o Package ASP split by technology 85 Scope of report 4 o Market value split by technology 88 Report methodologies & definitions 6 o 3D SoC Key features of this report 5 o 3D stacked memory About the author 7 o 2.5D interposers Yole Group of companies related reports 9 o UHD FO Glossaries 11 o Embedded Si bridge Companies cited in this report 12 o Chapter conclusion 94 3-Page summary 13 Market trends 96 Executive summary 17 o Cloud & edge computing 97 Context 66 o Cloud computing and networking 103 o Semiconductor industry – players pursuing Moore’s law 67 o High-Performance Computing (HPC) 111 o High-end performance packaging definition 71 o Artificial intelligence for autonomous vehicles 119 o Scope of report 72 o Chapter conclusion 125 o High-end performance packaging market segment 73 Commercialized products and its supply chain 127 o High-end performance packaging introduction 74 o Product launches 130 Market forecasts 75 o 3D stacked memories o Market Revenue 76 o (x)PU o Total market revenue o GPU for HPC o Split by end-market o Supply chain for high-end performance packaging 156 o Split by technology o Global mapping of high-end packaging o Market Units 80 o Global mapping based on technology o Total market units o Supply chain for high-end packaging products o Split by end-market o Latest progress of key players 175 o Split by technology High-end
    [Show full text]
  • Blu-Ray Disc Association Announces Specification for Next-Generation Broadcast Recordable Blu-Ray Disc™ Product Licensing to Commence in 2018
    Blu-ray Disc Association Announces Specification for Next-Generation Broadcast Recordable Blu-ray Disc™ Product Licensing to Commence in 2018 LOS ANGELES – December19, 2017 – The Blu-ray Disc Association (BDA) today announced completion of specifications for next-generation broadcast recordable Blu-ray Disc™ for the Japanese market. This is the culmination of the work of global leaders from the consumer electronics, IT and content creation industries. The next-generation broadcast recordable Blu- ray format will enable recording of Ultra HD content in the successful Japanese recordable market. Blu-ray Disc’s large data capacity has made it a top choice for archiving personal video content. Recordable Blu-ray Disc is widely used for recording and archiving broadcast content in Japan where Blu-ray recorders continue to represent almost 75% of the Blu-ray hardware market. "With 4K becoming the standard, not only for TVs, but also mobile devices and video cameras, extending recordable Blu-ray to enable Ultra HD content is a logical and very practical extension of format,” said Victor Matsuda, Chair of BDA Global Promotions Committee. “We are also anticipating that Ultra HD broadcasting will start in Japan around the end of 2018. The ability to continually expand to keep up with consumer demand for high quality experiences, remains one of Blu-ray’s greatest strengths and a primary reason for its success and longevity.” Licensing of the next-generation broadcast recordable Blu-ray format is scheduled to begin by January 2018. The BDA is working closely with industry leaders to develop the tools and processes needed to ensure interoperability between recorders, players and software.
    [Show full text]
  • Hybrid Bonding Patent Landscape 2019
    Patent Landscape Analysis Hybrid Bonding Patent Landscape Analysis – November 2019 Who has the ability to hamper the development of products using hybrid bonding processes? A technology driven by CIS but on its way to conquer other industries. REPORT OUTLINE • Hybrid Bonding The pace of Moore’s law is slowing, if it has not already stopped, as mentioned by Forbes and • Patent landscape analysis Nvidia. It’s reaching its limits because developing smaller technology nodes is doable • November 2019 technically, but is no longer cost efficient. The digital electronics market requires a higher • Ref.: KM19008 density semiconductor memory chip to cater to recently released central processing unit • PDF > 80 slides (CPU) components. To answer the growing demand and overcome Moore’s law’s limits, • Excel file > 1,000 patents multiple die stacking has been suggested as a solution. Advanced packaging technology • €6,490 for a multi-user license development, specifically 2.5D technology, was first used in high performance applications. Today, scaling the Z axis is becoming more and more important in what is called 3D stacking. REPORT’S KEY FEATURES: Generally, 2.5D-3D stacking was achieved thanks to Through Silicon Via (TSV) technology. • IP trends, including time-evolution However, TSVs are large and using them limits efforts to reach very dense architectures. of published patents, countries of Furthermore, filling TSVs with metals is complex and requires significant know how. To patent filings, etc. overcome these limitations, players have started to look at other solutions. A first step toward • Ranking of main patent assignees a new way of 3D stacking is ZiBond, developed by Ziptronix, a company founded in 2000 as a • Key players’ IP position and spin-out of Research Triangle Institute.
    [Show full text]
  • Equipment and Materials for 3D NAND Manufacturing 2020
    From Technologies to Markets Equipment and Materials for 3D NAND Manufacturing 2020 Market and Technology Report 2020 Sample © 2020 TABLE OF CONTENTS • WFE solutions for 3D-NAND manufacturing 177 • Glossary and definitions 2 o Deposition – CVD, ALD 187 • Table of contents 10 o Dry etching 194 • Report objectives 14 o Lithography 202 • Report scope 15 o Hybrid bonding 210 • Methodology & definitions 16 • 3D-NAND business players 222 • About the authors 17 o Financial analysis 248 • Companies cited in this report 19 o List of recent mergers and acquisitions 265 • Who should be interested in this report? 20 • Equipment for 3D-NAND manufacturing – market overview 270 • Market forecast – deposition for 3D-NAND manufacturing 278 • Yole Group related reports 21 Revenues, shipments (# of chambers), ASP, tool mix, and more • Three-slide summary 23 • Market forecast – dry etching for 3D-NAND manufacturing 286 • Executive summary 27 Revenues, shipments (# of chambers), ASP, tool mix, and more • Introduction and context 61 • Market forecast – lithography for 3D-NAND manufacturing 294 o Overview of the stand-alone memory business 67 Revenues, shipments (# of tools), ASP, tool mix, and more o Overview of semiconductor equipment market 86 • Market forecast – Hybrid bonding for 3D-NAND manufacturing 302 • 3D-NAND business – market, applications, and key players 93 Revenues, shipments (# of chambers) and ASP for two distinct scenarios • 3D-NAND technology and manufacturing process 109 • Impact of COVID-19 on the NAND Business 309 • General conclusions
    [Show full text]
  • Complaint of Tessera Advancedtechnologies, Inc
    UNITED STATES INTERNATIONAL TRADE COMMISSION WASHINGTON, D.C. \ In the Matter of CERTAIN WAFER-LEVEL PACKAGING SEMICONDUCTOR DEVICES AND PRODUCTS CONTAINING SAME Investigation N0. 337-TA­ (INCLUDING CELLULAR PHONES, TABLETS, LAPTOPS, AND NOTEBOOKS) AND COMPONENTS THEREOF COMPLAINT OF TESSERA ADVANCEDTECHNOLOGIES, INC. UNDER SECTION 337 OF THE TARIFF ACT OF 1930, AS AMENDED ~ COMPLAINANT PROPOSED RESPONDENTS Tessera Advanced Technologies, Inc. Samsung Electronics C0., Ltd. 3025 Orchard Parkway 129 Samsung-ro, Maetan-3dong, Yeongtong-gu San Jose, CA 95134 Suwon-si, Gyeonggi-do, South Korea 443-742 T: (408) 321-6000 Samsung Electronics America, Inc. COUNSEL FOR COMPLAINANT 85 Challenger Road Ridgefield Park, NJ 07660 Matthew J. Moore Maximilian A. Grant / Samsung Semiconductor, Inc. Bert C. Reiser 3655 N. 15‘Street LATHAM & WATKINS LLP San Jose, CA 95134 555 Eleventh Street, NW, Suite 1000 Washington, DC 20004 Telephone: (202) 637-2200 Facsimile: (202) 637-2201 Charles H. Sanders LATHAM & WATKINS LLP ' 200 Clarendon Street Boston, MA 02116 Telephone: (617) 948-6000 Facsimile: (617) 948-6000 Michael A. David LATHAM & WATKINS LLP 885 Third Avenue New York, NY 10022 Telephone: (212) 906-1200 Facsimile: (212) 751-4864 TABLE OF CONTENTS I. INTRODUCTION .............................................................................................. .. II. COMPLAINANT ............................................................................................... .. III. PROPOSED RESPONDENTS ..........................................................................
    [Show full text]
  • Tivo Corporation (Exact Name of Registrant As Specified in Its Charter)
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 _____________________________________________________________ FORM 10-K (Mark One) ☒ ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2019 or ☐ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 001-37870 TiVo Corporation (Exact name of registrant as specified in its charter) Delaware 61-1793262 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification No.) 2160 Gold Street , San Jose , California 95002 (Address of principal executive offices, including zip code) (408) 519-9100 (Registrant's telephone number, including area code) Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Trading Symbol(s) Name of Each Exchange on Which Registered Common Stock, par value $0.001 per share TIVO The Nasdaq Stock Market LLC (Nasdaq Global Select Market) Series A Junior Participating Preferred Stock Purchase Rights N/A The Nasdaq Stock Market LLC (Nasdaq Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes ☑ No ☐ Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Securities Act. Yes ☐ No ☑ Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]