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Speed Negotiation Improvement for Hard Disk Drive Serial ATA Interface by Considering Host Compatibility

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Speed Negotiation Improvement for Hard Disk Drive Serial ATA Interface by Considering Host Compatibility Speed Negotiation Improvement for Hard Disk Drive Serial ATA Interface by Considering Host Compatibility by Apisak Srihamat A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Microelectronics and Embedded Systems Examination Committee: Dr.Mongkol Ekpanyapong (Chairperson) Dr.Metthew N. Dailey Mak Chee Wai (External Expert) Nationality: Thai Previous Degree: Bachelor in Computer Engineering King Mongkut’s Institute of Technology, Ladkrabang, Thailand Scholarship Donor: Western Digital – AIT Fellowship Asian Institute of Technology School of Engineering and Technology Thailand December 2014 ACKNOWLEDGEMENTS First of all, I would like to thankful to Dr. Mongkol Ekpanyapong and Dr. Matthew N. Dailey who gave a very good guidance and support encouraged me to study and understand the objective, scope and limitations of this thesis. Then continue provide technical discussion to make me have clearer picture. I’m heartily thankful to Dr.Matthew N. Dailey, Dr.Manukid Parnichkun, and Dr.Metha Jeeradit who gave a very good suggestion during I study in AIT. I also would like to show my gratitude to Western Digital who gives me a time, support and job while I am studying master degree. Special appreciation goes to my supervisor at work, Mr. Petrus Hu, shouldering some of the responsibilities on my behalf in order to allow time for me to be away to complete my Masters study. The person I cannot forget, Mr. Mak Chee Wai as the external expert on the committee panel. He provided invaluable feedback, constant encouragement and support during my Masters study. I would like to thanks to my parents and family, who understand and allowed me to have extra time to work on this thesis. Any errors are mine. ii Abstract Serial ATA interface is mainly use in computer storage technology for a long time especially hard disk drive technology. The performance of interface is one of factor that causes hard disk transfer information faster or slower. And the problem of hard disk drive cannot be detected because of speed negotiation not successfully will cause hard disk drive not be able to load/store digital contents. The deeper understanding of the scenario that leading to worst performance then explanation relationship with speed negotiation was provided in this thesis. The goal is to study various parameters cause speed negotiation drop or not successfully negotiate speed in storage system by design model to experiment on physical parameters as components in storage system and logical parameters as speed negotiation logical implemented in Host and Device. Which Serial ATA specific called as Host Phy initialize state machine or Device Phy initialize state machine. Then setup models to execute the experiments to study and understand the results as target to consider scenario of host compatibility. The result of experimental showed speed negotiation in Serial ATA is only drop at the situation after Out of Band (OOB) signals are successfully transmitted and received (detected) between Host and Device, where by ALIGN primitives not detect at expected speed. Any parameters cause OOB unsuccessfully transmitted and received (detected) between Host and Device will results as cannot communication at all. This information leading to initiated new mechanism to carefully validate Serial ATA speed negotiation in Hard Disk Drive Company. And conclusion to increase visibility of speed negotiation results at end users to identify unexpected combination of storage system. iii TABLE OF CONTENTS CHAPTER TITLE PAGE Title Page i Acknowledgements ii Abstract iii Table of Contents iv List of Tables vi List of Figures vii List of Illustrations viii 1 Introduction 1 1.1 General Background 1 1.2 Statement of the problems 2 1.3 Objectives of the Special Study 2 1.4 Scope 2 2 Literature Review 3 2.1 Introduction to Hard Disk Drives SATA 3 Embedded firmware 2.2 Introduction to SATA specification 6 2.2.1 Physical layer 6 2.3 Expected behaviors in SATA speed 11 negotiation 2.4 Speed negotiation issues on difference host 16 and current work around technic 2.5 Looks for parameter(s)/factor(s) by analyze 21 bus trace of difference system 3 Methodology 23 3.1 Flowchart 23 3.2 Look for physical parameters /factors 24 3.2.1. Device component as physical parameters/factors 24 3.2.2. Cable component as physical 24 parameters/factors 3.2.3. Host component as physical 26 parameters/factors 3.3 Look for logical parameters/factors 28 3.3.1. State machine logic 28 3.3.2. Timing 29 3.4 Setting up model 29 3.4.1. Setting up model for physical 29 parameters 3.4.2. Setting up model for logical 30 parameters 3.5 Setting Simulation 31 3.5.1. Setting Simulation for physical 31 iv parameters 3.5.2. Setting Simulation for logical 35 parameters 3.6 Simulation 42 3.6.1. Simulation for physical parameters 42 3.6.2. Simulation for logical parameters 43 4 Signal detection and signal integrity 47 4.1 Signal detection 47 4.1.1. Signal integrity test 47 4.1.1.1. Clock stability/SSC 49 4.1.1.2. Receiver 51 4.1.1.3. Transmitter 53 4.2 Technique to reduce signal integrity issues 75 4.2.1. Emphasis 75 4.2.2. De-emphasis 76 4.2.3. Equalization 76 5 Host compatibility test 77 5.1 OS Data Integrity 78 5.2 Host chipset compatibility 80 6 Conclusion and Recommendations 83 7 References 85 v LIST OF FIGURES FIGURE TITLE PAGE 1.1 Parallel ATA cable with 40-pin connectors for master and slave 1 drives 1.2 Serial ATA controller connecting with one device on each port 1 1.3 SATA-IO Roadmap updated 2013 2 2.1 ARM processors connected as SoC in hard disk drive block diagram 4 2.2 SATA hardware block 4 2.3 Communication layers 7 2.4 The electronics signal passes through SATA cable between host and 7 device 2.5 RX differential input voltage conditions 8 2.6 Rx Intra-Pair Skew 9 2.7 Example of impedance measured at time 2ns after last major dip 9 2.8 The equipment that currently use to measure signal integrity in 10 SATA Plugfest at Taipei 2013 2.9 COMRESET sequence 10 2.10 Description of COMRESET sequence 11 2.11 Speed negotiation happens during COMRESET sequence 12 2.12 Scenario host 1.5Gbps negotiation speed with drive 6Gbps 13 2.13 Scenario host 3Gbps negotiation speed with drive 6Gbps 14 2.14 Scenario host 6Gbps negotiation speed with drive 6Gbps 14 2.15 Scenario host 1.5Gbps negotiation speed with drive 3Gbps 15 2.16 Scenario host 3Gbps negotiation speed with drive 3Gbps 15 2.17 Scenario host 6Gbps negotiation speed with drive 3Gbps 16 2.18 Scenario host 1.5Gbps negotiation speed with drive 1.5Gbps 16 2.19 Scenario host 3Gbps negotiation speed with drive 1.5Gbps 17 2.20 Scenario host 6Gbps negotiation speed with drive 1.5Gbps 17 2.21 Finisar SATA bus doctors captured SATA speed negotiation was 18 not successfully at 6Gbps 2.22 Flow chart of implemented workaround for new host controller 19 3Gbps chipset when drive at 6Gbps 2.23 Scenario new host controller 3Gbps negotiation speed with drive 19 6Gbps by workaround 2.24 Xgig SATA bus analyzer captured SATA speed negotiation was 20 drop to 1.5Gbps 2.25 Scenario new host controller 3Gbps negotiation speed dropped to 20 1.5Gbps with drive 6Gbps by including workaround 2.26 Performance measuring compare between 1.5Gbps and 3Gbps 21 2.27 Example of BusExpert captured SATA speed negotiation was drop 22 to 3Gbps and analyzing timing of behaviors 3.1 Flowchart of project 23 3.2 Schematic diagram of device’s components and defined physical 24 parameters related with device’s components 3.3 Experiment#1: SPARQ S-parameters measurement and results 25 3.4 Defined physical parameters related with cable’s components 26 3.5 Experiment#2: Environment for SPARQ and SATA cable fixture 26 3.6 Experiment#2: Results of significant impedance difference as 27 vi selected cable defected as physical parameters 3.7 Cable range 30cm(~1 foot) and cable 97cm(~1m) is referring as 27 parameters 3.8 Defined physical parameters related with host and example of host 28 connectors defected 3.9 Defined logical parameters by consider host compatibility 28 3.10 Flow chart of model for simulate scenario of physical parameters 30 3.11 Flow chart of model for simulate scenario of logical parameters 31 3.12 The storage system for setup model to simulate the physical 31 parameters 3.13 The storage system setup as known expected speed negotiation 32 results 3.14 The activity of experiment on physical parameter cable [defects, 32 open] 3.15 AHCI IA based system diagram 33 3.16 Flow chart of software to initiate speed negotiation then check 34 results of negotiation 3.17 Group of input and output of host and device PHY initialize state 35 machine 3.18 Truth table of interested host PHY initialize state machine 35 3.19 Input/output and internal wire required for HostPhyInitSM and 36 DevicePhyInitSM 3.20 Group of input and output of HostPhyInitSM split by state 36 3.21 Group of input and output of DevicePhyInitSM split by state 37 3.22 Truth table listed for HostPhyInitSM 38 3.23 Truth table listed for DevicePhyInitSM 39 3.24 Results of experiment#3 to expriment#56 showed effect from 42 physical parameters 3.25 Physical parameter#4 and parameter#8 result difference speed 42 support 3.26 ModelSim SE implemented Verilog HostPhyInitSM and 43 DevicePhyInitSM 3.27 Results of experiment#57 to experiment#66 to deploy timing 43 parameters from defined timing model 4.1 Signal distorted from transmitter to receiver in electronics 47 system/device 4.2 Step to build up eye diagram and use case scenario 47 4.3 Information from eye diagram 48 4.4 S-Parameters of signal-ended, 2-port network
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