Speed Negotiation Improvement for Hard Disk Drive Serial ATA Interface by Considering Host Compatibility

Apisak Srihamat

A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Microelectronics and Embedded Systems

Examination Committee: Dr.Mongkol Ekpanyapong (Chairperson) Dr.Metthew N. Dailey Mak Chee Wai (External Expert)

Nationality: Thai Previous Degree: Bachelor in Computer Engineering King Mongkut’s Institute of Technology, Ladkrabang, Thailand

Scholarship Donor: Western Digital – AIT Fellowship

Asian Institute of Technology School of Engineering and Technology Thailand December 2014

ACKNOWLEDGEMENTS

First of all, I would like to thankful to Dr. Mongkol Ekpanyapong and Dr. Matthew N. Dailey who gave a very good guidance and support encouraged me to study and understand the objective, scope and limitations of this thesis. Then continue provide technical discussion to make me have clearer picture.

I’m heartily thankful to Dr.Matthew N. Dailey, Dr.Manukid Parnichkun, and Dr.Metha Jeeradit who gave a very good suggestion during I study in AIT.

I also would like to show my gratitude to Western Digital who gives me a time, support and job while I am studying master degree. Special appreciation goes to my supervisor at work, Mr. Petrus Hu, shouldering some of the responsibilities on my behalf in order to allow time for me to be away to complete my Masters study. The person I cannot forget, Mr. Mak Chee Wai as the external expert on the committee panel. He provided invaluable feedback, constant encouragement and support during my Masters study.

I would like to thanks to my parents and family, who understand and allowed me to have extra time to work on this thesis.

Any errors are mine.

Abstract

Serial ATA interface is mainly use in computer storage technology for a long time especially hard disk drive technology. The performance of interface is one of factor that causes hard disk transfer information faster or slower. And the problem of hard disk drive cannot be detected because of speed negotiation not successfully will cause hard disk drive not be able to load/store digital contents. The deeper understanding of the scenario that leading to worst performance then explanation relationship with speed negotiation was provided in this thesis. The goal is to study various parameters cause speed negotiation drop or not successfully negotiate speed in storage system by design model to experiment on physical parameters as components in storage system and logical parameters as speed negotiation logical implemented in Host and Device. Which Serial ATA specific called as Host Phy initialize state machine or Device Phy initialize state machine. Then setup models to execute the experiments to study and understand the results as target to consider scenario of host compatibility.

The result of experimental showed speed negotiation in Serial ATA is only drop at the situation after Out of Band (OOB) signals are successfully transmitted and received (detected) between Host and Device, where by ALIGN primitives not detect at expected speed. Any parameters cause OOB unsuccessfully transmitted and received (detected) between Host and Device will results as cannot communication at all. This information leading to initiated new mechanism to carefully validate Serial ATA speed negotiation in Hard Disk Drive Company. And conclusion to increase visibility of speed negotiation results at end users to identify unexpected combination of storage system.

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TABLE OF CONTENTS

CHAPTER TITLE PAGE

Title Page i Acknowledgements ii Abstract iii Table of Contents iv List of Tables vi List of Figures vii List of Illustrations viii

1 Introduction 1 1.1 General Background 1 1.2 Statement of the problems 2 1.3 Objectives of the Special Study 2 1.4 Scope 2

2 Literature Review 3 2.1 Introduction to Hard Disk Drives SATA 3 Embedded firmware 2.2 Introduction to SATA specification 6 2.2.1 Physical layer 6 2.3 Expected behaviors in SATA speed 11 negotiation 2.4 Speed negotiation issues on difference host 16 and current work around technic 2.5 Looks for parameter(s)/factor(s) by analyze 21 bus trace of difference system

3 Methodology 23 3.1 Flowchart 23 3.2 Look for physical parameters /factors 24 3.2.1. Device component as physical parameters/factors 24 3.2.2. Cable component as physical 24 parameters/factors 3.2.3. Host component as physical 26 parameters/factors 3.3 Look for logical parameters/factors 28 3.3.1. State machine logic 28 3.3.2. Timing 29 3.4 Setting up model 29 3.4.1. Setting up model for physical 29 parameters 3.4.2. Setting up model for logical 30 parameters 3.5 Setting Simulation 31 3.5.1. Setting Simulation for physical 31

parameters 3.5.2. Setting Simulation for logical 35 parameters 3.6 Simulation 42 3.6.1. Simulation for physical parameters 42 3.6.2. Simulation for logical parameters 43

4 Signal detection and signal integrity 47 4.1 Signal detection 47 4.1.1. Signal integrity test 47 4.1.1.1. Clock stability/SSC 49 4.1.1.2. Receiver 51 4.1.1.3. Transmitter 53 4.2 Technique to reduce signal integrity issues 75 4.2.1. Emphasis 75 4.2.2. De-emphasis 76 4.2.3. Equalization 76

5 Host compatibility test 77 5.1 OS Data Integrity 78 5.2 Host chipset compatibility 80

6 Conclusion and Recommendations 83

7 References 85

LIST OF FIGURES

FIGURE TITLE PAGE

1.1 Parallel ATA cable with 40-pin connectors for master and slave 1 drives 1.2 Serial ATA controller connecting with one device on each port 1 1.3 SATA-IO Roadmap updated 2013 2 2.1 ARM processors connected as SoC in hard disk drive block diagram 4 2.2 SATA hardware block 4 2.3 Communication layers 7 2.4 The electronics signal passes through SATA cable between host and 7 device 2.5 RX differential input voltage conditions 8 2.6 Rx Intra-Pair Skew 9 2.7 Example of impedance measured at time 2ns after last major dip 9 2.8 The equipment that currently use to measure signal integrity in 10 SATA Plugfest at Taipei 2013 2.9 COMRESET sequence 10 2.10 Description of COMRESET sequence 11 2.11 Speed negotiation happens during COMRESET sequence 12 2.12 Scenario host 1.5Gbps negotiation speed with drive 6Gbps 13 2.13 Scenario host 3Gbps negotiation speed with drive 6Gbps 14 2.14 Scenario host 6Gbps negotiation speed with drive 6Gbps 14 2.15 Scenario host 1.5Gbps negotiation speed with drive 3Gbps 15 2.16 Scenario host 3Gbps negotiation speed with drive 3Gbps 15 2.17 Scenario host 6Gbps negotiation speed with drive 3Gbps 16 2.18 Scenario host 1.5Gbps negotiation speed with drive 1.5Gbps 16 2.19 Scenario host 3Gbps negotiation speed with drive 1.5Gbps 17 2.20 Scenario host 6Gbps negotiation speed with drive 1.5Gbps 17 2.21 Finisar SATA bus doctors captured SATA speed negotiation was 18 not successfully at 6Gbps 2.22 Flow chart of implemented workaround for new host controller 19 3Gbps chipset when drive at 6Gbps 2.23 Scenario new host controller 3Gbps negotiation speed with drive 19 6Gbps by workaround 2.24 Xgig SATA bus analyzer captured SATA speed negotiation was 20 drop to 1.5Gbps 2.25 Scenario new host controller 3Gbps negotiation speed dropped to 20 1.5Gbps with drive 6Gbps by including workaround 2.26 Performance measuring compare between 1.5Gbps and 3Gbps 21 2.27 Example of BusExpert captured SATA speed negotiation was drop 22 to 3Gbps and analyzing timing of behaviors 3.1 Flowchart of project 23 3.2 Schematic diagram of device’s components and defined physical 24 parameters related with device’s components 3.3 Experiment#1: SPARQ S-parameters measurement and results 25 3.4 Defined physical parameters related with cable’s components 26 3.5 Experiment#2: Environment for SPARQ and SATA cable fixture 26 3.6 Experiment#2: Results of significant impedance difference as 27

selected cable defected as physical parameters 3.7 Cable range 30cm(~1 foot) and cable 97cm(~1m) is referring as 27 parameters 3.8 Defined physical parameters related with host and example of host 28 connectors defected 3.9 Defined logical parameters by consider host compatibility 28 3.10 Flow chart of model for simulate scenario of physical parameters 30 3.11 Flow chart of model for simulate scenario of logical parameters 31 3.12 The storage system for setup model to simulate the physical 31 parameters 3.13 The storage system setup as known expected speed negotiation 32 results 3.14 The activity of experiment on physical parameter cable [defects, 32 open] 3.15 AHCI IA based system diagram 33 3.16 Flow chart of software to initiate speed negotiation then check 34 results of negotiation 3.17 Group of input and output of host and device PHY initialize state 35 machine 3.18 Truth table of interested host PHY initialize state machine 35 3.19 Input/output and internal wire required for HostPhyInitSM and 36 DevicePhyInitSM 3.20 Group of input and output of HostPhyInitSM split by state 36 3.21 Group of input and output of DevicePhyInitSM split by state 37 3.22 Truth table listed for HostPhyInitSM 38 3.23 Truth table listed for DevicePhyInitSM 39 3.24 Results of experiment#3 to expriment#56 showed effect from 42 physical parameters 3.25 Physical parameter#4 and parameter#8 result difference speed 42 support 3.26 ModelSim SE implemented Verilog HostPhyInitSM and 43 DevicePhyInitSM 3.27 Results of experiment#57 to experiment#66 to deploy timing 43 parameters from defined timing model 4.1 Signal distorted from transmitter to receiver in electronics 47 system/device 4.2 Step to build up eye diagram and use case scenario 47 4.3 Information from eye diagram 48 4.4 S-Parameters of signal-ended, 2-port network 48 4.5 PHY-04[a]: Spread-Spectrum Modulation Deviation (Min) 50 Reference 4.6 Jitter in-band and out-band 52 4.7 Result of Rx Imbalance 53 4.8 Result of Rx Differential RL 53 4.9 Result of Tx Imbalance 53 4.10 Result of Tx Differential RL 54 4.11 Result of TSG-02[b]: Fall time (Information) reference 56 4.12 Result of TSG-03[a]: Differential Skew, HFTP (Informative) 56 reference 4.13 Result of TSG-03[b]: Differential Skew, MFTP (Information) 57

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reference 4.14 Result of TSG-04[a]: AC common mode voltage, MFTP reference 57 4.15 Result of TSG-04[b]: AC common mode voltage, HFTP reference 58 4.16 Result of TSG-13[a]: RJ before CIC, MFTP, clock to data, JTF 58 defined (informative) reference 4.17 Result of TSG-13[g]: TJ after CIC, LBP, clock to data, JTF defined 59 (BER=1E-6) reference 4.18 Result of TSG-13[f]: TJ after CIC, HFTP, clock to data, JTF 60 defined (BER=1E-12) (informative) reference 4.19 Result of TSG-13[g]: TJ after CIC, HFTP, clock to data, JTF 61 defined (BER=1E-6) (informative) reference 4.20 Result of TSG-13[f]: TJ after CIC, MFTP, clock to data, JTF 62 defined (BER=1E-12) ( informative) reference 4.21 Result of TSG-13[g]: TJ after CIC, MFTP, clock to data, JTF 63 defined (ER=1E-6) (informative) reference 4.22 Result of TSG-13[f]: TJ after CIC, LFTP, clock to data, JTF defined 64 (BER=1E-12) (informative) reference 4.23 Result of TSG-13[g]: TJ after CIC, LFTP, clock to data, JTF 65 defined (BER-1E-6) (informative) reference 4.24 Result of TSG-13[f]: TJ after CIC, SSOP, clock to data, JTF defined 66 (BER=1E-12) (informative) reference 4.25 Result of TSG-13[g]: TJ after CIC, SSOP, clock to data, JTF 67 defined (BER=1E-6) (informative) reference 4.26 Result of TSG-14: Gen3 (6Gbps) TX maximum differential voltage 68 amplitude reference 4.27 Result of TSG-15: Gen3 (6Gbps) TX minimum differential voltage 69 amplitude (UI=5E6) reference 4.28 Result of TSG-16[a]: Gen3 (6Gbps) Tx AC common mode voltage, 69 FFT 3Ghz reference 4.29 Result of TSG-16[b]: Gen3 (6Gbps) Tx AC common mode voltage, 70 FFT 6Ghz reference 4.30 Result of OOB-04: Drive COMINIT transmit gap length reference 73 4.31 Result of OOB-05: Drive COMWAKE transmit gap length 74 reference 4.32 Result of OOB-07[a]: Drive responds to max in spec COMRESET 74 reference 4.33 Basic concept of pre-emphasis 75 4.34 11110000 binary pattern compare without/with de-emphasis 6dB 76 4.35 Basic concept of equalization 76 5.1 Raid Edition (RE) compatibility process map 78 5.2 Screen short of Passmark BurnInTest 81 5.3 Screen short of Passmark Sleeper 81 5.4 Screen short of Passmark Rebooter 82 5.5 Example of test case and result 82

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LIST OF TABLES

TABLE TITLE PAGE

2.1 List of the exception vector in ARM processors 6 2.2 Lab-source Signal for Receiver Tolerance Testing 8 2.3 The SATA speed support between hosts and devices result 11 possibility of speed establish 2.4 Example of parameters/factors affected with speed negotiation 22 listed 3.1 SATA cable requirements 27 4.1 Results of SATA GEN3 SSC test 49 4.2 Results of SATA GEN2 SSC test 51 4.3 Results of SATA GEN1 SSC test 51 4.4 Results of BER at speed GEN3, GEN2 and GEN1 52 4.5 Results of SATA GEN3 Tx compliant 55 4.6 Results of SATA GEN2i Tx compliant 71 4.7 Results of SATA GEN1 Tx compliant 72 4.8 Results of SATA OOB Tx compliant 73

LIST OF ABBREVIATIONS

AIT Asian Institute of Technology AHCI Advance Host Controller Interface APB Advance Peripheral Bus ATA Advanced Technology Attachment CPU Central Processing Units DMA Direct Memory Access EOM Eye opening monitor Gbps Giga bits per second HWC Hardware Compatibility OS Operating System OSI Open Systems Interconnection PATA Parallel ATA PHY Physical PIT Physical Interface Technology RE Raid Edition RSG Receiver Signaling Group SATA Serial ATA SCSI Small Computer System Interface SoC System on Chips TBG Time Base Generator TCM Tightly-coupled memory

CHAPTER 1 INTRODUCTION

1.1 General Background

In 1988 there is propose from American National Standard of Accredited Standards Committee to define standard for AT Attachment Interface (ATA1) [2]. This standard defines an integrated bus interface between disk drives and host processors. It provides a common point of attachment for manufacturing, integrators and suppliers. AT Attachment or called Parallel ATA (PATA), is an interface standard for computer and storage devices such as hard disk drives, floppy drives and optical disc drives for about 15 years.

Figure 1.1: Parallel ATA cable with 40-pin connectors for master and slave drives [82]

Particular period of time AT Attachment was improvement in multiple generations [3][4][5][6][7][8][9][10][11] by main support from Western Digital. One of the reasons AT Attachment was called PATA is introduction of Serial ATA (SATA) in 2003. [16] SATA replaces the AT Attachment standard by offering several advantages over the older interface by reducing cable size and cost (7 conductors instead of 40), hot plug, faster data transfer via higher signaling rates, and queuing protocol. SATA’s market share in the desktop PC market was 99% in 2008. It’s the release date of ATA8-ACS. [12]

\ Figure 1.2: Serial ATA controller connecting with one device on each port [82]

SATA is the most popular protocol between storage devices and computers, which was developed as 3 generations with different speeds per each generation. First revision was released 2003, known as 1.5 Gbps with 8b/10b encoding. Actual transfer rate is 1.2 G bps (150 MB/s). Initially, host and drive manufacturing use bridge chip to convert existing PATA to become SATA interface. Second revision was released later; it is second generation of SATA interface, known as 3.0 Gbps with 8b/10b encoding. Maximum transfer rate is 2.4 Gbps (300MB/s). The SATA cable that has been using since SATA 1.0 still able to handle transfer rate for SATA 2.0 without loss of sustained and burst data transfer performance. Third revision was released 2008, it’s the generation that still mainly use until now, known as 6.0 G bps with 8b/10b encoding. [7][18][19] The maximum transfer rate is 4.8 G bps (600MB/s). It’s required new cable that support higher transfer rate in physical. SATA 3 also introduces multiple features to improve performance and power consuming.

Figure 1.3: SATA-IO Roadmap updated 2013 [82]

The idea of speed negotiation was introduce as feature called autonegotiation in Ethernet protocol by 2 connected devices choose common transmission parameters as speed, and flow control. Initiate, share their capabilities then choose the highest performance transmission mode supported. In OSI model, autonegotiation was placed in physical layer during 1994-1997 [105][106][107][108][109][110][111]. The method to select mode, clock rate and parameters between device was public to any components later on 2003 [114]. Which it’s about same time SATA-IO started working on SATA 2.x (3Gbps) that required speed negotiation mechanism to allow 1.5Gbps and 3Gbps capable devices connected to 3Gbps capable host. The speed negotiation in SATA was inspired by auto negotiation work and research. However, because system has developed by many different vendors with different architectures and technologies, the speed or communication of SATA has dropped. Thus, it is necessary to investigate the various factors that negatively affect SATA speed in host compatibility and to setup model to improve the SATA speed negotiation.

1.2 Statement of the Problems

Issue was found as host can’t detect the drive or negotiated speed as lower than expected. The host can’t detect drive could cause BSOD (Blue Screen of Death), which consider serious problem in hard disk drive quality test and effected directly to customer satisfy. As well as negotiated speed as lower than expected could cause slower performance that also consider serious problem in hard disk that required maximum performance today.

1.3 Objectives of the Research

The aim of thesis is to study various parameters cause speed negotiation drop or not successfully negotiate speed in storage system.

1.4 Scope

To research to design model to experiment on physical parameters as components in storage system and logical parameters as speed negotiation logical implemented in Host and Device. Which Serial ATA specific called as Host Phy initialize state machine or Device Phy initialize state machine. Then setup models to execute the experiments to study and understand the results as target to consider scenario of host compatibility then provide conclusion for improvement.

Limitation of studying SATA signal integrity parameters that mainly effect with signal detection during speed negotiation required expensive tools that only available in Western Digital Corporation in United State. Experiment#1 and experiment#2 was referring to the signal measurement technique by particular expensive tool. Anyway, result of signal integrity measured is available for study the concept of signal parameters measurement as details in chapter 4.

Another limitation is the rejected proposed to execute experiment at hardware compatibility group that only available in Western Digital Corporation in United State. The experimental similar to the experimental executed for physical parameters as experiment#3 to experiment#56 in chapter 3 should be able to provide result of speed negotiation between Western Digital hard disk drive and various host controller implemented for actual market.

CHAPTER 2 LITERATURE REVIEW

2.1.Introduction to Hard Disk Drive SATA embedded firmware

The hard disk drive is a real-time control system was designed to use System on Chip (SoC) as integrated circuit (IC) that integrates embedded necessary blocks such as main controller, read channel, servo controller, buffer manager hardware block, DMA engine and interface SATA hardware block. Today ARM processor is the mainly use as processor cores in hard disk drive processor for some period of time. [57]

Figure 2.1 ARM processors connected as System on Chip in hard disk drive block diagram The SATA was embedded to the SoC as one of the module that integrated SATA Physical Layer (PHY), Link and Transport or Queue Manager blocks into a single module that allows direct and instant interconnections between the PHY and Transport layers. The embedded SATA module interfaces directly to the Serial ATA physical connection to receive and transmit difference data to handle all low-level transections (primitives) that comply with SATA 1.5G bps, 3G bps and 6G bps specification requirements, and application command and data transfer protocols that have to meet ATA and Serial ATA standard by referring to Time Base Generator (TBG). [62][64][77][78][79]

Figure 2.2 SATA hardware block The firmware implemented on µC/OS-II [120] by referring on basic operating system building blocks, tasks and event flag group. µC/OS-II provides the ability to destroy a task and then create it again. This capability is expected to be useful for aborting a current disk operation and quickly starting a new one.

SATA PHY module must have features that required for testing such as eye-opening monitor (EOM) to evaluate eye-opening [40] after receiver equalization which will explain more details in chapter 4, built-in PHY test to implement different self-test schemes and also loopback mode. In term of configuration should also configurable data rate as SATA spec required 1.5G bps, 3G bps and 6G bps, for some SoC might be able to perform automatic speed configuration. Then will need to have interface to CPU such as APB3 16- bits data parallel CPU interface or 3 bit serial CPU interface etc. The power management features as one of the main features in SATA as per requirement of reduces power consumption in computer/laptop technology required SATA PHY module to be able to control power. [28][41][43][48][56] The hard disk drive firmware behaviors after power up until post ready status to SATA Interface are, o Power on o Load specific configuration for initialize and control had disk drive o Initialize SoC, flash memory, SATA PHY, buffer, DRAM, Servo, channel, peripheral and connected hardware block resources o Initialization is required to perform as specific step because it’s necessary to wait for some hardware block to be initialized until complete before continue initialize next for example if flash memory stored configuration for initialize SATA PHY, it’s necessary to wait until initialize flash memory until finish and available to access to get particular configuration before initialize SATA PHY. And of course need to initialize SoC configuration related with bus that need for transfer data from/to memory address before initialize flash memory. o SATA PHY settings was optimized by using features eye-opening monitor, built-in PHY test and loop back mode then measuring to find tune signal integrity to meet product requirement and SATA compliant. [17][18][19] o Initialize operating system and individual threads (tasks) to be ready to work as specific behaviors required by hard disk drive such as disk task, background task and interface task etc. o Then will enable hardware interrupt such as SATA interface interrupt for receive new command. o After all related hardware is ready for work then hard disk drive will post status ready to host.

SATA Interrupt was designed to use as mark able IRQ interrupt. Based on ARM architecture the exception is taken whenever the normal flow of a program must temporary halt. For example to services an interrupt from a SATA command received. Before attempting to handle an exception, the processor preserved the critical parts of the current processor state so that the original program can resume when the handler routine has finished.

Table 2.1 List of the exception vectors in ARM processors [57] Interrupt request was generally defined in hard disk drive firmware as servo IRQ, Host IRQ and IRQ Dispatcher (SATA/Peripheral), the embedded SATA interrupt is generated from embedded hardware block and synchronized to the CPU clock. Assigned one of register to get set and remains set until all the enabled interrupt sources are cleared in the appropriate status registers. Note that CPU core may not respond to the interrupt immediately because of the wait state logic. However, the interrupt signal is latched until it is served. The example of SATA interrupt that mainly use in hard disk drive firmware are listed below, o Hardware reset/Software reset – The handler will perform disable power management timer and activate workaround state machine to avoid particular host controller chipset speed negotiation problem then calling reset handler to turn on LED and perform appropriate reset sequence/state machine. o Embedded SATA error and Command execution error – The handler will check if there FIFO overrun/parity error, data length error and transmit error to reset TX flow and command execution. Post interface CRC error if there is the cases. o Command process error – The handler will take it seriously to pause the activity as possibility internal embedded SATA internal FIFO of command execution sequence buffer or command receive sequence buffer has parity error. o Command receive error – The handler will check if queue tag error, mixed queue command and mix with non-queued command error then perform necessary process to clear queue error such as reset command execution sequence buffer FIFO, command receive sequence buffer FIFO, transport flow. Then clear FIFO error to report queue exception to host. o Transport layer interrupt – The handler will check if there are device initiate power management or host initiate power management was rejected by host, also check for PhyNotRdy to perform asynchronies signal recovery (ASR) if there is reach time limit. Check COMRESET was issue by host then wake reset state machine. Check COMWAKE was issue by host then update states of workaround state machine to avoid particular host controller chipset speed negotiation problem. Lastly check PhyRdy detected to change state machine to ready then disable workaround state machine to avoid host controller chipset speed negotiation problem. o Command abort – The handler will post exception for intruding command. (Received command when data transfer, ATA task file register data request was set)

o New command detected – The handler will active LED then wake up host task to decode command received then perform necessary proves per each command. o Firmware/hardware data transfer request done – Since hard disk drive firmware started transfer data, firmware will pending for event transfer complete to continue necessary release resource/buffer then particular event will generate by handler at this point.

2.2.Introduction to SATA specification

SATA specification defines protocol in 3 layer as physical layer, link layer and transport layer.

Figure 2.3 communication layers [18]

2.2.1. Physical layer is provide a description of characteristics to ensure interoperability of SATA components between host, device and interconnects and the expectation that Serial ATA device and host shall comply with the electronic specifications [16][17][18][19]

Figure 2.4 the electronics signal passes through SATA cable between host and device

The example of definition of Rx Differential Skew for SATA 2 and 3, it’s time difference between the single-ended mid-point of the Rx- signal failing/rising edge, and the single-

7 ended mid-point of the Rx+ signal rising/failing edge, as measured at the Rx connector. The receiver should tolerate the Rx skew per table 1.

Table 2.2 Lab-Sourced Signal for Receiver Tolerance Testing [18] The Rx Differential Input Voltage is the range of input voltage under compliance test conditions that receiver should operate. The Serial ATA device/host/connector has a transmitter and receiver with impedances near the nominal system impedance of 100 Ohms. [18]

Figure 2.5 RX Differential Input Voltage Conditions [18] The receiver Skew is an important parameter as excessive skew may effect to increased high frequency jitter and high frequency common mode noise at the high speed differential signal. Refer to figure 3 for late and early skew signaling affect the time when receiver resolves the differential input signals.

Figure 2.6 RX Intra-Pair Skew [18] In implementation, there is required to measurement the signal. For example developer will measure Rx differential to verify the pair differential impedance of the product under test transmitter is within expected limits. The test must be completed during transmission of the Mid Frequency Test Pattern (MFTP), the amplitude of a TDR pulse or excitation applied to an active transmitter shall not exceed 139mVpp (-13.2dBm 50 Ohms) signal ended. The test will verify both the minimum (85 Ohms) and maximum (115 Ohms) results for the pair differential impedance. (For 1.5 G bps products)

Figure 2.7 Example of impedance measured at time 2ns after last major dip The MFTP is pattern: 1100110011 0011001100b = encoded D24.3, its repetitive pattern.

Figure 2.8 the equipment that use to measure signal integrity in SATA-Plugfest convention at Taipei 2013 The purpose of a Serial ATA Plugfest is short time validating the design and develop products are in process of implementing Serial ATA protocol and features. The target product should be prototypes, products under development. There is multiple vendors designed and developed test tools to help to validate and advice on unclear features. The system set up from Tektronix, Lecroy and Agilent. It’s indirectly event to introduce new product from measurement’s vendors and host/device’s vendors.

In Physical layer also describe power-on sequence that specify the expected behavior of device and host after power-on to establishment of an active communication as COMRESET/COMINIT sequence

Figure 2.9 COMRESET sequences [18] There is description to explain each step of host/device as 9 steps and state machine in SATA spec, which will lead host/device/connector developers to be synchronized in expected behaviors.

Figure 2.10 description of COMRESET sequence [18] During the step where the PHY detection of received ALIGN primitives for state transitions, the PHY required accurate detection of the ALIGN primitive at particular signal speed, with required appropriate implementation to make sure there is no miss detection of ALIGN primitives that will lead to mistaken difference data rate detected. In fact, host capable 6G bps could also connect to drives capable 3G bps and/or 1.5G bps. In the other hand, drive capable 6G bps could connect to host capable 3 G bps and/or 1.5G bps. But communication will only established at lowest speed between both sides.

Table 2.3 the SATA speed support between hosts and drives result possibility of speed establish

2.3. Expected behaviors in SATA speed negotiation

The Speed negotiation happens during COMRESET sequence. It’s initialize step when attached storage device to host system to determine the speed that device and host is going to use for communication.

Host Device

Speed negotiation

Figure 2.11 Speed negotiation happens during COMRESET sequence [18]

The expected speed negotiation is a minimum of maximum of host speed and maximum of drive speed. ExpectedMaxSpeedNegotiation = Min(maxHostSpeed,maxDriveSpeed)

The scenario for 9 cases of difference host and device speed negotiation as listed.

• Host 1.5Gbps/Drive 6Gbps: Expected maximum speed at 1.5Gbps • Host 3Gbps/Drive 6Gbps: Expected maximum speed at 3Gbps • Host 6Gbps/Drive 6Gbps: Expected maximum speed at 6Gbps

• Host 1.5Gbps/Drive 3Gbps: Expected maximum speed at 3Gbps • Host 3Gbps/Drive 3Gbps: Expected maximum speed at 3Gbps • Host 6Gbps/Drive 3Gbps: Expected maximum speed at 3Gbps • Host1.5Gbps/Drive 1.5Gbps: Expected maximum speed at 1.5Gbps • Host 3Gbps/Drive 1.5Gbps: Expected maximum speed at 1.5Gbps • Host 6Gbps/Drive 1.5Gbps: Expected maximum speed at 1.5Gbps

Figure 2.12 Scenario Host 1.5Gbps negotiation speed with Drive 6Gbps At host beginning of speed negotiation 533ns (20Dwords at lowest speed 1.5Gbps) is maximum time at host side for speed COMWAKE negated before start sending D10.2 when device negate last COMWAKE as defined in SATA spec section OOB signal. The device also have allowed time 53.3us + 175ns for holding time before hardware initialize to transmit first ALIGN primitives at drive’s highest speed. The 873.8us is allowed time at host to wait for host to detect device transmit ALIGN primitives. If no ALIGN primitives detect at host within time limited, host will retry again by initiate COMRESET sequence. At Drive side 54.6us or 109.2us allowed time to keep sending ALIGN primitives at the speed support at the same time drive’s receiver will look for ALIGN primitives response from Host. If no response for 54.6us or 109.2us, drive will drop speed to lower and try again until lowest support speed. The drive will have limit timeout to indicate host not available but it’s not defined in SATA spec for expected behaviors in Drive side.

Figure 2.13 Scenario Host 3Gbps negotiation speed with Drive 6Gbps

Figure 2.14 Scenario Host 6Gbps negotiation speed with Drive 6Gbps

Figure 2.15 Scenario Host 1.5Gbps negotiation speed with Drive 3Gbps

Figure 2.16 Scenario Host 3Gbps negotiation speed with Drive 3Gbps

Figure 2.17 Scenario Host 6Gbps negotiation speed with Drive 3Gbps

Figure 2.18 Scenario Host 1.5Gbps negotiation speed with Drive 1.5Gbps

Figure 2.19 Scenario Host 3Gbps negotiation speed with Drive 1.5Gbps

Figure 2.20 Scenario Host 6Gbps negotiation speed with Drive 1.5Gbps

2.4. Speed negotiation issues on difference host and current work around technic

As per look at information from SATA spec in PHY layer, there is allowable for Host/Device to implement speed negotiation in the difference ways but specific pattern of detecting signal like ALIGNp or DWORDS to recognize speed before starting normal communication as speed detected. Which could cause the issue that host can’t detect the drive or negotiated speed as lower than expected. The host can’t detect drive could cause BSOD (Blue Screen of Death) that consider serious problem in hard disk drive test case and effected to customer satisfy. As well as negotiated speed as lower than expected could cause slower performance that also consider serious problem in hard disk.

Figure 2.21 Finisar SATA Bus Doctor captured SATA speed negotiation was not successfully at 6G bps Finisar SATA Bus Doctor captured SATA speed negotiation was not successfully at 6Gbps when Host and drive are 6G bps capable. This case has happened when host controller Developer Company released new chipset. The host implementation isn’t following spec and need more allowable time to perform speed negotiation. By considering signal captured by logic analyzer then realized that particular host controller 3G bps SATA host missed detects 6G bps signal as 3G bps signal (ALIGN and SYNC primitive) during 2 nd speed negotiation window with 3G bps ALIGN primitives host switch to sending SYNC prematurely. Once host is in this state COMINIT (via ASR) is required to reset OOB and try again.

There is decided to work around the problem by fixing speed at 6G bps then force to go down to 3G bps after period of time to ensure that timing for negotiation at 6G bps is long enough to cover host controller chipset’s bugs. The implementation happened in the device firmware when load and initialize SATA Phy as its first period that will have speed negotiation after power cycle the drive.

Figure 2.22 flow chart of implemented workaround for host controller 3G bps capable that has a problem when drive at 6G bps As per flow chart after hard disk drive powered on then firmware was loaded by second level loader then started execute hard disk drive firmware then initialized necessary SATA PHY register as to control higher SATA speed (6G bps for this case) then wait for abut 250us for receiving COMWAKE OOB before force device to drop speed setting in SATA PHY register to become 3G bps instead of 6G bps. This design was proved that fix the problem found earlier on particular host controller 3Gbps chipset and implemented in production firmware since then.

Figure 2.23 Scenario particular host controller 3Gbps negotiation speed with Drive 6Gbps by workaround

Later, we found out that the designed workaround solution is affected directly to another host chipset that capable to communicate to 6G bps speed but naturally can’t accomplishment speed negotiation in period of time frame 240us. This scenario causes device not able to communicate to host as expected speed then drop down to lower speed and directly cost in performance of the drive slower than expected.

Figure 2.24 Xgig SATA bus analyzer captured SATA speed negotiation was drop to 1.5Gbps Xgig SATA bus analyzer captured SATA speed negotiation between host chipset LSI 1064/1068 and drive. The speed was dropped to 1.5Gbps even Host is 3Gbps capable and drive is 6Gbps capable after apply work around. The root cause was identified as timing issue when ALIGN primitives was sending between host/drive cause host drop down speed after missing speed negotiation windows of 3Gbps then drop down to 1.5Gbps.

Figure 2.25 Scenario LSI Host 3Gbps negotiation speed dropped to 1.5Gbps with Drive 6Gbps by including workaround

The data analysis from the speed drop to 1.5G bps instead of expected 3G bps as host capable by chipset LSI 1064/1068 and drive capable is 6G bps measuring sequential read/write block count 256 with queue deep 16.

Figure 2.26 Performance measuring compare performance between speed 1.5G bps and 3G bps

As per measured average transfer rate is as below, When speed drop to 1.5G bps o Average transfer rate of sequential write block count 256, queue deep 16 is 132550 kbps o Average transfer rate of sequential read block count 256, queue deep 16 is 134902 kbps

When speed stay at 3G bps o Average transfer rate of sequential write block count 256, queue deep 16 is 178438 kbps o Average transfer rate of sequential read block count 256, queue deep 16 is 178397 kbps

2.5.Looks for parameter(s)/factor(s) by analyze bus trace of difference system

The host compatibility that executing today after development hard disk drive is about 200 difference host system. The plans to look for get bus trace for speed negotiation period then analyze to get solid parameter(s) and/or factors(s) for improvement.

Figure 2.27 Example of SerialTek SATA BusXpert captured SATA speed negotiation was drop to 3Gbps and analyzing timing of behaviors SerialTek SATA BusXpert captured SATA speed negotiation was drop to 3Gbps when Host chipset LSI 9265/9280 6Gbps capable and Drive is also 6Gbps capable, in this case host required more time to ready to detected 6Gbps ALIGNp from drive then drop down to 3Gbps at the end. Analyzed factors and/or parameters that effected with speed negotiation in host environment in the table.

Table 2.4 Parameter/Factors affected with speed negotiation listed

CHAPTER 3 METHODLOGY

3.1. Flowchart

The flowchart of this project is show in figure 3.1.

Start

Looking for control parameter(s)/factor(s)

Setup Model

Setup Simulation

Simulation

End

Figure 3.1 Flowchart of project

3.2. Look for physical parameters/factors

The parameters/factors were considered from storage system as physical and logical. The physical parameters were considered from components of Device, Cable, and Host. The reason is the storage system in real use cases scenario is the combination of components listed and those components could have a physical factors that suspected cause speed drop or speed negotiation not successfully.

3.2.1. Device component as physical parameters/factors

Consider Device’s schematic diagram. [87] Device components that related with SATA Tx, Rx path was identified as parameters.

Figure 3.2: Schematic diagram of device’s components and parameters

The experiment 01: During period of define SoC defects cause communication issue, LeCroy SPARQ is used to look at the TDR profile of SoC to compare the TDR profiles between the Good and NG chips. GigaProbe DVT-30 is used for probing the BGA balls. Microscope eheV1 is used for high-resolution imaging for accurate positioning of the probe.

Figure 3.3: Experiment 01: SPARQ S-parameters measurement and results

SATA_RXP and SATA RXM show very different differential TDR profile and S- parameters [116] for SoC good and NG. Observed good case, the S11 shows almost all the signal energy is reflected back at frequencies below 8GHz. For NG case, the S11 shows an upward rising profile – signal energy is transmitted at frequencies below 8GHz but as frequency increases, more signal reflected. 25

3.2.2. Cable component as physical parameters/factors

Consider Cable’s components [19] as from real scenario the wire/connectors were identified as possible defect as short and Open. There also agreement of long wire range could cause connectivity issue more easily. Also common contaminations were also considered in the scenario of coffee/water and dust.

Figure 3.4: Defined parameters related with cable’s components

Experimental 02: During period of identify possible defect, LeCroy SPARQ [99] is used to look at the TDR profile to compare the TDR profiles between the Good and NG (Short/Open) cables. As result showed impedance is significant compared Good and NG cables.

Figure 3.5: Experimental 02: Environment for SPARQ and cable fixture [19][99]

Table 3.1: SATA cable requirements

Figure 3.6: Experimental 02: Result of significant impedance difference of selected cable defects as physical parameters Experimental 02: The result showed good cable has impedance about 85-115 ohm and stay close to 100 ohm along the wire. The Open cable is infinity ohm and short cable is nearly zero ohms.

Figure 3.7: Cable range 30cm (~1 Foot) and cable 97cm (~1m) is referring as parameters.

3.2.3. Host component as physical parameters/factors

As scope of research is not cover internal Host system as consider as black box. Consider only external Host components that commonly found in storage system as connectors and contaminations.

Figure 3.8: Defined parameters related with host and example of host connectors detected

This host is a SATA connector defect host. The defect happened during shipment because the person who shipped this system doesn’t package properly. Power Supply was just place nearby computer’s mother board. A lot of air plan’s vibration and hand carry package by postman made Power Supply bump to SATA connector cause SATA connector scratched. When connect this SATA connector to hard disk drive by well-known good SATA cable. The DOS-Operating System showed interrupt error, which suspected it happened because architecture of DOS-Operating System was driving by single thread IO based.

3.3. Look for logical parameters/factors

The parameters/factors were considered from storage system as physical and logical. The logical parameters were considered from the implementation effort of difference host/device.

Figure 3.9: Defined logical parameters by consider host compatibility

3.3.1. State machine logic

The logic of COMRESET sequence defined [16][17][18][19] is not really proved that all host and device really implement as same concept. This is considering one of logical parameters. Especially, the ALIGN primitives detection.

3.3.2. Timing

By consider time model of expected behaviors of speed negotiation we realized: Timing that ALIGN will transmit from drive is: Di = Dcn + Dhi Di is required time for drive initialize to transmit ALIGN primitives Dcn is duration time that drive COMWAKE negate Dhi is duration time that drive holding idle before transmit ALIGN primitives

Timing that ALIGN was detecting by host is: Hdet = Di + ∑ Dtrans + Hi + ∑ Hdets

Hdet is required time for Host to detect ALIGN primitives Di is required time for drive initialize to transmit ALIGN primitives Dtrans is required time for drive to transmit signal of ALIGN primitives at speed (each) Hi is required time for host initialize detectors to detect ALIGN primitives Hdets is required time for host to detect ALIGN primitives (each)

The speed drop will happens as condition: Hdet > Hadet

Hdet is required time for Host to detect ALIGN primitives Hadet is allowed time for Host to detect ALIGN primitives

Note that Hadet is constant per SATA spec, its 54.6us. Must consider to reduce required time for host to detect ALIGN primitives. There is limitation by hard disk drive to access to host improvement then will consider only drive improvement.

3.4. Setting up model

As parameters ware defined as physical and logical, the model was setting up separately for different categories of parameters.

3.4.1. Setting up model for physical parameters

Model was designed to simulate physical parameters by create software to control Host Bus Controller to perform 1,000 loops of power cycles, allow few seconds for speed negotiation until hard disk drive ready to communication then check SATA speed to make sure drive is not drop the speed or can’t communicate. The similar model was defined as NLP Receive Link Integrity Test state diagram [105]. The model of experiment will execute on 3 Hosts that was configuration to SATA speed 6Gbps, 3Gbps and 1.5Gbps to study the effect of physical parameters to each known good storage system that can negotiate speed as expected in 1,000 loops without any issues found. The 3 Hosts will still remain same motherboard and Host Controller chipset as per limitation of hardware usage to perform the experiment.

Figure 3.10: Flow chart of model for simulate scenario of physical parameters

3.4.2. Setting up model for logical parameters

Model was designed to simulate logical parameters by actual implement the SATA speed negotiation state machine by VLSI on ModelSim PE Student Edition [100] to simulate and study both state machine logic and timing. This model of experiment is indirectly referring to Open-Source SATA Core for Virtec-4 FPGAs [49] was public as completed SATA speed negotiation state machine that control Virtec-4 FPGAs hardware by Field- Programmable Gate Arrays (FPGAs) to communicate with hard disk drive as a Host. Actually the Master Thesis [49] is target to implement high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. But the Master Thesis also implemented must have functionality of SATA like speed negotiation state machine as to remain high-speed Data Acquisition System.

Figure 3.11: Flow chart of model for simulate scenario of logical parameters

3.5. Setting Simulation 3.5.1. Setting Simulation for physical parameters

The storage system was setting up for validating model to simulate the physical connectivity parameters. As the limitation of hardware usage the storage test system is referring to well-known good 3 Host configured to difference possible SATA speeds (1.5Gbps, 3Gbps and 6Gbps) by configure the AHCI registers on the host controller. Those hosts will connect to Hard Disk Drive configured as SATA speeds matched with each Host. It’s mean storage test system is 3 sets of Host connected to Hard Disk Drive.

Figure 3.12: The storage system for set up model to simulate the physical connectivity parameters

The model to simulate the scenario of physical connectivity parameters was implemented as pictures below:

Figure 3.13: The system setup as known expected speed negotiation results

The physical parameters will be placing to replace well-known good components in the system as experiments to study the effect of physical parameters to the SATA speed negotiation. For example: When consider one of physical parameters as cable component [defect, open] the defect cable that measured infinity impedance will be place to system number 1 (6Gbps capable) then start software to execute 1,000 loops of SATA speed negotiation to get the result of speed negotiation.

Figure 3.14: The activity of experiment on physical parameter Cable [Defects, open] The similar activity will happen again on Host number 2 (3Gbps capable) and then Host number 3 (1.5Gbps capable)

Software to simulate speed negotiation was implementing by referring to Dos operating system’s API through Western Digital internal tools called Taskfile Register Exerciser that accepts user commands through the keyboard or via script files. It will display the task file data and status through various interface screens. The execution at CPU to control AHCI controller is displayed as architecture below.

Figure 3.15: AHCI IA Based system diagram [23]

AHCI registers [20][21][22][23] was mainly referring to control COMRESET sequence as listed: Offset 18h: PxCMD – Port x Command and Status PxCMD[01] Spin-Up Device (SUD): This bit is read/write for HBAs that support staggered spin-up. On an edge detect from ‘0’ to ‘1’, the HBA shall start a COMRESET initialization sequence to the device. Clearing this bit to ‘0’ does not cause any OOB signal to be sent on the interface. Offset 28h: PxSSTS - Port x Serial ATA Status (SCR0: SStatus) PxSSTS[07:04] Current Interface Speed (SPD): Indicates the negotiated interface communication speed. PxSSTS[03:00] Device Detection (DET): Indicates the interface device detection and Phy state. * (The means by which the implementation determines device presense may be vendor specific. However, device presense shall always be indicated anytime a COMINIT signal is received.) Offset 2Ch: PxSCTL - Port x Serial ATA Comtrol (SCR2" SControl) PxSCTL[07:04] Speed allowed (SPD) was referring for indicates the highest allowable speed. 0h - No speed negotiation restrictions 1h - Limit speed negotiation to Generation 1 2h - Limit speed negotiation to a rate not greater than Generation 2 3h - Limit speed negotiation to a rate not greater than Generation 3 All other values reserved PxSCTL[03:00] Device Detection Initialization (DET): Controls the HBA's device detection and interface initialization.

0h - No device detection or initialization action requested 1h - Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications reinitialized. While this field is 1h, COMRESET is transmitted on the interface. Software should leave the DET field set to 1h for a minimum of 1 millisecond to ensure that a COMRESET is sent on the interface. 4h - Disable the Serial ATA interface and put Phy in offline mode.

Figure 3.16: Flow chart of software to initiate speed negotiation and check expected results

3.5.2. Setting Simulation for logical parameters Design DUT and components in Verilog Language

As Verilog development required, define the Device under test (DUT) and components in the Verilog model and signal that will transfer per each components.

Reset, Host Phy Initialize Signal (OOB, ALIGN [Gen1-3], D10.2), Device’s Signal State Machine PhyRdy, Gen

Device Phy Initialize Reset, Signal (OOB, ALIGN [Gen1-3], SYNC), State Machine Host’s Signal PhyRdy, Gen

Figure 3.17: Group of input and output of Host and Device Phy initialize state machine

Wrote down truth table:

Figure 3.18: Truth table of interested Host Phy initialize state machine

To define input corresponding to output for each state machine as well as internal logic that will help input to be able to control output such as interval, ordering of input. Karnaugh Maps [101][102] only allow for small design problems as four variables. There are larger Karnaugh Maps discussed [103][104], it could apply together with complex calculation. To satisfy optimizing digital logic by divide smaller input/output and truth table for each state machine.

Figure 3.19: Input/output and internal wire required for HostPhyInitSM and DevicePhyInitSM

Figure 3.20: Group of input and output of HostPhyInitSM split by State

Figure 3.21: Group of input and output of DevicePhyInitSM split by State

The technique to split input and output helped simplify the truth table and optimization

*Red color is the scenario speeds were mistakenly detected by hardware; logic control will adjust to minimum speed detected.

*Red color is unexpected scenario; state machine should still remain in same state.

Figure 3.22: The Truth table listed for HostPhyInitSM

Figure 3.23: The Truth table listed for DevicePhyInitSM

Performed Karnaugh Maps and optimize digital gate design for HostPhyInitSM result is:

HR_Reset: HR_AwaitCOMINIT = ~Reset COMRESET = Reset

HR_AwaitCOMINIT: HR_AwaitNoCOMINIT = COMINIT HR_Reset = ~COMINIT x COMINITRetryInterval

HR_AwaitNoCOMINIT HR_COMWAKE = ~COMINIT

HR_COMWAKE HR_AwaitCOMWAKE = ~COMWAKE HR_AwaitNoCOMWAKE = COMWAKE COMWAKE = 1 // COMWAKE = 0 when enter into next state

HR_AwaitCOMWAKE HR_AwaitNoCOMWAKE = COMWAKE HR_Reset = ~COMWAKE x COMWAKERetryInterval COMWAKE = 0

HR_AwaitNoCOMWAKE HR_AwaitAlign = ~COMWAKE COMWAKE = 0

HR_AwaitAlign HR_AdjustSpeed = ALIGN_6G + ALIGN_3G + ALIGN_1_5G HR_Reset = ~ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G x ALIGNRetryInterval AdjustTo6G = ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G AdjustTo3G = ALIGN_3G x ~ALIGN_1_5G AdjustTo1_5G = ALIGN_1_5G D10_2 = ~ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G x ~ALIGNRetryInterval

HR_AdjustSpeed HR_SendAlign = AdjestTo6G + AdjustTo3G + AdjustTo1_5G Gen_6G = AdjustTo6G x ~AdjustTo3G x ~AdjustTo1_5G Gen_3G = AdjustTo3G x ~AdjustTo1_5G Gen_1_5G = AdjustTo1_5G

HR_SendAlign ALIGN_6G = Gen_6G x ~Gen_3G x ~Gen_1_5G ALIGN_3G = Gen_3G x ~Gen_1_5G ALIGN_1_5G = Gen_1_5G HR_Ready = (SYNC x Gen_6G) + (SYNC x Gen_3) + (SYNC x Gen_1_5G)

HR_Ready ALIGN_6G = 0 ALIGN_3G = 0 ALIGN_1_5G = 0 PhyRdy = 1

Performed Karnaugh Maps and optimize digital gate design for DevicePhyInitSM result is:

DR_Reset DR_COMINIT = ~Reset x COMRESET DR_COMINIT DR_AwaitCOMWAKE = 1 COMINIT = 1 DR_AwaitCOMWAKE DR_AwaitNoCOMWAKE = COMWAKE DR_Reset = ~COMWAKE x COMWAKERetryInterval DR_AwaitNoCOMWAKE DR_COMWAKE = ~COMWAKE DR_COMWAKE DR_SendAlign = 1 COMWAKE = 1 DR_SendAlign [Knurh map 5 variable] DR_ReduceSpeed = ~LowestSpdFlag x ALIGNRetryInterval x ~ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G DR_Error = LowestSpdFlag x ALIGNRetryInterval x ~ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G DR_Ready = (~LowestSpdFlag x ALIGN_6G x ~ALIGN_3G x ~ALIGN_1_5G) + (~LowestSpdFlag x ~ALIGN_6G x ALIGN_3G x ~ALIGN_1_5G) + (~LowestSpdFlag x ~ALIGN_6G x ~ALIGN_3G x ALIGN_1_5G) + (LowestSpdFlag x ~ALIGN_6G x ~ALIGN_3G x ALIGN_1_5G) TransmitALIGN = (ALIGN_3G x ALIGN_1_5G) + (LowestSpdFlag x ALIGN_6G) + (LowestSpdFlag x ALIGN_3G) + (~LowestSpdFlag x ALIGN_6G x ALIGN_1_5G) + (~LowestSpdFlag x ALIGN_6G x ALIGN_3G) + (~ALIGNRetryInterval x ~ALIGN_6G x ~ALIGN_3G x x ~ALIGN_1+5G) COMWAKE = 0 DR_SendAlign_2 ALIGN_6G = TransmitALIGN x Gen_6G x ~Gen_3G x ~Gen_1_5G ALIGN_3G = TransmitALIGN x Gen_3G x ~Gen_1_5G ALIGN_1_5G = TransmitALIGN x Gen_1_5G DR_ReduceSpeed DR_SendAlign = (Gen_6G x ~Gen_3G x ~Gen_1_5G) + (~Gen_6G x Gen_3G x ~Gen_1_5G) DR_Error = (~Gen_6G x ~ Gen_3G) + (Gen_1_5G) + (Gen_6G x Gen_3G) LowestSpdFlag = ~Gen_6G x ~Gen_3G x Gen_1_5G Gen_6G = 0 // never reduce to maximum Gen_3G = (Gen_6G x ~Gen_3G x ~Gen_1_5G) Gen_1_5G = (~Gen_6G x Gen_3G x ~Gen_1_5G) DR_Error DR_Reset = 1 //For debugging propose, let it stay still

DR_Ready ALIGN_6G = 0 ALIGN_3G = 0 ALIGN_1_5G = 0 PhyRdy = 1

3.6. Simulation

3.6.1. Simulation for physical parameters

Figure 3.24: Results of experiment#3 to experiment#56 showed effect from physical paramaters. As combination 54 results of experiment (18 parameters x 3 Storage systems) defined as experiments number 03-56 in this paper, the drive can’t communicate in the storage system is most of the physical parameters but no result as speed drop found. Information found is each 1,000 loops that executed total 54,000 loops have repeating result. These results showed most of physical parameters chosen are strongly impact to the signal detection [32][34][38][39] at every speed. And same host (configuration) is actually has same results with significant factors added into the storage system experimental results.

1 1 Parameter4 Parameter18 6G 6G

0 Parameter4 Parameter18 1.5G 0 3G 0 500 1000 0 500 1000 Parameter4 Parameter18 3G 1.5G -1 -1

Figure 3.25: Parameter 4 and Parameter 8 was place on storage system cause difference speed The parameters hard disk drive connectors defects and host connectors defects could cause high speed at 6Gbps drop but still remain communicable as expected speed when lower speed to 3Gbps and 1.5Gbps. Those physical parameters 4 and 18 are interesting to investigate into details by measuring physical signal integrity parameters [40][56][71][88] of those physical parameters to identify the parameters cause speed negotiation not successful. It is required to analyze the scenario of uncompleted negotiated speed to understand the signal receiver and transceiver [28][34][54][79][80][86] cause highest speed at 6Gbps can’t be detect OOB/ALIGN primitives/non-ALIGN primitives. Anyway, this is limitation of resource as the tools for measure physical signal is expensive and only

42 available at Western Digital in United State. The analyzing parameters of physical signal are not possible to setup the simulation at this point. Instead of analyzing physical signal of physical parameter,

3.6.2. Simulation for logical parameters

Figure 3.26: ModelSim SE implemented Verilog HostPhyInitSM and DevicePhyInitSM The simulation logical parameters by ModelSim SE Student edition [100] by firstly replace the timing parameters into Verilog model to study the effect at each case.

Verilog model implemented considered speed negotiation successfully is implemented as signal detection time less than or equal signal detection allowed. Hdet <= Hadet and Ddet <= Dadet

Hdet is required time for Host to detect OOB, ALIGN or non-ALIGN primitives Hadet is allowed time for Host to detect OOB or ALIGN or non-ALIGN primitives Ddet is required time for Drive to detect OOB or ALIGN primitives Dadet is allowed time for Drive to detect OOB or ALIGN primitives

The experiments to replace (increase) signal detection required time in each detection points by Hdet > Hadet and Ddet > Dadet during speed negotiation was executed one by one to study the scenario of speed negotiation.

Figure 3.27: Results of experiments to replace timing parameters from timing model defined

As 10 results of experiments (Experiments number 57-66), it’s proved that signal detection at the state to detect ALIGN (not lowest speed) between Host and Device is critical to the scenario of speed drop. By consider result of physical parameters combined with logical parameters results to replace timing parameters listed. The physical parameter that has result as cannot communicate is matched with condition of logical parameters (time). To summary the result of experimental related with experimental so far: From results physical parameter (PhyParm) number 1-3, 5-10, 12, 15-17 is matched with either of logical parameters (LogParm) 1, 2, 5-10. We could write as mathematic model as below:

PhyParm[x] = 0; x = 1-3, 5-10, 12, 15-17 LogParm[y] = 0; y = 1, 2, 5-10

PhyParm[x] = LogParm[y] = 0

Then, PhyParm[i] = 1; i = 0, 11, 13, 14 //0 is storage system well-known good conditions LogParm[j] = 1; j = 0 //0 is Verilog designed state machine good conditions

PhyParm[i] = LogParm[j] = 1

Then, PhyParm[m] = -1; m = α // Alpha ( α) is assumed physical parameters cause speed drop. LogParm[n] = -1; n = 3, 4

PhyParm[m] = LogParm[n] = -1

To rewrite time model according to result of experiment:

1 = (Hdet OOB <= Hadet OOBRetryInterval) or (Hdet ALIGN <= Hadet ALIGNRetryInterval) or (Hdet non-ALIGN <= Hadet non-ALIGNRetryInterval) or (Ddet OOB <= Dadet OOBRetryInterval) or (Ddet ALIGN <= Dadet ALIGNRetryInterval) or (Ddet ALIGN 6Gbps > Dadet ALIGNRetryInterval) or (Ddet ALIGN 3Gbps > Dadet ALIGNRetryInterval) 0 = (Hdet OOB > Hadet OOBRetryInterval) or (Hdet ALIGN 1.5Gbps > Hadet ALIGNRetryInterval) or (Hdet non-ALIGN > Hadet non-ALIGNRetryInterval) or (Ddet OOB > Dadet OOBRetryInterval) or (Ddet ALIGN 1.5Gbps > Dadet ALIGNRetryInterval) -1 = (Hdet ALIGN 6Gbps > Hadet ALIGNRetryInterval) or (Hdet ALIGN 3Gbps > Hadet ALIGNRetryInterval)

When: 1 = Expected speed: Such as able to communicate as 6Gbps on Storage System configure to limit to 6Gbps

-1 = Speed drop: Such as able to communicate as 3Gbps on Storage System configure to limit to 6Gbps 0 = cannot communicate The speed negotiation by consider host compatibility is mainly required to focus on signal detection because result of experimental pointed to speed drop and cannot communicate. Those factors are different in various host environments. OOBRetryInterval represent COMINITRetryInterval and COMWAKERetryInterval. Those interval are not actually defined [17][18][19]. OOB specification is only specific signal character of transmit Brust length, transmit Gap length and Gap detection windows. Which allowed the developer to define as infinity or as much as possible. Observed Open- Source SATA Core [49] set COMINITRetryInterval and COMWAKERetryInterval to 0xFFFF (65,535). There are tentative numbers as not defined [17][18][19]. We could consider those OOBRetryInterval as infinity.

At this point, the different of implementation Host by different vendor or called Host compatibility in short could cause simply higher or lower possibility distribution to cause result as cannot communicate.

Few conditions cause cannot communicate (result is 0) can be substitute as: (Hdet OOB > Hadet OOBRetryInterval) become (Hdet OOB > infinity) (Ddet OOB > Dadet OOBRetryInterval) become (Ddet OOB > infinity) Dadet ALIGNRetryInterval is 54.6us [17][18][19] but reduce speed still remain can’t detect ALIGN until end up cannot communicate because HostPhyInitSM will struck at state HR_SendAlign then wait for non-ALIGN primitives. Consider infinity too. (Ddet ALIGN > Dadet ALIGNRetryInterval 6Gbps) become (Ddet ALIGN > infinity) (Ddet ALIGN > Dadet ALIGNRetryInterval 3Gbps) become (Ddet ALIGN > infinity) Hadet non-ALIGNRetryInterval is infinity. (Hdet SYNC > Hdet non-ALIGNRetryInterval) become (Hdet SYNC > infinity)

lim > = 0 →

lim . > = 0 →.

lim > = 0 →

Even ALGINRetryInterval was defined [17][18][19] but it could change to any value depend on host vendor defined. This parameters is should validate when validating Phy initialize state machine implemented by difference vendor as fact from results of experiments. To get character of host implemented to avoid failure at end user.

By consider defined value [17][18][19] in scenario of speed drop to 3Gbps or 1.5Gbps: Hadet ALIGNRetryInterval is 873.8us

The conditions cause speed drop to 3Gbps or 1.5Gbps (result is -1) can be substitute as: (Hdet ALIGN > Hadet ALIGNRetryInterval 6Gbps) become (Hdet ALIGN > 873.8us) (Hdet ALIGN > Hadet ALIGNRetryInterval 3Gbps) become (Hdet ALIGN > 873.8us)

lim > = −1 →.

Again ALGINRetryInterval was defined [17][18][19] but it could change to any value depend on host vendor defined. This parameters should validate when validating Phy initialize state machine implemented by difference vendor as fact from results of experiments. In case results of validation is failed, the device developer could check signal integrity then apply improvement if necessary and initiate communication to host developer for improvement to avoid failure at end user.

CHAPTER 4 SIGNAL DETECTION AND SIGNAL INTEGRITY

The results of experimental defined the signal detection is mainly affected to results of speed negotiation. It’s inspired to study the parameters of signal integrity, noise, electronic design, margin estimation and configuration.

4.1. Signal detection 4.1.1. Signal integrity As per digital designs in past have not suffered by issues associated with transmission line effects. As lower frequencies the signal still has comparable data characterization and system is working as designed. The high speed signal increased in electronics signal transmits from transmitter through SoC package, PCBA board and connection cable until receiver must have signal distorted. [115]

Figure 4.1: Signal distorted from transmitter to receiver in electronics systems/devices

Eye diagram is the technique to get serial data acquired then divided signal into 1 unit segments based on recovered clock using PLL to building eye diagram. [40]

Figure 4.2: Step to build up eye diagram and use case scenario

The use case scenario of eye diagram can provide information on the signal quality as categorized as vertical and horizontal measured information as listed. - Vertical Measurements o Eye Amplitude o Eye Crossing o Eye Height o Eye Level

o Eye Signal to Noise Ratio o Quality Factor o Vertical Eye Opening - Horizontal Measurements o Eye Crossing Time o Eye Delay o Eye Fall Time o Eye Rise Time o Eye Width o Horizontal Eye Opening o Jitter

Figure 4.3: Information from eye diagram

S-Parameters To understand how the channel affects the signals, we can treat the entire channel as a 2- Port Network and just look at the input and output behavior of this network. S-parameters (Scattering parameters) are basically ratios of signal powers that are reflected on transmitted in a port or between two ports in the network [116].

Figure 4.4: S-Parameters of single-ended, 2-port network To measure the S11 and S21 of a DUT, send a signal to the DUT at port 1 and measure the reflection at port 1 and the transmission at port 2. Return loss: S11 – Ratio of reflected signal power at port 1 to input power at port 1(b1/a1) Insertion loss: S21 – Ratio of transmitted power at Port 2 to input power at port 1 (b2/a2)

PHY is an abbreviation for the Physical Layer (the lowest layer) of the OSI model. The PHY connects the Link Layer to a physical medium such as a SATA or SAS cable and defines the means of transmitting raw bits rather than logical data packets. The PHY

48 performs character encoding, transmission, reception and decoding. In western Digital, the Physical Interface Technology team is responsible for the PHY. The PIT team characterizes the PHY to meet the Specification (Spec) or a customer request. Sometimes PIT is referred to as Signal Integrity (SI) because the team also analyzes and mitigates signal degradation to avoid errors or failures.

The study was to understand the Signal integrity measuring report for good drive program on Dec 03, 2012: [113]

Test Equipment: Agilent DSA91304A Digital Signal Analyzer 13Ghz with 6G SATA Compliance Application 1.61 DSA71604 using RT Eye and JIT3 Agilent 81134A Pulse/Pattern Generator Wilder SATA to SMA Test Adapter LeCroy Eagle FE6-1 De-Emphasis Module LeCroy Eagle R6 Clock Synthesizer LeCroy PERT Eagle 6 Analyzer LeCroy PER-AC06-D01-X Eagle De-Emphasis Signal Converter Bertscope Differential Inter Symbol Interference (ISI) Test Board 5 pairs of matching high quality coaxial SMA cables

4.1.1.1. Clock stability / SSC Due to the periodicity of the digital clock signals, the energy concentrates in one particular frequency and also in its odds harmonics. There levels or energy is radiated and therefore this is where a potential electromagnetic interference (EMI) issue arises. Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. [89]

TABLE 4.1: Results of GEN3 SSC test

Figure 4.5: PHY-04[a]: Spread-Spectrum Modulation Deviation (Min) Reference: Test Description: Spread-Spectrum Modulation Deviation specifies the allowed frequency variation from the nominal Fbaud value when Spread Spectrum Clocking (SSC) is used. This deviation includes the long-term frequency variation of the transmitter clock source, and the SSC frequency modulation on the transmitter output. Pass Limits: [-5.350kppm of Fbaud to 350ppm of Fbaud] SSC Modulation Deviation(Min) -2.936kppm of Fbaud

Figure 4.6: PHY-04[d]: Spread-Spectrum Modulation DFDT (Max) Reference

Test Description: Spread-Spectrum Modulation DFDT specifies the maximum short term rate of change (slope) of the spread spectrum modulation profile (df/dt) is within the conformance limit. Pass Limits: <= 1.250kppm/us SSC Modulation DFDT (Max) 231ppm/us

TABLE 4.2: Results of GEN2 SSC test

TABLE 4.3: Results of GEN1 SSC test

4.1.1.2. Receiver As jitter blurs the data edge information in the incoming data stream, it is the dominant contributor to bit Error in clock recovery circuits which are designed to extract the clock information contained in the data. [90] This Jitter Tolerance Mask in figure below is taken from the 10Gbe standard (802.3ae, XAUI) This is also similar with SATA standard definition. The intention for such a jitter mask is to ensure margin for all types of frequency jitter, wander, noise, crosstalk and other variable system effects. Under these conditions a receive circuitry shall run properly for a very low BER In-band Jitter Phase Lock Loop (PLL)/ Cloak-Date-Recovery (CDR) are able to follow, and do not cause eye closure, so this is compensated on the receiver side and does not contribute into the jitter budget. This is the case if the PLL/CDR is able to compensate for >1 UI.

Figure 4.6: Jitter in-band and out-band SATA Specification RX Jitter Tolerance: Gen3 Jitter tolerance Limit (Tj minimum) without SSC: 100ps Gen2 Jitter tolerance Limit (Tj minimum) without SSC: 200ps Gen1 Jitter tolerance Limit (Tj minimum) without SSC: 400ps Minimum Eye Opening: 240mV. Jitter tolerance tested with SSC On.

Gen3 RSG

Gen2 RSG

Gen1 RSG

Table 4.4: Results of RSG at speed GEN3, GEN2 and GEN1

Figure 4.7: Results of Rx Imbalance

Figure 4.8: Results of Rx Differential RL

4.1.1.3. Transmitter

Figure 4.9: Results of Tx Imbalance 53

Figure 4.10: Results of Tx Differential RL

TABLE 4.5: Results of SATA Tx compliant GEN3i

Figure 4.11: Results of TSG-02[b]: Fall Time (Informative) Reference Test Description: Fall times are measured between 20% and 80% of the signal. Fall time requirement tr/f applies to differential transitions (TX+ - TX-), for both normal and OOB signaling. Pass Limits: [33.00ps to 80.00ps] Fall Time (Mode) 53.57ps

Figure 4.12: Results of TSG-03[a]: Differential Skew, HFTP (Informative) Reference Test Description: TX Differential Skew is the time difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX- signal falling/rising edge. It is an important parameter to control as excessive skew may result in increased high frequency jitter and common mode noise levels seen at the far end of the interconnect. Pass Limits : <= 20.00ps Differential Skew, tskew3.84ps

Figure 4.13: Results of TSG-03[b]: Differential Skew, MFTP (Informative) Reference Test Description: TX Differential Skew is the time difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX- signal falling/rising edge. It is an important parameter to control as excessive skew may result in increased high frequency jitter and common mode noise levels seen at the far end of the interconnect. Pass Limits: <= 20.00ps Differential Skew, tskew620fs

Figure 4.14: Results of TSG-04[a]: AC Common Mode Voltage, MFTP Reference Test Description: This specifies maximum sinusoidal amplitude of common mode signal measured at the transmitter connector. This parameter is a measure of common mode noise other than the CM spikes during transitions due to TX+/TX- mismatch and skews which are limited by the rise/fall mismatch and other requirements. Pass Limits: <= 120.00mVAC Common Mode Voltage, Max26.26mV

Figure 4.15: Results of TSG-04[b]: AC Common Mode Voltage, HFTP Reference Test Description: This specifies maximum sinusoidal amplitude of common mode signal measured at the transmitter connector. This parameter is a measure of common mode noise other than the CM spikes during transitions due to TX+/TX- mismatch and skews which are limited by the rise/fall mismatch and other requirements. Pass Limits: <= 120.00mVAC Common Mode Voltage, Max35.20mV

Figure 4.16: Results of TSG-13[a]: RJ before CIC, MFTP, Clock To Data, JTF Defined (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Random Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 180.00mUIRJ before CIC, MFTP, Clock To Data, JTF Defined89.60mUI

Figure 4.17: TSG-13[g]: TJ after CIC, LBP, Clock To Data, JTF Defined (BER=1E-6) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 460.00mUI TJ after CIC, LBP, Clock To Data, JTF Defined (BER=1E-6)115.20mUI

Figure 4.18: TSG-13[f]: TJ after CIC, HFTP, Clock To Data, JTF Defined (BER=1E- 12) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 520.00mUI TJ after CIC, HFTP, Clock To Data, JTF Defined (BER=1E-12)141.10mUI

Figure 4.19: Results of TSG-13[g]: TJ after CIC, HFTP, Clock To Data, JTF Defined (BER=1E-6) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 460.00mUI TJ after CIC, HFTP, Clock To Data, JTF Defined (BER=1E-6)115.60mUI

Figure 4.20: TSG-13[f]: TJ after CIC, MFTP, Clock To Data, JTF Defined (BER=1E- 12) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 520.00mUI TJ after CIC, MFTP, Clock To Data, JTF Defined (BER=1E-12)158.50mUI

Figure 4.21: TSG-13[g]: TJ after CIC, MFTP, Clock To Data, JTF Defined (BER=1E-6) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 460.00mUI TJ after CIC, MFTP, Clock To Data, JTF Defined (BER=1E-6)129.50mUI

Figure 4.22: Results of TSG-13[f]: TJ after CIC, LFTP, Clock To Data, JTF Defined (BER=1E-12) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 520.00mUI TJ after CIC, LFTP, Clock To Data, JTF Defined (BER=1E-12)162.30mUI

Figure 4.23: TSG-13[g]: TJ after CIC, LFTP, Clock To Data, JTF Defined (BER=1E- 6) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 460.00mUI TJ after CIC, LFTP, Clock To Data, JTF Defined (BER=1E-6)136.40mUI

Figure 4.24: TSG-13[f]: TJ after CIC, SSOP, Clock To Data, JTF Defined (BER=1E- 12) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 520.00mUI TJ after CIC, SSOP, Clock To Data, JTF Defined (BER=1E-12)159.30mUI

Figure 4.25: TSG-13[g]: TJ after CIC, SSOP, Clock To Data, JTF Defined (BER=1E- 6) (Informative) Reference Test Description: This specifies the transmitters shall meet the Clock-to-Data jitter measurement specification for Total Jitter with JTF defined. Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. Pass Limits: <= 460.00mUI TJ after CIC, SSOP, Clock To Data, JTF Defined (BER=1E-6)132.80mUI

Figure 4.26: TSG-14: Gen3 (6Gb/s) TX Maximum Differential Voltage Amplitude Reference Test Description: The maximum differential voltage [(TX+) - (TX-)] measured at the Transmitter shall comply to the respective electrical specifications. This is measured at mated Serial ATA connector on transmit side including any preemphasis.For Gen3i and Gen3u the maximum differential output voltage is likewise measured at the TX compliance point. Pass Limits: <= 900.00mV VdiffTX, Max TX Differential Output Voltage 889.70mV

Figure 4.27: Results of TSG-15: Gen3 (6Gb/s) TX Minimum Differential Voltage Amplitude (UI=5E6) Reference Test Description: The minimum differential voltage [(TX+) - (TX-)] measured at the Transmitter shall comply to the respective electrical specifications. This is measured at mated Serial ATA connector on transmit side including any pre-emphasis. The minimum differential output voltage is measured after the Gen3i CIC. Pass Limits: >= Vdiff_Min_Gen3i_LimitV VdiffTX, Min TX Differential Output Voltage 462.65mV

Figure 4.28: Result of TSG-16[a]: Gen3 (6Gb/s) Tx AC Common Mode Voltage, FFT 3Ghz Reference Test Description: Maximum sinusoidal amplitude of common mode signal measured at the transmitter 69 connector. This parameter is a measure of common mode noise other than the CM spikes during transitions due to TX+/TXmismatch and skews which are limited by the rise/fall mismatch and other requirements. The 1st and 2nd harmonics frequency of the data rate shall be measured. Pass Limits: <= 26.00dBmV(pk)(rms) TX AC Common Mode Voltage 8.55dBmV(pk)(rms)

Figure 4.29: TSG-16[b]: Gen3 (6Gb/s) Tx AC Common Mode Voltage, FFT 6Ghz Reference Test Description: Maximum sinusoidal amplitude of common mode signal measured at the transmitter connector. This parameter is a measure of common mode noise other than the CM spikes during transitions due to TX+/TX mismatch and skews which are limited by the rise/fall mismatch and other requirements. The 1st and 2nd harmonics frequency of the data rate shall be measured. Pass Limits: <= 30.00dBmV(pk)(rms) TX AC Common Mode Voltage -8.68dBmV(pk)(rms)

TABLE 4.6: Results of SATA TX compliant GEN2i

TABLE 4.7: Results of SATA TX compliant GEN1

TABLE 4.8: Results of SATA OOB TX compliant test

Figure 4.30: OOB-04 : Drive COMINIT Transmit Gap Length Reference Test Description: Send in-spec nominal COMRESET to Drive. Verify Drive responds with 6 bursts of COMINIT signal with Inter-burst timing in specification. Pass Limits: [310.4ns to 329.6ns] Drive COMINIT Transmit Gap Length 319.6ns

Figure 4.31: OOB-05 : Drive COMWAKE Transmit Gap Length Reference Test Description: Send in-spec nominal COMWAKE to Drive. Verify Drive responds with 6 bursts of COMWAKE signal with Inter-burst timing in specification. Pass Limits: [102.4ns to 109.9ns] Drive COMWAKE Transmit Gap Length 106.3ns

Figure 4.32: OOB-07[a]: Drive Responds to Max In-Spec COMRESET Reference Test Description: Send repetitive max In-Spec COMRESET Gap Windows signal to Drive, verify that the Drive responds consistently with COMINIT to each stimulus. Pass Limits: Valid responses/Invalid responses Drive Responds to Max In-Spec COMRESET 0.000

4.2 Technique to reduce signal integrity issues The theory of high-speed signal travelling through a backplane is significant high- frequency losses, primarily skin effect and dielectric losses. It could make difficult for the receiver to interpret the signal. This effect is referred to an inter-symbol interference (ISI). The technique to reduce/improve those issues was introduced as emphasis, de-emphasis and equalizer.

4.2.1. Emphasis

Pre-emphasis (emphasis as in general term) was introduced to increase high frequency components at transmit domain, it is applying some delay and inversion to the signal, also add it back to the original signal with the proper weight. Transmit Emphasis pre-distorts signal in anticipation of the channel effects at Transmitter side. [26][117][118][119]

Figure 4.33: Basic concept of Pre-emphasis digital filter [117]

4.2.2. De-emphasis De-emphasis suppresses was introduced to suppresses the low-frequency components at the transmitter. Where edge transition (0 to 1 OR1 to 0) occurs, the voltage swing was applied to the symbol after transmitting. The amount of swing voltage reduction called tap weight of the de-emphasis [118]. The comparison of repeating 11110000 pattern between with de-emphasis (tap weight applied 6 dB) and without de-emphasis is as below. [118]

Figure 4.34: 11110000 binary pattern compare without/with de-emphasis 6dB [118]

4.2.3. Equalization

Linear Equalization was introduced to tries to undo channel effects at receiver side by creating an equalizer response that will counteract the channel loss. [117][118] The Linear equalization will boost the high-frequency component of the input stream.

Figure 4.35: Basic concept of Equalization technique

The equalizer is responsible to inverse of the channel response. Then equalized response will be flat. The technique mentioned of reducing signal lose is available at both host transmitter/receiver and drive transmitter/receiver implemented today technology. It is required storage components system developer to analyze their own components when developed to find tune the appropriate configuration. Anyway, the electrical margin was introduce as confidential as of today tend.

CHAPTER 5 HOST COMPATIBILITY TEST

The result of study about speed negotiation for hard disk drive Serial ATA interface was inspired to looks for related test module/test group implemented and executing in Hard Disk Drive Company. The Hardware Compatibility Group (HWC) is the group that validates the compatibility of RAID Controllers / Host Bus Adapters (HBAs) with Western Digital hard drives. Compatibility definition (by HWC) 1. Compatibility testing is defined by exercising the Hard Drive while in the projected customer environment. 2. Tests are intended to exercise the drive from the user perspective. 3. Tests target exercising the SATA/SAS interface.

Hardware compatibility process map is defined as

Figure 5.1: Raid Edition (RE) Compatibility Process Map

After released firmware, partner alliance group will specific hardware that customer is going to use by Western Digital Hard Disk Drive. Then Firmware Integrity Test (FIT) engineer will generate new issue tracking reporting for HWC group to work on executing host compatibility tests and identify either firmware issues or partner issue then notify to issue owner to fix the issue then re-test until complete.

The distribution controller list: (As updated 03/01/2011) ATTO - R380 Promise - FastTrack TX8660 LSI - 9750-8i - 9690A-4i - 9260-8i - 9240-4i - 9211-8i - 8708EM2 - 3442E-R

The test category was separate to: 1. OS Data Integrity 2. Host Chipset Compatibility

5.1. OS Data Integrity The data integrity is accuracy and consistency of stored data, indicated by an absence of any alteration in data. Data integrity compromised as error that occur when data is transmitted from host to drive and firmware or/and hardware malfunctions. The OS Data Integrity will perform write/read and compare the data in variant of OS.

The Operating System for OS Data Integrity : (As updated Aug 10, 2013) - Linux variant distribution o Enterprise distribution: Fedora Core 14, Redhat Enterprise, Mandriva Free Linux 2010.2, OpenSUSE 11.3, SUSE Enterprise Server 11 o Desktop distribution: Ubuntu 11.10 (x86,x64), Debian 6.0, PCLinuxOS, Mint 10 - Windows XP, Vista 7 (x86, x64), Windows Server 2003/2008 Exterprise (x86, x64) - Apple Mac OS X Leopard, Lion, Snow Leopard There are some of the test also perform on variant Host chipset example on Windows 7 for x64 and x86. - Windows 7 x86 w/ SP1 AMD Chipset – 3G Systems - Windows 7 x86 w/ SP1 Intel Chipset – 3G Systems - Windows 7 x86 w/ SP1 NVidia Chipset – 3G Systems - Windows 7 x86 w/ SP1 VIA Chipset – 3G Systems - Windows 7 x64 & x86 w/ SP1 {ATTO 6G SAS} – 6G Systems - Windows 7 x64 & x86 w/ SP1 {LSI 6G SAS} – 6G Systems - Windows 7 x64 & x86 w/ SP1 {Marvell 6G SAS} – 6G Systems - Windows 7 x86 w/ SP1 {ATTO 6G SAS} – Power Cycle / Power Management - Windows 7 x86 w/ SP1 {LSI 6G SAS} – Power Cycle / Power Management - Windows 7 x86 w/ SP1 {Marvell 6G SAS} – Power Cycle / Power Management - Windows 7 x64 Intel Chipset – Nothing is broken (NIB) - Windows 7 x86 Intel Chipset – Non NCQ mode – Nothing is broken (NIB) Note that Power Cycle / Power Management are 200 Cold boots, 200 Warm boots, and 200 S4 Sleep cycles. And when particular OS is outdated, it will be removed from the must test list and replace with new version.

5.2. Host chipset compatibility The compatibility testing is defined by exercising the Hard Drive while in the projected customer environment as well as end-user environment Test list : (As updated Aug 10, 2013) - Partition and Format – Single drive - Warm Boot – Single drive - Cold Boot – Single drive - Sleeper – Single drive - Beatdisk – Single drive - RAID Array Creation – Multiple drive - RAID Partition and Format – Multiple drive - RAID Beatdisk – Multiple drive - At the end of the test FIT Engineer also need to Inspect Log files

Host Chipset Compatibility Validation : (As updated Aug 10, 2013) - SATA o 1.5G Motherboard o 3G Motherboard o 6G Motherboard o 6G&3G Motherboard o 6G Onboard Host o 1.5G Onboard Host o 1.5G Controller Card o 3G Controller Card o 6G Controller Card - SAS o 3G Controller Card o 6G Controller Card - Bridge device o PATA to SATA2 Bridge - 2.5” External Device - 3.5” External Device

Example of chipset of 1.5G/3G/6G/6G&3G Motherboard AMD - NVdia Nforce780i - AMD 970/SB950 - A75 Hudson D3 Intel - Intel Z68 - Intel 82801GR ICH7R - Intel 82801 JR

Software referring for validation : (As updated Aug 10, 2013) Passmark BurnInTest - Assists in PC Troubleshooting and diagnostics. - The fastest CPU Burn In tool around (As CPU Heat Generation benchmark testing) - Avoid delivering D.O.A. (Dead on Arrival) hardware to customers. - Reduce burn in times with multithreaded simultaneous testing of components. - Build image as a supplier of quality systems. - Test the stability of a system after configuration changes or hardware upgrades (critical for overclocking).

Figure 5.2: Screen short of Passmark BurnInTest

Passmark Sleeper - Put a PC into any sleep state (S1, S2, S3) supported by the system - Place PC into hibernation (S4) - Wake the computer after a specified period of time. - Put a PC to sleep or hibernation from the command line - Force the PC into the requested sleep state - Cycle through all sleep states or just all states supported by the system - Launch Sleeper from BurnInTest scripts to test sleep states between test runs. - Display the supported sleep states

Figure 5.3: Screen short of Passmark Sleeper

Passmark Rebooter - Shutdown, Reboot or Logout of a PC. - Reboot a PC from the command line - Set a timer so that the PC will reboot after a certain amount of time - Setup a reboot loop, to reboot a PC over an over again in a cycle. - Force a shutdown or request a shutdown. - Enable and disable the Windows auto-login feature. (NT/2000/XP only) - Include reboots into your hardware stress testing plan, (when used with BurnInTest).

Figure 5.4: Screen short of Passmark Rebooter

Figure 5.5: Example of test case and result of test

Observed, test listed is specific to identify error by simulate user activities. Anyway, there is no specific result of speed negotiation drop provided. But the result of cannot communication can indirectly found by hard disk drive can’t detect. To create software to check and report the result of speed negotiated success after power up completed is the simple way to measure speed negotiation where by matching product firmware with new arrival hardware. The huge requirement is hardware and operating system is required to update often to catch the market growth. Software must support every single new hardware and operating system in the market.

Options of improvement HCC test to cover speed negotiation drop were listed: - To develop software to check and report the result of speed negotiated success after power up completed - To develop hard disk drive firmware to take a note of speed negotiation completed/in-completed during test the report via log file that will be check by FIT engineers. - To develop FPGA system that able to transform itself to be a hard disk drive to listen to signal profile and speed negotiation activity has been done by each new system then replay the speed negotiation activity again to Western Digital hard disk drive to validate expected speed negotiation.

Unfortunately, HCC rejected to execute any experimental request to get information. Any execution must be official request that get approved by resource management because it consume multiple of technicians and engineers working hours in Irvine, United states to execute all possibility host and drive. The software that supports every platform is required long term plan to develop and allocate resource to validate.

CHAPTER 6 CONCLUSION AND RECOMMENDATION

The first and second experimental on measuring S-parameters on defected SoC and impedance of defected cable cause communication issue by look at TDR profile compared with good and NG showed the possibility of physical components cause the communication issue by physical parameters instead of the pure logical parameters as initiated idea of research. The third experiment until experiment 56 th showed physical parameters identified is mainly effect to communication. It’s not actually provided the speed negotiation drop. The experiment 57-66 th pointed to the reason. It is because identified physical parameters is affected to signal integrity issues that cause OOB signal can’t be detected and actually not reached the point that negotiated speed by ALIGN primitives. It’s difficult to define the physical parameters that only cause signal integrity at primitives but not cause signal integrity at OOB. Anyway, logical parameters simulation by replacing additional delay when signal detection period both OOBs and primitives showed the fact that signal detection issue could happen when receiver try to detect primitives cause speed drop is possible but the logic implementation by referring to old spec without restriction to define duration time to be aware by Host or Device can happen more easily. This information must be warned to Host and Device developer to avoid problem found. As NWay Solution idea implemented on Ethernet since 1994 [106], the idea introduced to allow both automatic and manual configuration capabilities. From result of experimental of this research, SATA software driver should provide the simple idea of manual configurable speed negotiation via general driver software that going to control host and/or device to be able to configure to be maximum capability to avoid automatic speed negotiation that might face the problem cause by multiple factors listed in this research. Even Ethernet Auto negotiation Best Practices [107] was provided information to strongly recommend to move default of configuration to be auto negotiation instead of leaves it manual because many years passed should guaranty that speed negotiation already reliable enough any those interoperability issues already fixed. Anyway, the best practices also provide a hint that when disabled auto negotiation, both ends of the link must match configuration [107]. Since maximum of SATA is known 6Gbps onward and lower are only 3Gbps and 1.5Gbps. It’s not much overhead for administrators and end users to remember motherboard and hard disk drive capability to be able to configure the maximum SATA speed. The driver software to install at host could refer to model to validate physical parameters defined in this research to implement the capability to validation the speed negotiation in very beginning of attached storage device (hot-plug) then keep monitoring speed negotiation is expected or not expected. Driver software could refer to identify device command response word 222 to get expected speed SATA1.x is 1.5Gbps, SATA2.x is 3Gbps and SATA3.x is 6Gbps by definition. At the same time driver software could check AHCI registers PxSCTL.SPD for expected speed at host site then PxSSTS.SPD and PxSSTS.DET for results of speed negotiated. When driver software not received expected result then report warning message to administrators or end users to check their own system setup and feedback to vendor to help on compatibility as combination of storage system. In parallel, hard disk drive Company as western digital could also apply this idea to validate at host compatibility test group for validating cover all possibility hosts defined. This is to avoid customer experience performance lower than expected and communication issues related with speed negotiation and to be lead in storage business in term of reliability of the storage product.

Regarding the state machine implemented, the developer could also refer to development kit [72][79][80] to simulate the logic to validate before implementation and after implemented. The main concept of validate before implementation could replace similar to logical model to simulate the scenario that will happen in the field. The concept of validate after implemented could also refer to development kit to simulate the possibility of causes listed in logical parameters to validate the response of worst case scenario. Another idea found during experiment the logical parameter is to feedback from Phy initialize state machine to re-configuration to improve SATA Phy configuration but as of today SATA hardware configuration, there is no feedback directly from Phy layer to higher layer to decide to improve the configuration as of SATA was designed based on concept that each layer should not work on another layer’s tasks. This means Application layer who actually provide configuration of Phy layer is not actually get any feedback directly from Phy layer (Phy initialize state machine was implemented at Phy layer) to be able to re-program the better value to improve and look for result at next round of speed negotiations. Anyway, this effort required many communication that can’t finished with in few years because each group (SoC designer, electronics hardware designers, and firmware designer) must be one together to accomplished this idea. Lastly, disk I/O was defined as bottlenecks in storage system since 2006 [121] and there are efforts to replace hard disk drive by solid state drive [122]. To consider growth market chair by maximize reliability and performance by consider implementing additional device driver and validation speed negotiation by hard disk drive company will leading hard disk drive still holding growth market chair as expected by business standpoint.

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