Isbc® 215 WINCHESTER DISK CONTROLLER HARDWARE REFERENCE MANUAL
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iSBC® 215 WINCHESTER DISK CONTROLLER HARDWARE REFERENCE MANUAL Copyright © 1980, 1981 Intel Corporation Intel Coporation, 3065 Bowers Avenue, Santa Clara, CA 95051 Order Nu mber: 121593-002 iSBC 21S™ WINCHESTER DISK CONTROLLER HARDWARE REFERENCE MANUAL Order Number: 121593-002 Copyright (el 1980, 1981 Intel Corporation I Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051 I REV. REVISION HISTORY PRINT DATE -001 Original Issue 1181 -002 Manual updated for mInor corrections. 9/81 - Additional copies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this document. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9(a)(9). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products: BXP Intelevision Micromap CREDIT Intellec Multibus i iRMX Multimodule ICE iSBC Plug·kBubble iCS iSBX PROMPT im Library Manager Promware INSITE MCS RMXIRO Intel Megachassis System 2000 Intel Micromainframe UP! IlScope and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or RMX and a numerical suffix. ii PREFACE This manual provides information regarding the installation, programming, operation, and servicing of the iSBC 215™ Winchester Disk Controller. Related documents include: • The 8086 Family User's Manual, Order No. 9800722 • Intel MULTIBUgrM Specifications, Order No. 9800683 • Intel 8080/8085 Assembly Language Reference Manual, Order No. 9800301 • MCS-86™ MACRO Assembly Language Reference Manual, Order No. 900640 • MCS-86/85TM Family User's Manual, Order No. 121506 • 8089 Assembler User's Guide, Order No. 9800938 • iSB)(fM Bus Specification, Order No. 142686 • iSBX 218™ Flexible Disk Controller Hardware Reference Manual, Order No. 121583 iii CONTENTS CHAPTER 1 GENERAL INFORMATION Page Page Introduction .................................... 1-1 Execute iSBX I/O Program .................. 3-16 Description ..................................... 1-2 I/O Transfer Through iSBX Bus ............ 3-16 Specifications ................................... 1-3 Buffer I/O ................................... 3-17 Diagnostic ................................... 3-18 CHAPTER 2 Posting Status ................................. 3-18 PREPARATION FOR USE Transfer Error Status .......................... 3-19 Introduction .................................... 2-1 Interrupts ...................................... 3-20 Unpacking and Inspection ...................... 2-1 Controlling Data Transfer Board Installation Considerations .............. 2-1 Through the iSBX Bus .................... 3-20 Power Requirement ........................... 2-2 I/O Transfers Using iSBC 215 Cooling Requirement ......................... 2-2 Controller Resident Firmware .............. 3-20 Multibus Connector ............................. 2-2 Data Transfer Using User Written Switch/Jumper Configurations ................. 2-2 I/O Transfer Programs .................... 3-20 Wake-Up Address Selection ................... 2-6 Example Controller I/O Program .............. 3-23 Wake-Up I/O Port Address Selection ......... 2-7 System Data Bus Selection ................... 2-7 CHAPTER 4 Interrupt Priority Level ....................... 2-7 PRINCIPLES OF OPERATION Any Request Selection ........................ 2-7 Introduction .................................... 4-1 Common Bus Request .......................... 2-7 Schematic Interpretation ........................ 4-1 Winchester Drive Interface ..................... 2-7 Functional Overview ............................ 4-2 -5-Volt Selection Detailed Functional Description ..... .. 4-5 (8" Shugart/Quantum Drives Only) ........... 2-8 Controller to Host Communications ............. 4-6 Cabling Requirements ........................ 2-8 Multibus Interface .............................. 4-6 Drive Installation ............................. 2-9 8089 I/O Processor (lOP) ....................... 4-6 iSBX Multimodule Interface ................... 2-22 Clock Circuit ................................... 4-6 iSBX 218 Board Installation ................... 2-23 Bus Arbiter ..................................... 4-7 Power Up/Down Considerations ............... 2-24 Bus Controller Logic ............................ 4-8 Diagnostic Check .............................. 2-24 Multibus Interface Data Transfer Logic ........................ 4-8 CHAPTER 3 Controller Initialization ......................... 4-8 PROGRAMMING INFORMATION Wake-Up Address Comparator .................. 4-9 Introduction .................................... 3-1 Controller Reset and Clear .................. 4-10 Programming Options .......................... 3-1 Establishing A Link With Disk Organization .............................. 3-1 I/O Communications Blocks ............... 4-10 Track Sectoring Format ........................ 3-2 Interrupt Priority Logic ........................ 4-11 Controller I/O Communications Blocks ......... 3-2 Local Memory Map ............................ 4-11 Host CPU-Controller-Disk Drive Interaction .... 3-4 ROM .......................................... 4-11 Wake-Up I/O Port .............................. 3-4 RAM .......................................... 4-11 Wake-Up Block ................................. 3-4 Local Memory Mapped I/O Ports Channel Control Block ......................... 3-4 and iSBX I/O Ports ....................... 4-11 Controller Invocation Block ..................... 3-4 Controller to Disk Drive Communications ..... 4-12 I/O Parameter Block ........................... 3-4 Controller to Winchester Typical Controller Operations . .. 3-6 Disk Drive Interface ....................... 4-12 Initializing the Controller ..................... 3-6 Control Cable Signals ......................... 4-13 Track Formatting ............................. 3-9 Read/Write Cable Signals ..................... 4-14 Alternate and Defective Track Handling ..... 3-12 Controller to iSBX Connector Interface ........ 4-14 Data Transfer and Verification .............. 3-12 Controller to Disk Drive Interface Timing ..... 4-15 Read Sector ID .............................. 3-13 DMA Mode .................................. 4-15 Read Data ................................... 3-13 Disk Formatting ............................. 4-16 Read Data Into Controller Buffer and Verify 3-14 Write Data Transfer ......................... 4-18 Write Data .................................. 3-15 Read Data Transfers ........................ 4-20 Write Data from Controller Buffer to Disk '" 3-15 SER/DES Logic ............................... 4-20 Initiate Track Seek .......................... 3-15 Sync Byte Comparator Logic ................ 4-21 IV CONTENTS (Continued) Page Page 32-Bit ID Comparator Logic ................... 4-21 Service and Repair Assistance .................. 5-1 ECC Generator Logic .......................... 4-21 Self Diagnostic ................................. 5-1 Status Ftegister Logic .......................... 4-21 Replaceable Components ........................ 5-1 Line Drivers and Fteceivers .................... 4-22 CHAPTER 5 APPENDIX A SERVICE INFORMATION HANDSHAKE SEQUENCES AND Introduction .................................... 5-1 EXAMPLE HOST PROCESSOR Service Diagrams ............................... 5-1 DISK CONTROL PROGRAM TABLES T~~ TI~ ~~ Table Title Page 1-1. Board Specifications ...... .. 1-3 3-4. iSBC 215 Controller RAM 1-2. Winchester Disk Drive Available for Program and Characteristics ....................... 1-5 Parameter Storage .................. 3-22 2-1. Multibus Connector PI 3-5. 8089 Handshake and Control Lines Pin Assignment ...................... 2-2 on the iSBX Bus .................... 3-22 2-2. iSBC 215 Controller/Multibus 3-6. Control and Status Lines Interface PI Signal Descriptions ..... 2-3- on the iSBX Interface ............... 3-23 2-3. iSBC 215 Controller/Multibus 3-7. Jumper Connections Allowing Option Interface Signal Characteristics ...... 2-6 Lines to be Driven .................. 3-23 2-4. Configuration Jumpers and Switches .. 2-7 4-1. 8089 Status Line Decodes .............. 4-8 2-5. Interrupt Priority Level Selection ...... 2-7 -4-2. Host Wake-Up Commands ............. 4-9 2-6. Winchester Drive 4-3. Local 110 Ports ....................... 4-12 Manufacturer Selection ............... 2-8 4-4. iSBX Bus 110 Port Addresses ......... 4-12 2-7. -5-Volt Selection ... .. 2-9 4-5. Control Cable Line Functions ......... 4-13 2-8. J3 and J4 Pin Assignments ........... 2-22 4-6. Read/Write Cable Line Functions ..... 4-14 2-9. iSBX Bus Control Jumper Pins ....... 2-24 4-7. iSBX Bus Mnemonics-to-Controller