University of Florida EEL 3701 — Fall 2018 ECE Department Dr. Gugel

LAB 8: Elementary Central Processing Unit (CPU) Design

OBJECTIVE IR1:0 Action The objective of this lab is to design and implement an elementary central processing unit (CPU) based on the 00 Move REGA’s contents to REGB CPU designed in Lab 6. You will implement a 2-bit 01 Load REGA with data on INPUT bus instruction field will be used to control a simple state 10 Rotate REGA Left by 1 bit machine that in turn will be used to set the mux lines in 11 Add REGA + REGB + Cin the ALU according to what type of instruction is Table 3. IR Instructions Set designated for execution. MATERIALS Instruction Register (IR) Design Proto-Board, Wires, Switches, LEDs, & CPLD The IR is a 2-bit storage register with a synchronous Part I - INTRODUCTION - LAB CPU IR.LD input. When IR.LD = T, data is loaded into the The ALU designed in Lab 6 consisted of four 4:1 register at the next active clock transition. When IR.LD= muxes on the inputs of REGA (A) and four 4:1 muxes F, the register contents are held. This register can be on the inputs of REGB (B). The select lines for these simply realized with a 2:1 mux on the input of each flip- muxes were designated MSA1:0 and MSB1:0, flops of the IR. When the 2:1 mux select line is low, respectively. For a quick review, the muxes selected select the IR outputs back to the IR inputs and when a bus in the following manner. the select line is high, run the INPUT bus signals to the inputs of the IR. Bus Selected as PRE-LAB REQUIREMENTS MSA1/ MSA0/ Input 1. Convert the flowchart in Figure 2 into an ASM MSB1 MSB0 to REGA/REGB diagram; i.e., put in the actual mux select signals in 0 0 INPUT Bus the ASM diagram and make sure the timings are 0 1 REGA Output Bus correct. Use the minimum number of states. 1 0 REGB Output Bus Hint: use conditional outputs. 1 1 OUTPUT Bus 2. Create a Next State truth table for the IR controller. Table 1. MUX A and B settings. 3. Create the IR controller as a symbol block to work with the symbol block that will be your Lab 6. The The outputs of REGA and REGB were then passed controller circuitry can be implemented graphically to a combinatorial logic block and the results of this or with VHDL. If you choose to implement it were then passed to four 8:1 muxes. The select graphically, K-maps must be done with to find the lines for these four muxes were designated as MSOP or MPOS. If you choose VHDL you do not MSC2:0. For review purposes, these (3) lines need to use K-maps or simplify your equation. selected the following. 4. Run a Quartus simulation to test all instructions created in the controller circuitry. In your Quartus MSC2:0 Action simulation show the values of REGA and REGB. 000 Complement of REGA Bus to the OUTPUT Bus 5. Include all BDF and VHDL code in your report. 001 REGA Bus AND REGB BUS to the OUTPUT 6. Download your design to the breakout board. 010 REGA Bus OR REGB BUS to the OUTPUT 7. Connect the 7 Segment Display and switches to 011 REGA Bus to the OUTPUT Bus the breakout board; verify it functions as specified 100 REGB Bus to the OUTPUT Bus in the Pre-Lab Requirements. Reg A & B should Shift REGA Bus right one but to the OUTPUT be displayed as before on the Dual 7 Segment 101 without sign extension Display, which must match the truth table that was 110 shift REGA Bus left one bit to the OUTPUT Bus originally given in lab6_7SegDecoderdesign.pdf. 111 REGA + REGB + Cin to the OUTPUT Bus & Cout IN-LAB REQUIREMENTS Table 2. MUX C settings. Demo your lab by demonstrating a function that will be provided by your TA. INTRODUCTION – IR CONTROLLER HELPFUL HINTS A state machine controller and Instruction Register If something does not function as expected, look (IR) are now added to the ALU to facilitate the through your design where an error may occur, so this execution of simple instructions. See Figure 1 for the can isolate the error. A useful tool for debugging a total system components. The IR register contains design is to add outputs for some of the internal signals, 2-bits which represent the four instructions in Table 3. i.e., signals that are neither outputs nor inputs of your A flowchart for the Controller is shown in Figure 2. You design. This will assure to you each signal is operating are to convert the flowchart into an ASM diagram. as expected.

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University of Florida EEL 3701 — Fall 2018 ECE Department Dr. Gugel

LAB 8: Elementary Central Processing Unit (CPU) Design

POINT BREAKDOWN • Pre-lab Materials (ASM chart, Controller design) 10% • In-lab Demo a function designed in lab 30% • Pre-lab Simulation Results 10% • In-lab Quiz 50%

RESET INPUT3:0 OUT3:0 INPUT3:0 Lab 6: A-G CPU and RESET MSA1:0 Cout 7-Segment INPUT1:0 MSB1:0 LE0 IR1:0 Decoder IR Controller LE1 MSC2:0

IR.LD IR.LD

Clock Cin

Figure 1. System Components.

Note1: When not specified, the default actions for Load IR register with each state is to “hold” INPUT1:0 (i.e., next REGA and REGB and op code) at the next OUT = REGA. active clock edge.

Note2: Reset is used to set all registers/flip-flops to a known (zero) state. Decode op code

00 01 IR1, IR0 10 11

(Set INPUT = new data) Set muxes to sum Set muxes to transfer Set muxes to left shift Set muxes to load REGA+REGB+Cin into REGA into REGB INPUT Data into REGA REGA*2 into REGA REGA

Figure 2. Flowchart for the Controller.

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