A System Level Approach to the Design and Analysis of PCB

ABSTRACT

ABERG, BRYCE. An Approach for the Design and Analysis of PCB Busbars in High Power SiC Inverters using FEA Tools. (Under the direction of Iqbal Husain).

Wide band gap semiconductors, including silicon carbide (SiC) and gallium nitride (GaN), allow engineers to develop higher power density systems compared to traditional Si technology. Silicon Carbide, in particular, has promising applications to the automotive, aerospace, and utilities industries among others. Commonly used to create solid electrical and mechanical connections in high power systems, busbars are critical in ensuring system reliability in terms of voltage spike and temperature rise. Laminated busbars, commonly consisting of heavy copper planes separated by a non-conductive substrate, are widely used in industry due to their mechanical, electrical, and thermal robustness. Printed circuit boards (PCB) have advantages over laminated busbars in developing high power density systems. While the optimization of laminated busbar design has been widely reported, high power PCB busbars are less represented in literature. Therefore, a simulation-based methodology used to analyze and optimize the design of PCB busbars using finite element analysis (FEA) tools will be discussed. Two systems were considered for these studies including a 135 kW SiC traction inverter and a 125 kVA SiC inverter used in an active harmonic filter. Components comprising the power loop, including the PCB busbar, power module, and heavy duty interconects were modeled in Q3D to extract the loop inductance for both systems. The two experimental methods used to validate simulation results included double pulse tests (DPT) and impedance measurements. The busbar design in the 135 kW system was optimized using Ansys Q3D, resulting in a 19 % reduction in voltage spike amplitude according to double pulse tests. The loop inductance in the 135 kW system was also measured using an impedance analyzer and there was a less than 5 % difference between measured and simulated inductance values. These experimental results validated the simulation-based approach to analyzing PCB busbars and these same methods were applied to the PCB bussing system in the 125 kVA inverter during the project’s design phase. The study of the 125 kVA SiC inverter’s PCB busbar included an analysis of its design to determine its effect on the system in terms of voltage spikes and temperature rise. The methods from the previous section were extended to demonstrate how the extracted loop inductance from Q3D can be used to define the minimum required decoupling capacitance for a system. The FEA analysis approach was extended to include a thermal-electric simulation to verify the PCB busbar will have an acceptable worst-case temperature rise. Extracted loop inductance from impedance measurements agreed with simulation results, indicating FEA analysis of parasitic loop inductance can have acceptable accuracy. By analyzing two different systems, this simulation-based analysis approach was shown to be appropriate for analyzing specific reliability metrics for any high power system utilizing a PCB busbar. © Copyright 2018 by Bryce Aberg

by Bryce Aberg

A thesis submitted to the Graduate Faculty of North Carolina State University in partial fulﬁllment of the requirements for the Degree of Master of Science

Electrical Engineering

Raleigh, North Carolina

2018

APPROVED BY:

Wensong Yu Douglas Hopkins

Iqbal Husain Chair of Advisory Committee DEDICATION

I dedicate this document to my family: Pete, Judy and Tyler Aberg and also to my exceptional girlfriend, Lauren Ervin. It is for these people whom I want to improve the world and I am privileged to have their full support.

ii BIOGRAPHY

The author was raised outside of Portland, Oregon before his family moved to Nashville, TN when he was 10 years old. Throughout school, he enjoyed learning about math and languages which lead him to take an interest in computer science starting in middle school. As a teenager, he watched his father work on various personal projects around the house and in the garage. This lead him to pursue electrical engineering at Western Kentucky University, where he graduated with his Bachelor’s in 2016. While at WKU, he had internships with NASA at the Kennedy Space Center in Florida and the Armstrong Flight Research Center in California a total of four times. These internships were crucial in developing his passion for engineering, aviation, and aerospace which lead him to pursue a graduate degree at North Carolina State University. Starting in 2017, the author was a Research Assistant at the Future Renewable Electric Energy Delivery Management (FREEDM) Systems Engineering Research Center and was also an intern at Northrop Grumman. After graduating with his Master’s in Electrical Engineering from NCSU, the author will join Boeing Commercial Aviation in Seattle, WA as an Electrical Engineer.

iii ACKNOWLEDGEMENTS

First, I want to thank my advisor Dr. Iqbal Husain and Dr. Wensong Yu. Their technical guidance on my work and research allowed me to grow as an engineer during my time here at NCSU. I want to give a huge thank you to Dr. Radha Sree Krishna Moorthy; working with her was an absolute pleasure and I am proud of what we accomplished together. I also want to thank Dhrubo Rahman and Li Yang, whose advice and guidance was appreciated. I also extend gratitude to both Marshal Ollimah and Dr. Andrew Lemmon, without whom some of the experimental results would not be possible. I want to thank my professors from WKU: Dr. Fahrad Ashrafzadeh, Dr. Walter Collett, and Dr. Sanju Gupta. Their belief in me as a student and advice were important factors in my decision to pursue graduate school. I want to acknowledge the NC Space Grant for ﬁnancial support during Summer 2018. Finally, I want to acknowledge Power America for funding the projects described herein.

iv TABLE OF CONTENTS

List of Tables ...... vii

List of Figures ...... viii

Chapter 1 Introduction ...... 1 1.1 High Power Voltage Source Inverters Utilizing Silicon Carbide Semiconductors...... 1 1.1.1 Comparison of Semicondcutor Technology in High Power Inverters...... 1 1.2 Research Motivation and Objectives...... 2 1.3 Thesis Organization...... 3

Chapter 2 Study Approach ...... 4 2.1 Introduction ...... 4 2.2 Literature Review...... 4 2.2.1 Busbar Technology...... 4 2.2.2 A Review of Busbar Analysis and Optimization Literature...... 5 2.3 Busbar Analysis Approach ...... 7 2.3.1 Deﬁnition of Loop Inductance...... 7 2.3.2 Parasitic Inductance Theory ...... 9 2.3.3 Parasitic Capacitance Theory ...... 10 2.3.4 Parasitic Resistance Theory...... 12 2.3.5 Parasitic Extraction using Finite Element Analysis ...... 12 2.4 Experimental Validation...... 13 2.4.1 Extraction of Loop Inductance using Impedance Measurements...... 13 2.4.2 Switching Characterization using the Double Pulse Test...... 16

Chapter 3 Modeling, Minimization, and Measurement of Parasitic Loop Inductance for a 135 kW EV Inverter ...... 19 3.1 Introduction ...... 19 3.1.1 System Overview ...... 19 3.2 High Power PCB Busbar Design ...... 22 3.2.1 High voltage sustainability ...... 22 3.2.2 High current conducting capability...... 22 3.2.3 Power loop inductance...... 23 3.2.4 Heavy Duty Interconnect Design...... 25 3.3 Parasitic Inductance Extraction of the Major Components of the Power Loop ...... 25 3.3.1 Modeling of the SiC Power Module ...... 26 3.3.2 Modeling of the PCB Busbar-A and the Interconnects...... 27 3.3.3 Decoupling Loop Inductance with Busbar-A ...... 28 3.4 Optimization of Busbar Design for Minimal Loop Inductance ...... 29 3.5 Experimental Results...... 33 3.5.1 Loop Inductance Extraction using an Impedance Analyzer...... 33 3.5.2 Switching Characteristics using the Double Pulse Test ...... 35 3.5.3 DPT Simulation ...... 37

v 3.6 Benchmark Comparison ...... 38 3.7 Discussion...... 39 3.7.1 Measurement Adapter Design Lessons Learned...... 40

Chapter 4 Design and Analysis of a PCB Busbar System for a 125 kVA SiC Inverter ...... 44 4.1 Introduction ...... 44 4.2 System Overview...... 44 4.3 Local Busbar Design...... 45 4.3.1 Optimized Heavy Duty Interconnect Design ...... 46 4.4 Design Analysis using FEA ...... 49 4.4.1 Model Preparation for FEA Analysis...... 49 4.4.2 Decoupling Power Loop Parasitic Extraction ...... 50 4.4.3 Required Decoupling Capacitance...... 51 4.4.4 DPT Simulation ...... 54 4.4.5 Local Busbar Thermal-Electric Analysis...... 56 4.4.6 Power Loop Inductance Measurement PCB Design and Analysis...... 59 4.5 Experimental Results...... 63 4.5.1 Parasitic Inductance Extraction using Impedance Measurements...... 63 4.6 Discussion...... 64

Chapter 5 Conclusion ...... 66 5.1 Summary...... 66 5.1.1 PCB Busbar Design and Analysis Methodology...... 67 5.1.2 The Role of Busbar FEA Analysis in System Design and Analysis...... 69

APPENDICES ...... 74

vi LIST OF TABLES

Table 1.1 Comparison of a SiC MOSFET inverter and Si IGBT inverter...... 2

Table 2.1 Compensation Parameters in Eq. (2.18) [23] ...... 16

Table 3.1 NCSU 135 kW EV Inverter System Speciﬁcations ...... 20 Table 3.2 Extracted Module Parasitics at 10 MHz ...... 28 Table 3.3 Summary of Q3D Results for Busbar Design Iterations...... 32 Table 3.4 Loop Inductance Results Summary...... 35 Table 3.5 DPT Results (800 V bus voltage)...... 35 Table 3.6 DPT Simulation Results (800 V, 220 A)...... 38 Table 3.7 System Comparison between NCSU Inverter and Benchmark Inverter[41] . . . . . 38 Table 3.8 DPT Comparison between NCSU Inverter and Benchmark Inverter [41] ...... 38

Table 4.1 Summary of Heavy Duty Interconnect Design Iterations...... 49 Table 4.2 Decoupling Loop Inductance Extraction Considering Different Phases ...... 50 Table 4.3 DPT Simulation Results for Different Decoupling Capacitance Values...... 55 Table 4.4 Assumed thermal conductivity of thermal-electric simulation materials...... 58 Table 4.5 Busbar Measurement PCB Analysis Summary ...... 62 Table 4.6 Local Busbar Extracted Inductance Summary ...... 64

vii LIST OF FIGURES

Figure 2.1 Equivalent circuit for the power loop in a single-phase of an inverter...... 8 Figure 2.2 A single-turn rectangular loop around an air core...... 10 Figure 2.3 A simple parallel plate capacitor ...... 11 Figure 2.4 Current loop for measurement...... 14 Figure 2.5 Impedance analyzer speciﬁcation...... 15 Figure 2.6 Connection block diagram for an impedance analyzer, measurement adapter, and DUT...... 16 Figure 2.7 A DPT Circuit for Measuring Voltage Spike of a Half-Bridge Circuit ...... 17 Figure 2.8 Example of a DPT gating signal (red) and load inductor current (green)...... 17

Figure 3.1 System level overview for the 135 kW SiC EV traction inverter...... 20 Figure 3.2 Three-phase half-bridge topology for the inverter...... 20 Figure 3.3 135 kW EV Inverter Solidworks Model ...... 21 Figure 3.4 Single phase half-bridge showing power loop current paths...... 22 Figure 3.5 Busbar layer stack showing layer number and nets...... 23 Figure 3.6 PCB busbar-A design for the 135 kW SiC inverter with 1 kV DC-link...... 24 Figure 3.7 (a) Heavy duty interconnect, (b) the connectors on the module...... 25 Figure 3.8 Internal layout of the 1.2 kV SiC power module...... 26 Figure 3.9 Current in the distribution the 1.2 kV SiC power module...... 27 Figure 3.10 Equivalent circuit representing the stray inductances in the module between the DC+ and DC- terminal...... 27 Figure 3.11 (Left) Current distribution in path involving the DC link capacitors (Loop 2) in the busbar and (right) current distribution involving the decoupling capacitors (Loop 1) in busbar PCB...... 28 Figure 3.12 Heavy duty interconnect current density for 150 A, showing a maximum of 250 A/c m 2...... 29 Figure 3.13 (a) Current path in in the busbar and decoupling capacitor current loop, (b) DC current density in decoupling capacitor current loop at 100 A. Notice the hot spots in the top two ceramic capacitors. Note the AC layers in the busbar and middle terminal in the module were eliminated in (a) for clarity...... 30 Figure 3.14 PCB busbar-B...... 31 Figure 3.15 PCB busbar-C...... 32 Figure 3.16 Adapter compensation measurement...... 33 Figure 3.17 Busbar-A impedance measurement...... 34 Figure 3.18 Busbar-C impedance measurement...... 34 Figure 3.19 Left: Full DPT waveforms. Right: VDS and VGS at turn-off. DPT waveforms with a 800 V source and 220 A at turn-off for (a) busbar-A with only DC-link capacitors, (b) busbar-A with DC-link and decoupling capacitors, and (c) busbar-C with DC- link and decoupling capacitors installed. Scaling for VDS in (b) was incorrectly set to 100 V/div, while the others are are 250 V/div...... 36

viii Figure 3.20 DPT simulation results showing VDS (green) and VGS (red) for the lower switch of the half-bridge module in a run with a 800 V source and 220 A at turn-off. (a) Busbar-A: 871 V peak (b) busbar-C: 850 V peak ...... 37 Figure 3.21 (Left) 135 kW NCSU Inverter and (right) 250 kW Benchmark Inverter [41] . . . . . 39 Figure 3.22 Measurement adapter designs...... 40 Figure 3.23 Measurement adapter V2 ...... 41 Figure 3.24 Circuit diagram showing the current path in the impedance measurement. The decoupling capacitors were shorted using copper strips...... 42

Figure 4.1 Wolfspeed’s 1.2 V Six-Pack power module...... 45 Figure 4.2 Wolfspeed’s 1.2 V Six-Pack power module...... 45 Figure 4.3 (a) Local busbar layout highlighting the top (DC+) layer, (b) local busbar layout highlighting the bottom (DC-) layer and pads for small ceramic decoupling capacitors near the DC source terminals...... 47 Figure 4.4 (Top)reference connector, (a) connector design A, (b) connector design B, (c) connector design C...... 48 Figure 4.5 Assembled power module and local busbar showing "plug-n-play" conﬁguration. 49 Figure 4.6 FEA model showing local busbar and power module used in Ansys Q3D for parasitic inductance extraction...... 50 Figure 4.7 Current density of phase A/C and the local busbar from Ansys Q3D at 50 ADC . . . 51 Figure 4.8 Current density of phase B and the local busbar from Ansys Q3D at 50 ADC . . . . . 51 Figure 4.9 Equivalent circuit of parasitic inductance in a single leg of an inverter with DC-link and decoupling capacitors...... 52 Figure 4.10 Decoupling Impedance Analysis ...... 54 Figure 4.11 DPT simulation results for the power loop in the 125 kVA inverter for (a) no decoupling capacitor and (b) CDEC = 39.3 nF...... 56 Figure 4.12 Thermal-electric simulation model...... 57 Figure 4.13 Thermal-electric simulation results...... 59 Figure 4.14 Diagram highlighting where three separate loops in the system will be broken to measure their inductance using the ZA and measurement PCB...... 60 Figure 4.15 Design 1: Loop inductance measurement PCB layout. Numbered annotations refer to the numbered loops in Fig. 4.14...... 60 Figure 4.16 Ansys Q3D model of the power module with the measurement PCB attached. . . . 61 Figure 4.17 Design 2: Loop inductance measurement PCB layout. Numbered annotations refer to the numbered loops in Fig. 4.14...... 62 Figure 4.18 Impedance analyzer results using the local busbar measurement PCB...... 63 Figure 4.19 Impedance analyzer results using the local busbar measurement PCB...... 64

Figure 5.1 Block diagram describing an iterative busbar design process using simulation tools. 68 Figure 5.2 Modeling levels of electrical systems. Adapted from [40]...... 69 Figure 3 Heavy Duty Interconnect for the 135 kW SiC EV Inverter...... 77 Figure 4 Heavy Duty Interconnect Design A for a 125 kVA SiC Inverter Local Busbar . . . . . 77 Figure 5 Heavy Duty Interconnect Design B for a 125 kVA SiC Inverter Local Busbar . . . . 78 Figure 6 Heavy Duty Interconnect Design C for a 125 kVA SiC Inverter Local Busbar . . . . 78

ix CHAPTER 1

INTRODUCTION

1.1 High Power Voltage Source Inverters Utilizing Silicon Carbide Semicon- ductors

Wide band gap (WBG) power electronic technology utilizing Silicon Carbide (SiC) and Gallium Nitride (GaN) has matured enough to the point semiconductor manufacturers have offered devices using these materials for over a decade. A signiﬁcant amount of research has focused on the advantages WBG materials have over Silicon. Devices using WBG materials have the potential for improved thermal performance, faster switching speeds, and higher blocking voltages compared to equivalent Si technology. By taking advantage of these device level improvements over Si, systems implementing SiC WBG devices can realize higher power density [17]. The Advanced Research Projects Agency - Energy has identiﬁed "high impact opportunities" for using WBG devices in place of Si in industries including motor drives, utilities, automotive, and aerospace [26].

1.1.1 Comparison of Semicondcutor Technology in High Power Inverters

Silicon Carbide MOSFET’s have several advantages over Si IGBT devices including better thermal performance, lower switching loss, and higher switching speed. These advantages suggest a higher power density EV inverter could be created by replacing Si IGBT’s with SiC MOSFET’s [25]. Organizations designing inverters often use several metrics when describing their product including power rating and efﬁciency, but the most useful metric for comparing different converters is power density. Table 1.1 below shows the difference in a SiC EV inverter created by Wolfspeed with a state-of-the-art Si IGBT inverter present in General Motor’s Chevy Volt as of 2016. These two particular converters were chosen because they are well documented, have similar power ratings, and represent both research efforts and industry work. Of course, the objectives of a research study and development for high volume production are different. However, Table 1.1 has quite a few discussion points. First, SiC MOSFET devices are used to

1 block higher voltages in the Wolfspeed inverter than the Volt system. By operating at a higher voltage, the current requirements for the SiC system can be relaxed to achieve the same power output. Second, the maximum switching speed is 33x higher in the SiC inverter than the Si inverter. The major beneﬁt of this higher switching speed is a reduction in required DC-link capacitance; the SiC inverter requires 30 µF compared to 750 µf used in the Si inverter. Finally, comparison of the SiC and Si inverter in terms of volumetric power density shows the SiC inverter’s volumetric power density is 30% higher than the Si system. This example underscores how SiC devices show great promise in improving traditional Si inverter performance.

Table 1.1 Comparison of a SiC MOSFET inverter and Si IGBT inverter

Power DC Link Volumetric Gravimetric Max Switching Organization Rating Voltage Power Density Power Density Frequency (kHz) (kW) (V) (kW/L) (kW/kg) Wolfspeed [32] 81.8 900 17.0 12.4 40 Chevy Volt [6] 135 430 12.98 16.27 1.2

1.2 Research Motivation and Objectives

Industry typically wants to improve power density in their systems, achieved by either decreasing the volume and weight or increasing power rating for the same system size. Automakers are particuarly interested in decreasing the volume of their traction power inverter module (TPIM). In the case of the 2nd generation extended range Chevy Volt reported in 2015, improvements in inverter design lead to a 2.7 L reduction in the TPIM’s volume and a 6.3 kg reduction in weight; a 43% increase in gravometric power density. Volumetric power density in the 2nd generation was only improved by 2% because the system power rating was also decreased by nearly 40 kVA. However, the system level benefits of this improved design was a 30% increase in range and a 6% efficiency gain while driving in the city [6]. Although the above example is very specific, some of its results can be generalized. For instance, reducing weight and volume from the 1st generation Volt’s TPIM was critical in achieving the above improvements. One of the components in any high power system affecting both weight and volume is the busbar. Because busbars are the electrical and mechanical connection points for power systems, a highly integrated busbar would have connections for many different system components including power modules, capacitors, current and voltage sensors, as well as gate drivers to achieve a compact architecture. Traditional laminated busbar technology poses design challenges in realizing this type of highly integrated busbar and with this in mind, the work discussed in this thesis is the result of exploring one particular way to reduce the size and weight of power systems, namely by adopting a planarized

2 PCB busbar. Attention to busbar design is critical in ensuring reliability within any power system, but speciﬁc attention will be paid to the analysis of thermal performance and the busbar’s effect on the power loop’s parasitic inductance. Full understanding of the PCB busbar’s effect on system performance will allow the designer to ensure reliability in terms of overvoltage and thermal stress. PCB and laminated busbar technologies are similar, therefore, the same techniques that have been applied to the analysis and design of high performance laminated busbar technology will be applied to the PCB busbar case to compare results and derive any considerations for the design process. The methods for analyzing a PCB busbar presented in this document will focus on their use as a tool to demonstrate the performance of the busbar’s ability to achieve reliability goals, such as low voltage overshoot and temperature rise.

1.3 Thesis Organization

This thesis will continue with Chapter 2, which will describe the methods used to analyze, optimize, and design PCB busbar systems. Attention will be given to defining parasitic elements from an electromagnetic standpoint. This will allow for a full understanding of their role in the analysis procedure discussed in later chapters. The procedure for modeling and simulating the busbar, using finite element analysis (FEA) tools, will also be discussed to avoid repetition in later sections. The chapter will conclude with a description of two methods used to experimentally verify simulation results. Chapter 3 will discuss the analysis of a busbar used in a 135 kW EV inverter with SiC power modules and the optimization of the PCB busbar’s parasitic inductance to reduce voltage overshoot. Included in this chapter is a discussion about measuring small parasitic elements by using an adapter circuit board to connect the busbar to an impedance analyzer. Additionally, this section will discuss double pulse test measurement and simulation results for design verification. Chapter 4 will discuss the design, analysis, and validation of a PCB-based bussing system for a 125 kVA active harmonic filter utilizing SiC power modules. While the focus of Chapter 3 was on improving an existing busbar design, Chapter 4 will focus on the using the developed analysis methodology to inform decisions made at the design stage of the project. The final chapter will conclude the thesis by combining key points presented in preceding chapters into a a full summary of the design and analysis methodology presented in this document.

3 CHAPTER 2

STUDY APPROACH

2.1 Introduction

This chapter will discuss the methods and analysis approach used to study the topic of busbar design. It will begin with a literature review covering developments in high power busbar design and analysis, followed by a review of parasitic elements from an electromagnetic perspective. A general procedure for simulating and estimating busbar parasitic parameters will be discussed and the section will end with an approach to verify busbar design through direct and indirect means.

2.2 Literature Review

The following section will discuss the use of busbars in high power systems as well as trends in the analysis of these structures.

2.2.1 Busbar Technology

To improve system reliability in power converters, busbars consisting of layers of copper are often employed to provide low impedance electrical and mechanical connections between the different components in a power system including power devices, capacitors, and loads. The alternative to a busbar for power applications is a wiring harness, but busbars have several electrical and mechanical advantages over wiring harnesses including reduced stray inductance and smaller space requirements [12]. Industry standard busbar technology in the 1990’s consisted of planar, parallel copper plates for carrying high current loads; this approach was cheap and produced better performance than a wiring harness [4]. However, mutual inductance cancellation in this structure is small compared to an overlapping structure. Laminated busbars, consisting of multiple copper plates separated by a dielectric,

4 have become a dominant technology for high power systems due to their low inductance, high reliability, and ability to incorporate AC conductors in their design. In fact, laminated busbar technology has been successfully used in kW and MW applications due to its high voltage robustness and current current carrying capability [9][46]. For example, inverters with power ratings above 100 kW in electric vehicles have used Si IGBT power modules and laminated busbars with DC bus voltages up to 700 V [22][19]. However, recent studies have focused on using SiC power modules and a boosted DC link voltage above 700 V to achieve higher power densities [34][32]. Because SiC power devices have higher edge rates than comparable Si devices, the danger of large voltage spikes from parasitic inductance contributed by the busbar is more pronounced and must be minimized through good design practice in order to ensure system reliability.

2.2.2 A Review of Busbar Analysis and Optimization Literature

Although the concept of a busbar is not new, the optimization of interconnect inductance is a more recent necessity. The alternative to a busbar system is one which primarily uses thick cables to connect different components, but the downside of using cables is a high stray inductance. This side effect may have been acceptable in systems using bipolar junction transistor (BJT) power devices due to their slow switching speed. Motivation to reduce parasitic inducance may have been low due to this fact. However, in the early 1990’s, researchers began reporting work related to busbar inductance optimization. This work may have been motivated by the fact insulated gate bipolar transistors (IGBT) were becoming industry standard allowing for faster switching power electronics with higher current change rates. In 1993 Skibinski and Divan discuss the advantages of a planar busbar over wiring harnesses in terms of parasitic inductance and temperature rise. They theoretically showed the parasitic inductance for a 12-inch long busbar can be reduced by at least 25% by adopting a planar bus structure. Their discussion included the design methodology for a multi-layer busbar with emphasis on maximizing mutual flux cancellation by overlapping planes. To validate their methods, they presented impedance measurement results for a low inductance laminated busbar highlighting the improvements [36]. This particular work is most likely not the earliest report on the use of planar busbars, but it represents a shift away from the use of wiring harnesses when the goal of a design was to minimize parasitc inductance. Next, the use of finite element analysis (FEA) applied to busbar analysis will be discussed. The earliest document discussing the use of FEA for calculating magnetic fields in a structure was reported in 1965 by Winslow [42]. These early use cases were performed by hand by the engineer and were eventually made into punch cards for early computers. Thus, the speed at which FEA could be performed was certainly limited in complexity and time. One of the earliest papers discussing the use of FEA software applied to busbar analysis was published almost 25 years later in 1991 by Chiampi. In the paper, FEA simulations were used to predict power losses due to Joule heating and current sharing in a high power industrial busbar system. The author states electromagnetic field equations were solved

5 under quasistatic conditions. The busbar geometry was simple enough that a 2D representation would sufﬁce for their simulation [15]. As will be seen in later chapters, this approach to analyzing a busbar is not radically different from the approach used today. The only difference is that FEA software now is able to easily represent and simulate 3D geometries allowing for in depth studies to be completed quickly. In 2006, Guichon et. al published an oft cited paper titled, "Busbar Design: How to Spare Nanohen- ries?" [20]. The authors discuss several approaches to designing a laminated busbar including the effects of multiple layers and the impact on parasitic inductance from the placement of required mounting holes. They explain the two core goals in any busbar’s design: to achieve (1) low parasitic inductance and (2) balanced current between paralleled components. Their analysis is supported by computational simulations performed on a 3D representation of a busbar. An initial busbar design was used in the study and, through computation simulations, the negative impacts on parasitic inductance of hole placements were shown. Additionally, the authors discuss the process used to balance current in two particular branches in the busbar. The authors conclude their paper with some practical advice for low inductance busbar designs, such as maximizing layer overlap and being cognizant of the effects of hole placement which minimize parasitics. Perhaps the most comprehensive paper discussing the design and analysis of laminated busbars was authored by Callegro et. al. [11]. Topics in the paper include electrical reliability, manufacturability, optimizing DC current distribution, analyzing Ohmic power loss, and optimizing busbar parasitic elements. Their analysis of current distribution, power loss, and parasitic inductance and capacitance used FEA as a tool to compare different busbars to predict performance and validate their design. Additionally, the authors also analyze their designs under both DC and AC conditions to analyze current density and provide a qualitative discussion of EMI. They used an approach similar to other works [19] to experimentally validate their simulation results. They experimentally evaluated their busbar using an impedance analyzer to measure parasitic elements and double pulse testing to measure voltage spikes. The breadth of topics discussed in this work makes it a valuable resource for practical busbar design and analysis. Literature related to high power PCB busbars is limited because laminated busbar technology offers excellent performance in a wide range of applications. However, a paper written by Rahman et. al. in 2016 discusses the use of a PCB busbar to achieve a compact, planarized design for a 55 kW SiC EV traction drive inverter. The paper brieﬂy discusses the PCB busbar design including the placement of ceramic decoupling capacitors for voltage spike reduction and the use of multiple 4 Oz. copper layers to achieve the required currenty carrying capability. The authors also include simulation results from Ansys Q3D to provide an analysis of the busbar’s parasitic inductance to show a low loop inductance is achievable with a multi-layer PCB comparable to a laminated busbar [34]. However, the authors do not discuss a process for optimizing the power loop inductance or decoupling capacitor placement, indicating there is room to improve upon this work by applying the design and analysis approach for

6 traditional laminated busbars to the design and analysis of PCB busbars. Few authors report analysis performed to predict the effect the parasitic loop inductance of their busbar will have on performance parameters, such as voltage spikes or switching loss. In the literature mentioned above, any analytical approach to analyzing a busbar design is typically limited to using theoretical equations to estimate the inductance of a busbar prior to using FEA software to obtain precise estimations. One method for analyzing the effect parasitic elements have on MOSFET performance using time-domain analysis has been reported [44] and can be applied to estimate MOSFET turn-off voltage spike using device datasheet parameters and parasitic inductance estimates. However, it is limited in application because it describes a general case. Another approach to busbar analysis in the frequency domain reported by Chen et. al. [14] is used to inform the selection of decoupling capacitors and their placement to suppress voltage spike. A primary conclusion from that work is the decoupling capacitance should be at least 50 times larger than the device’s output capacitance to successfully decouple the DC-link capacitor’s parasitic inductance from the device, thereby reducing overvoltage stress due to high rates of current change. The works discussed discussed above are certainly useful on their own merits, but there are . On the one hand, most papers on busbar optimization focus on only a small handful of parameters in depth, such as the effect of hole placement on parasitic inductance [20]. On the other hand, authors who discuss a large variety of topics relevant to busbar optimization, like Callegro et. al, have limited space to go into detail about each topic. Therefore, one of the goals of this document is to provide an in-depth study on the topic of busbar design and analysis using FEA tools.

2.3 Busbar Analysis Approach

This section will discuss a generalized approach used in later chapters for the analysis of PCB busbars.

2.3.1 Deﬁnition of Loop Inductance

In high power voltage source inverters, a large amount of input capacitance is required to reduce voltage ripple from the input, which is often a boost converter. These DC-link capacitors are typically physically large and thus difﬁculty exists in placing these components close to the switching devices and a large physical loop exists between the power module and DC-link capacitors. This loop can be described using several properties, but the most useful in practical applications is the loop’s inductance because this property affects the switching characteristics of the system including overvoltage and switching losses. The loop inductance is deﬁned as the summation of all partial self inductances of conductors making up the loop and the mutual inductance between each condcutor as in Eq. 2.1 where

Li is the partial self-inductance of a conductor and Mi j is the mutual inductance between it and another conductor.

7 X X X LLOOP = Li + Mi j + M j i (2.1) i =1 i ,j i ,j Loop inductance is sometimes called stray inductance or parasitic inductance and this work will refer to it as parasitic inductance to highlight the fact this inductance results in unwanted behavior in the system. Several options exist to mitigate the effect of loop inductance and the cases in this work focus on the use of decoupling capacitors to provide a low impedance path for high frequency current to ﬂow through to limit voltage overshoot when the SiC MOSFET’s turn off. Decoupling capacitors are small ceramic capacitors placed very close to the power module to create a second loop that has much lower loop inductance than the loop including the DC-link capacitors, resulting in lower voltage spikes. The circuit in Fig. 2.1 shows these two loops.

Figure 2.1 Equivalent circuit for the power loop in a single-phase of an inverter

Where LDS represents the parasitic inductance of the power module, LP 1 represents the parasitic inductance the decoupling capacitors contribute to the loop, LP 2 and LP 5 denotes the parasitic inductance of the path to the DC-link capacitors, LP 3 and LP 4 represent the parasitic inductances of the DC source, and M is the mutual inductance between the busbar and power module. Mutual inductance can either be negative or positive depending on the direction of current ﬂow in the conductors. Therefore, two loops exist:

LLoop1 = LDS + LP 1 + 2M1 (2.2)

LLoop2 = LDS + LP 2 LP 5 + LESL + 2M2 (2.3)

Where LLoop1 is the loop inductance between the power module and the busbar with decoupling

8 capacitors and LLoop2 is the loop inductance between the DC-link capacitors and power module. The ESL of the decoupling capacitors is ignored in the above description because for ceramic capacitors it’s small and paralleling of passives mitigates its effect. This is less true for DC-link capacitors, thus their ESL is not ignored. A brief description of the electromagnetic theory behind parasitic elements will now begin to provide insight into why these parasitic elements exist and must be included in high ﬁdelity circuit models.

2.3.2 Parasitic Inductance Theory

From a magnetic circuit perspective, a bus bar is equivalent to a single-loop coil around an air core. Self-inductance, or parasitic inductance in the present topic, relates the amount of magnetic ﬂux produced in the air core to the current ﬂowing through a conductor. For a linear core, like air, this simple relationship is

Φ L (2.4) = I where Φ represents the amount of magnetic flux and I is the total current. An expression for the magnetic flux flowing through a cross sectional surface is a consequence of Faraday’s Law:

Z Φ = B~ dS~ [21] (2.5) · where B~ is the magnetic ﬁeld at some point r away from the differential surface area dS~. Biot-Savart’s Law describes the magnetic ﬁeld at some point r away from a point on a conductive medium:

Z µ0 I d ` r B = 0 [21] (2.6) 4π r ×3 | 0| Using the above equations, the self inductance can be derived for various geometries. For instance, the ﬁrst geometry often introduced to students is a circular loop of wire having a self inductance derived from the above equations to be µ A L o c (2.7) = l

Where l is the length of the air core and Ac is its cross-sectional area. It is obvious from Eq. 2.7 the inductance of a loop can be reduced by having a small cross-sectional area and a wide conducting path. In the case of a power system with a busbar, the loop is assumed to be rectangular. Figure 2.2 shows this rectangular loop and each portion of the loop can be assumed to be a rectangular bar of width w, length `, and thickness t in mm. In this case the self inductance of each bar can be calculated analytically using:

2` w + t 1 L = 2`[l n( + 0.5 + 0.2235( )] 10− nH [11][35] (2.8) w + t ` ×

9 Figure 2.2 A single-turn rectangular loop around an air core.

If the geometry of a busbar is known, the above equation can be used to estimate the self- inductance of a busbar or any rectangular conductor under DC conditions. However, due to the skin effect, using an analytical approach to determine the parasitic inductance for a conductor becomes more complicated. As others point, there are two components making up the parasitic inductance in a conductor that he describes as internal and external inductance [12][33]. The internal inductance arises from flux linkages inside the conductor and, in fact, (2.8) is an expression for internal inductance. Due to the skin effect, current will primarily flow near the surface of the conductor at high frequency causing the internal inductance to be negligible. External inductance describes the effect external conductors like a return path or ground plane have on self inductance and dominates internal inductance at high frequency due to it being frequency independent. Several authors discuss the difficulty in using analytical solutions to obtain accurate estimates of self inductance [12][39]. Caponet mentions no closed form solutions exist for a simple rectangular conductor and complex equations are only useful in certain situations. Although the equations mentioned by Caponet and Wang can potentially offer insights into what parameters affect busbar inductance most, namely the length and width of the current paths, busbars often do not have simple geometries and thus equtaions given in literature are of limited use. Ultimately, Paul turned to the use of numerical solutions to determine the high frequency inductance of conductors [33]. Ansys Q3D was designed to extract the parasitic elements from complex geometries and therefore can be a powerful tool that will be used in the following sections to describe the parasitic inductance for complex geometries.

2.3.3 Parasitic Capacitance Theory

Electrical potential between two conductors gives rise to a separation of charges between the conductors establishing an electric ﬁeld. Capacitance is simply the relationship between the total amount of charge separation and the electric potential, expressed as

Q C = [21] (2.9) Va b

10 where Q is the total charge and Va b is the potential between the two conductors. This form of the capacitance equation is fine for defining the term, but from a design perspective it is more useful to describe the capacitance in terms of its geometry. Gauss’s Law relates the total charge enclosed by a surface to the amount of flux passing through it

I Q = D~ d~ s [21] (2.10) S · where D~ is the electric ﬂux density, equal to the electric ﬁeld multiplied by the material’s permitivitty,

ε, and d s~ is the differential surface area of the conductor. The potential, Va b between two conductors can be expressed in terms of the electric ﬁeld.

Z a Va b = E~ d l [21] (2.11) b Equation 2.9 can be rewritten in a general form by combining the two above equations for charge and potential.

H ~ ~ S E d s C = εr εo a · (2.12) R ~ b E d l Therefore, any potential difference between two conductors will result in a capacitance. Although intentionally used in the construction of components like capacitors, this behavior can be unwanted in busbars and is called parasitic capacitance in context. A simple example of this is the basic parallel plate, shown in ﬁgure 2.3.

Figure 2.3 A simple parallel plate capacitor

For a parallel plate capacitor, equation 2.12 can be simpliﬁed to

εA C 21 (2.13) = d [ ]

11 The above ﬁgure is assumed to be the case most of the time in busbars, and from equations 2.12 and 2.13, the parasitic capacitance in a busbar is determined by its geometry. Because parasitic capacitance and inductance are not dependent on geometric parameters in the same way, improvements to one parasitic element through a redesign of busbar geometry could negatively impact the other element. Therefore, busbar geometry can be optimized to balance these two behaviors.

2.3.4 Parasitic Resistance Theory

At DC, the parasitic resistance of a conductor can be calculated using the simple relationship between resistivity and geometry:

l ρ RDC = (2.14) AC

Where ρ is the materialâA˘Zs´ conductivity in ohms-m, l is the length of the material, and AC is the cross sectional area. At high switching frequency or ringing, the skin effect must be taken into account when analyzing parasitic resistance. The skin effect is the tendency for current to concentrate near the surface of a conductor due to induced eddy currents in the center [21]. Therefore, the current density is highest at the surface and tends to be reduced in the middle of the conductor. The skin depth for a cylindrical conductor, or the thickness where the majority of current is ﬂowing, can be calculated using:

v t 1 δ = [21] (2.15) f πµσ

Where δ is the skin depth in meters, µ is the permeability of the conductor in H/m which is assumed to be equal to the permeability of a vacuum, and f is frequency in Hz. For copper at 20C, the skin depth in mm simpliﬁes to:

65.6 δ = (2.16) pf The skin depth effectively reduces the thickness of the conductor used to calculate its cross sectional area. At high frequencies, the skin depth will begin to approach a conductors thickness, at which point its resistance will increase with the square root of frequency resulting in more I 2R loss. Thus the skin effect can potentially be a limiting factor when choosing the thickness of a busbar, particularly if the switching frequency is high.

2.3.5 Parasitic Extraction using Finite Element Analysis

The following is the general procedure for developing a parasitics model of a busbar. The circuit design software used was Altium and the FEA package was Ansys Q3D Extractor. It is important to note that this procedure does not include simulating the busbar with its power module.

12 1. The busbar is designed in circuit layout software. Conductor and substrate thickness and spacing are defined during the design process to achieve the required current carrying capacity and voltage insulation. Once finalized, a drawing file is exported which represents each layer of the PCB as a 2D drawing.

2. To build a model of the busbar in Ansys Q3D, the busbar drawing ﬁle must be imported layer by layer. Each layer’ thickness and spacing are set according to the layer details speciﬁed in the design process.

3. Once the full board stack has been modeled, pads for ceramic capacitors are identiﬁed and a block with the same dimensions as the capacitor is placed across the pads. This block will act as a short across the capacitor terminals to create a closed path for current to ﬂow.

4. Each net on the board corresponds to a net in Q3D and each net may have multiple sources, but only one sink may be defined. The current source is defined as the DC+ module terminal connector and a sink is defined as the DC- module terminal connector.

5. An analysis is setup to extract the parasitic resistance, inductance, and capacitance and mesh resolution is set. Ansys Q3D uses an iterative solver to perform its simulations and will continue refining its mesh until convergence occurs or the maximum number of iterations defined by the user is reached. Convergence is said to be achieved when the change in a parasitic value between two iterations is less than a specified percentage. The default variation for convergence is 1%.

6. The output of the simulation is a resistance, inductance, or capacitance matrix representing the partial and mutual inductance for the different nets in the busbar. For an inductance matrix with multiple nets, the diagonal values of the matrix are the self-inductance of each net and the off-diagonal values represent the amount of mutual inductance between each net [5].

2.4 Experimental Validation

Two methods of validating simulation results will now be discussed including impedance measurements and double pulse tests.

2.4.1 Extraction of Loop Inductance using Impedance Measurements

Simulation results are most useful when they accurately reﬂect reality, therefore some method of measuring the loop inductance must be used to compare to the FEA results. In fact, if an engineer does not have access to expensive FEA software, such as Ansys Q3D, taking a measurement is a cost effective method for extracting the loop inductance under the assumption they have access to the

13 correct measurement equipment. This work is based on publications by Dr. Andrew Lemmon, who has written several publications on measuring stray inductance in multi-chip power modules [27][28].

(a) Decoupling capacitor current loop (b) Broken loop connected to an impedance analyzer.

Figure 2.4 Current loop for measurement.

The circuit in Fig. 2.1 consists of two loops, but only the decoupling capacitor loop will be considered for measurement. Therefore, the loop of interest is shown in Fig. 2.4(a) and includes the module and decoupling capacitor path parasitic inductance. To measure this loop, an impedance analyzer can be used. The basic idea behind an impedance analyzer uses an injection of a small signal current into the device under test (DUT) allowing for the measurement of the resulting voltage used to calculate the DUT’s impedance; this will be further discussed shortly. To achieve current injection into the loop in Fig. 2.4(a), there must be a break in the loop of interest where the small signal can be injected, as shown in Fig. 2.4(b). The challenge in measuring the impedance in the case of high power systems is the fact busbars are not typically designed to be connected to common BNC or SMA connections commonly found on measurement equipment. Therefore, a measurement adapter must be designed to achieve two goals: (1) facilitate electrical connection between the inverter and impedance analyzer’s terminals and (2) make a break in the loop to allow a signal to be injected. The speciﬁc impedance analyzer used in this discussion will be Keysight’s E4990A shown in Fig. 2.5(a). The E4990A implements an auto-balancing bridge method for measuring impedance. The auto-balancing bridge allows for wideband measurements from 20 Hz - 120 MHz [23]. This method is appropriate for the measurement of loop inductance in high power systems because resonance in the system due to the parasitic inductance is most likely under 100 MHz. The basic operation of the auto-balancing bridge method for impedance measurement is straight forward. To begin, there are four ports on an auto-balancing bridge: HC , HP , LC , and LP . A small signal

14 (a) Keysight E4990A. Image from [24] under fair (b) Basic auto-balancing bridge operation. Image use. from [23] under fair use.

Figure 2.5 Impedance analyzer speciﬁcation.

current, IX , is injected at port HC and the voltage across the DUT is measured at HP . Current exits the DUT at LC and must ﬂow through a range resistor Rr which affects the impedance range of the measurement [23]. The impedance is expressed simply in (2.17).

VX ZDUT = Rr (2.17) IX To facilitate the connection between the four ports on the analyzer and the DUT, a measurement adapter must be designed. A block diagram showing the role of the adapter is shown in Fig. 2.6. Unfor- tunately, the measurement adapter itself will have parasitic inductance, resistance, and capacitance which can cause measurement error. In other words, when the equipment measures the DUT, it is actually measuring the DUT impedancethe plus the measurement adapter’s parasitic impedance. For the studies in this document, the loop inductances of interest are less than 40 nH and parasitic elements in the measurement adapter can cause severe measurement error if not properly compensated for. The most common method for compensating this unwanted behavior is to perform open/short/load measurements to characterize the ﬁxture residuals. The compensation involves measuring only the measurement adapter’s impedance under several conditions. The open condition, where the output terminals are left unconnected, measures the adapter’s stray capacitance. The short condition, where the output terminals are shorted together, measures the adapter’s stray resistance and inductance. The load compensation places a load at the output terminals of the adapter and provides a reference impedance for the measurements. The DUT impedance measurement results are thus compensated according to (2.18) with the terms deﬁned in Table 2.1

(ZS ZXM )(ZL ZO ) ZDUT = − − ZLT (2.18) (ZXM ZO )(ZS ZL ) − − Finally, if the purpose of the impedance measurement is to determine the parasitic loop inductance the decoupling capacitor pads on the busbar can be shorted out and a power module must be connected

15 Figure 2.6 Connection block diagram for an impedance analyzer, measurement adapter, and DUT.

Table 2.1 Compensation Parameters in Eq. (2.18) [23]

Parameter Deﬁnition

ZDUT Compensated DUT impedance ZXM Measured DUT impedance ZO Measured open impedance ZS Measured short impedance ZL Measured load impedance ZLT True load impedance

to complete the loop. The measurement adapter board connects the busbar/module loop with the E4990A which performs a frequency sweep and records the compensated DUT impedance which can be analyzer after the fact to extract the loop inductance. If the capacitor pads are shorted, a single resonant should be present between the decoupling loop inductance and the module’s COSS . Therefore, the slope of the curve after the resonant point can be used to calculate the parasitic loop inductance from the equation below.

∆Z Ll oop = (2.19) ∆ω

2.4.2 Switching Characterization using the Double Pulse Test

Double pulse tests (DPT) are often employed to characterize systems in terms of rise time, fall time, and voltage overshoot. When a power module is connnected to a busbar and the relevant capacitors are also installed, the double pulse test can be used to determine the voltage spike components will experience under various DC source voltages and load conditions. A DPT is often used in high power systems to document voltage spike [41] and is particularly useful when comparing different busbar designs when they are used in conjunction with the same power module.

VDC td e l a y ILOAD = × (2.20) LLoad

For a half-bridge circuit, the circuit shown in Figure 2.7 can be used for DPT. CLINK and CHF

16 Figure 2.7 A DPT Circuit for Measuring Voltage Spike of a Half-Bridge Circuit

Figure 2.8 Example of a DPT gating signal (red) and load inductor current (green).

refer to the DC-link and any snubber capacitors across the DC source on the busbar, Q1 and Q2 refer to the devices within the half-bridge, and an inductive load is connected to the module. In this particular setup, device Q1 will always be off and the pulses for the test will only be applied to the gate of Q2. An example of a gating signal is shown in Figure 2.8. While the gate signal for the low side device is off, circulating current will ﬂow through the high side diode and load inductor, causing the total amount of current circulating through the system to linearly increase according to (2.20) and shown in Fig. 2.8. The load current the device will switch at is determined DC source voltage, the load inductor’s inductance, and the delay in the gate signal. Measurement of voltage overshoot on the output of the power module is the primary goal of experimental double pulse tests performed for the work in this thesis. Because ringing in the 10’s of MHz

17 range is expected to be present in the output voltage waveform in the following studies, high voltage probes with high bandwidth are required for measurements. Additionally, the rise and fall time of the drain-source voltage waveform, defined as the time it takes for the waveform to rise or fall between 10% and 90% of its final value, wcan be measured to validate simulation accuracy. To confirm the expected turn-off current is appropriate, current transducers capableare employed to measure the load inductor current. Finally, if measurements of the drain-source current of the bottom leg of the half-bridge are taken, switching energy loss can be estimated using that data and the drain-source voltage data.

18 CHAPTER 3

MODELING, MINIMIZATION, AND MEASUREMENT OF PARASITIC LOOP INDUCTANCE FOR A 135 KW EV INVERTER

3.1 Introduction

The basic electric vehicle (EV) powertrain consists of a battery, a voltage source inverter, and a motor. The purpose of the inverter is to to process the electrical energy from the battery in such a way that it can be used by the motor to generate mechanical power. The power electronics in the inverter can potentially contribute a significant amount of power loss to the drivetrain system. A significant amount of research, both in industry and academia, focuses on the development of inverters with high electrical efficiency. Recent trends industry trends include the replacement of Silicon-based IGBT power devices with SiC MOSFET’s due to SiC’s potential for higher blocking voltage, faster switching, and better thermal performance than Si. Major automakers including Toyota, Nissan, and Chevrolet [22] use Si-IGBT power devices as switches in their inverter designs and adoption of SiC-based inverters may lead to better performing EV powertrains [25]. As mentioned before, laminated busbars are standard in the EV industry for providing electrical connections between components in high power systems. Very few sources document the use of a PCB as a busbar in an inverter, but the system in this study implements a PCB busbar to achieve high power density. Because SiC devices can switch at high speeds than traditional Si devices, the potential for voltage spikes from high di/dt and parasitic loop inductance is a real concern. Therefore, this chapter will implement the methods and procedures discussed in the previous chapter to more fully understand the PCB busbar’s effect on commutation loop inductance and voltage spikes in a 135 kW EV inverter.

3.1.1 System Overview

The system consists of a boost converter that raises the DC source voltage to 1 kV which a three-phase inverter then processes for use in a permanent magnet synchronous machine (PMSM). The system overview is shown below in Fig. 3.1, a high level equivalent circuit for the inverter is shown in Fig. 3.2,

19 and Table 3.1 shows its system level speciﬁcations. In the circuit in Fig. 3.2, the DC-link and decoupling capacitors are shown as single components, but in reality they are spread between multiple capacitors.

Figure 3.1 System level overview for the 135 kW SiC EV traction inverter.

Figure 3.2 Three-phase half-bridge topology for the inverter.

Parameter Speciﬁcation Bus Voltage 1 kV

Maximum Output Current 150 ARMS Switching Frequency 20 kHz DC-Link Capacitance 52 µf Decoupling Capacitance 0.9 µf

Table 3.1 NCSU 135 kW EV Inverter System Speciﬁcations

Traditionally, copper-based laminated busbars have been the go-to solution to ensure high efficiency and safe operation in traction applications [13] and the operating frequency was generally limited to 10- 20 kHz. With an increased operating frequency, busbar design is crucial since the system performance, safety, efficiency, and electromagnetic emissions are heavily influenced by the busbar architecture and parasitic components [29][10][20][12]. With increased demand for high power density power converters,

20 busbar form-factor and interconnection with power modules play signiﬁcant roles in the overall system- level design. Printed circuit board (PCB)-based busbars are alternatives to copper-based laminated busbars owing to ease of design, manufacturability, and simpliﬁed system assembly.

Figure 3.3 135 kW EV Inverter Solidworks Model

The system used in this study in Fig. 3.3 is a 135 kW EV traction inverter with a 1 kV DC bus imple- mented with half-bridge MPCM’s. An equivalent circuit model of parasitic inductances is shown in Fig.

3.4 where LDS represents the lumped parasitic inductance of the power module and the remaining inductances represent the contribution of the bussing. Often, the parasitic inductance in the loop consisting of a power module and DC-link capacitor is large because the dimensions of these capacitors prevent them from being placed close to the power module terminals [12]. A common technique for reducing parasitic loop inductance, thereby reducing switching energy loss and turn-off voltage spike, is to place decoupling capacitors as close to the power module terminals as possible [38][14]. Therefore, the two loops of concern in this study are the DC-link capacitor loop (LDS + LP 2 + LP 5 + LESL ) and the decoupling capacitor loop (LDS + LP 1) with the goal of achieving LP 1 << LP 2 + LP 5. LP 3 + LP 4 denotes the stray inductance of the power cables used to connect the terminals of the busbar to the DC voltage. This chapter will demonstrate an approach to the design, analysis, and validation of a PCB busbar by considering the commutation loop as a whole unit consisting of a MCPM, heavy duty interconnects, capacitors, and busbar. This work will illustrate the modeling of the various components that constitute the commutation loop in an inverter using ﬁnite element analysis (FEA). Thus, the MCPM, PCB busbar and the module to PCB interconnect are modeled in Ansys Q3D Extractor to obtain a lumped commutation loop inductance value. The busbar design is centered around the Wolfspeed 1.7 kV, 7.5 mΩ high performance SiC half-bridge power module (SKU: HT-3231-R). The designed PCB busbar encompasses

21 Figure 3.4 Single phase half-bridge showing power loop current paths.

the interconnection of the power modules, as well as the capacitors and the power connectors.

3.2 High Power PCB Busbar Design

Several considerations will now be discussed to describe the design of the busbar in meeting system requirements for the 135 kW SiC inverter with a 1 kV bus.

3.2.1 High voltage sustainability

High voltage PCB’s require insulation between different traces and planes to prevent arcing and corona production [37]. Direct arcing occurs between conductors in a PCB when the insulating material’s dielectric strength is exceeded. A common insulating material between layers in a PCB is FR-4, which is also the case for this PCB busbar, and one source states FR-4 can provide an insulation of 150 V/mil, though this is a conservative recommendation [37]. To further decrease the chance of corona production in a high power PCB busbar, corners in traces and pours are recommended to be round. In addition to the appropriate separation of layers in the PCB, the distance between traces and planes in the same layer must be considered to prevent arcing and corona production. IPC-2221A states the clearance distance between conductors for FR-4 to sustain 4800 V must be at least 3 mm [18]. These requirements were used to design the PCB busbar to sustain 4 kV using a standard PCB manufacturer.

3.2.2 High current conducting capability

System speciﬁcations require a a continuous current of 100 ADC , however the inverter was designed to produce a maximum AC current of 150 ARMS . A multilayer structure was used to meet these current requirements. The structure of the busbar consists of three AC phase output planes that have two DC+ and DC- planes above and below them. The trace of the phase output traces were designed using (3.1) from the IPC-2221A standard to keep the temperature rise below 40 C. The equation relates the trace’s ◦

22 cross-sectional area to the expected temperature rise and from this equation, the minimum width of DC and AC traces was 20 mm and 25 mm, respectively.

b c I = k∆T A (3.1) where, for internal layers: k = 0.024, b = 0.44, c = 0.725 for external layers: k = 0.048, b = 0.44, c = 0.725 [18]

3.2.2.1 Multilayer Structure of the PCB Busbar

From the discussion above, a multilayer PCB was manufactured consisting of 8-layers of 4 Oz. copper with a representation of the stack shown in 3.5.

Figure 3.5 Busbar layer stack showing layer number and nets.

3.2.3 Power loop inductance

Electromagnetic compatability (EMC) and reliability are concerns for switching power converters, especially systems utilizing SiC power devices with higher switching frequencies, and power loop inductance is an important performance metric affecting both of these behaviors. To ensure a system’s switching performance, efﬁciency, and safety are realized, the parasitic inductance contributed by the busbar must be minimized [20][12]. In this PCB busbar design, minimization of the loop inductance has been addressed by selecting the vertical stacking structure discussed above. The DC+ and DC- power planes are stacked in pairs with a maximum amount of overlap. Adopting this design approach enables magnetic ﬂux cancellation effects to reduce parasitic inductance. In the case of AC planes, the different phases do not have any vertical overlap with each other.

23 The initial PCB busbar designed for the 135 kW SiC inverter with a 1 kV DC link is shown in Fig. 3.6 and has two stages of capacitance including one set for energy storage and one for decoupling. The two capacitor stages result in two parallel loops between the DC+ and the DC- terminal in the busbar as shown in Fig. 3.4. The two stages of capacitors are described below: 1st-stage - Bulk DC-link capacitors for energy buffer or voltage stabilization. Two 27 µF capacitors were distributed for each module (ESL = 15 nH, resonant frequency = 250 kHz). The DC-link capacitors constitute the larger current path in Loop 2 in Fig. 3.4. 2nd stage - Ceramic capacitors were distributed near the power modules on both sides of the board to reduce the device’s voltage overshoot. These decoupling capacitors constitute the localized current commutation Loop 1 in the inverter in Fig. 3.4. Efﬁcacy of the decoupling capacitors in reducing voltage overshoot is dependent on their placement with respect to the DC+ and DC- terminals of the module because their placement affects the decoupling current path and thus the parasitic inductance. The amount of decoupling capacitance required to successfully decouple the DC-link capacitor loop inductance from the decoupling capacitor loop inductance is discussed by Chen et al [14]. The initial busbar-A design has capacitors placed around the module as shown in Fig. 3.6.

Figure 3.6 PCB busbar-A design for the 135 kW SiC inverter with 1 kV DC-link.

24 (a) (b)

Figure 3.7 (a) Heavy duty interconnect, (b) the connectors on the module.

3.2.4 Heavy Duty Interconnect Design

To utilize the low inductance module effectively, and to minimize the commutation loop inductance, customized heavy duty connectors with current handling capability of 150 A each, shown in Fig. 3.7, were designed using Solidworks. These interconnects allow the power module to be electrically and mechanically connected to the high voltage PCB busbar with minimal added parasitic inductance to the commutation loop.The connectors were manufactured out of copper with Nickel plating, shown in Fig. 3.7(a) and a model showing how the connectors are placed on the power module is shown in Fig. 3.7(b). The connection between the busbar and module is made by soldering the connectors into the PCB and putting a M4 bolt through each connector into a module terminal. Additionally, these interconnects offset the busbar several millimeters from the top of the module, allowing an extra set of small ceramic decoupling capacitors to be placed on the bottom side of the busbar if needed.

3.3 Parasitic Inductance Extraction of the Major Components of the Power Loop

Several researchers discuss the difﬁculty in using analytical solutions to obtain accurate estimates of self inductance [12][39]. Caponet et. al mentions no closed form solutions exist for a simple rectangular conductor and complex equations are only useful in certain situations. Although the equations mentioned by Caponet and Wang can potentially offer insights into what parameters affect busbar inductance most, namely the length and width of the current paths, busbars often do not have simple geometries and thus equtaions given in literature are of limited use. Ultimately, Paul turned to the use of numerical solutions to determine the high frequency inductance of conductors [33]. Ansys Q3D was designed to extract the parasitic elements from complex geometries and therefore can be a powerful tool that will be used to analyze the power loop in the traction inverter. The following discusses the extraction of parasitic inductance of the different components that

25 constitute the commutation loop in the inverter. The commutation loop inductance in the inverter under study includes the inductance of the 1.7 kV SiC module, inductance contributed by the PCB busbar between the DC+ and and DC- terminals, and the inductance of the module to PCB interconnect. These inductances have been extracted using FEA and a simple model of each component has been provided.

3.3.1 Modeling of the SiC Power Module

The 1.7 kV module (HT-3231-R) shares the same low inductance package as that of the 1.2 kV version [43]. The latter was opened to expose its internal architecture. The physical dimensions and spacing of the direct bonded copper (DBC) dimensions of the terminals were extracted from the exposed 1.2 kV module shown in Fig. 3.8. The die positions and wire bond dimensions in the 1.7 kV module were non-destructively obtained through micro-CT. With these details, the 1.7 kV module was modeled in Ansys Q3D extractor for the estimation of its stray inductances. Distribution of 150 A in the commercially available 1.2 kV module is shown in Fig. 3.9. The Q3D model and the current distribution in the 1.7 kV module is similar to that of the 1.2 kV module in Fig. 3.9. The inductance and resistance values extracted from Ansys Q3D Extractor are tabulated in Table 3.2. The corresponding equivalent circuit of the commutation loop is shown in Fig. 3.10. The parasitic inductance in the module between the DC+ and the DC- terminals can be estimated using (3.2). LDS in Fig. 3.4 is the same as the lumped value in

3.2. The extracted lumped stray module inductance (Lmod ul e ) between the DC+ and the DC- terminals without a return path is 10.48 nH at 10 MHz.

Lmod ul e = L1 + L2 + L3 + 2 (M12 + M23 + M13) (3.2) ×

Figure 3.8 Internal layout of the 1.2 kV SiC power module.

26 Figure 3.9 Current in the distribution the 1.2 kV SiC power module.

Figure 3.10 Equivalent circuit representing the stray inductances in the module between the DC+ and DC- terminal.

3.3.2 Modeling of the PCB Busbar-A and the Interconnects

The initial design for the busbar will be discussed, which will be called design-A. two design iterations are also discussed later and will be called design-B and C, respectively. From Fig. 3.4, it is evident the second current commutation loop (Loop 2) is made up of the parasitic inductance of the path in the busbar to the large ﬁlm capacitors, LP 2 and LP 5, the ESL of the DC-link capacitors, and the parasitic inductance in the module. This loop will be referred as LCCL x 2 and the X will refer to the busbar − design iteration (A, B, or C). The addition of the distributed ceramic capacitors resulted in another loop,

LCCL x 1, consisting of a smaller parasitic inductance from the path to the decoupling capacitor, LP 1, − where LP 1 < LP 2 +LP 5. Reduction in the stray inductance contributed by the busbar to the commutation loop inductance signiﬁcantly reduces the overshoot voltage across the devices. The current distribution in the two loops is shown in Fig. 3.11. The heavy duty interconnect was simulated in Ansys Q3D to estimate the maximum current density when the connector is conducting 150 ADC . The result is shown in Fig. 3.12 and the current density is highest in the outer pins at 250 A/c m 2. Additionally, the interconnect was simulated at a frequency of 10 MHz to extract its parasitic inductance, which was less than 1 nH. In later simulations, the parasitic inductance of the busbar and interconnect will be lumped together.

27 Table 3.2 Extracted Module Parasitics at 10 MHz

Element La c (nH ) Ra c (mΩ) L1,R1 1.77 1.77 L2,R2 3.03 0.39 L3,R3 1.21 0.31 M12,R12 0.91 0.91 M23,R23 0.69 0.07 M13,R13 0.18 0.18

Figure 3.11 (Left) Current distribution in path involving the DC link capacitors (Loop 2) in the busbar and (right) current distribution involving the decoupling capacitors (Loop 1) in busbar PCB.

3.3.3 Decoupling Loop Inductance with Busbar-A

The three major components of the power loop including the power module, busbar, and heavy duty interconnect have been modeled in Ansys Q3D and their partial self-inductances have been extracted. However, determining the decoupling loop inductance is more complex than summing up these parts due to the effect of mutual ﬂux cancellation. To obtain a clear understanding of the loop inductance for the system, all three components were combined into one model for simulation in Q3D. For ease of modeling and discussion, the heavy duty interconnect’s parasitic inductance was lumped together with the PCB busbar. The current path in busbar-A, shown in Fig. 3.11(a) between the DC+ and DC- terminals, causes mutual inductance cancellation between the busbar and module. The ceramic decoupling capacitors were replaced with copper squares in the model to act as a short to complete the loop. A representation of the current commutation loop path is shown in Fig. 3.13(a). Though the bridge in the busbar-A does not completely overlap with the module as seen in Fig. 3.13(a), the opposing currents in the bridge and the module lead to ﬂux cancellation, thereby reducing the inverterâA˘Zs´ decoupling loop inductance. The inductance of the localized commutation loop formed by the ceramic capacitors is therefore given by 3.3:

LCCL X 1 = LDS + LP 1 X 2MX (3.3) − − −

28 Figure 3.12 Heavy duty interconnect current density for 150 A, showing a maximum of 250 A/c m 2.

where the X will be replaced by the busbar design iteration (A, B, or C), LDS is the lumped self-inductance of the power module, LP 1 X is the inductance contributed by the decoupling current path in the busbar, − and MX is the mutual inductance between the module and busbar. This cancellation effect is assumed to be negligible with the DC-link capacitors due to their physical distance from the module. The inductance matrix extracted from Q3D at 10 MHz is given by (3.4).

LDS MA 10.46 nH 4.3 nH = (3.4) MA LP 1 A 4.3 nH 10.40 nH −

With mutual inductance cancellation, the inductance of the decoupling loop, LCCL A1, was extracted − from Q3D to be 12.8 nH at 10 MHz. The current distribution at 100 A DC in this loop is shown in Fig.

3.13(b). Mutual inductance cancellation has been approximated in simulation by subtracting the LS1 A of − the PCB busbar with the mutual indutance estimate such that the overall inductance of the commutation loop remains the same as LCCL A1. The extracted loop inductance estimates for this busbar and power − module are also reported in an earlier work [1]. However, the previously reported work contained mistakes in the Q3D simulation because the shield and AC laers in the busbar were not modeled. The current work’s models do contain those layers and the effect on the loop inductance is apparent when comparing numbers between the two works. The current work’s extracted loop inductance will be veriﬁed experimentally later, which underscores the importance of representing the busbar structure accurately in simulation.

3.4 Optimization of Busbar Design for Minimal Loop Inductance

The original busbar-A design was iterated upon to determine the effect decoupling capacitor placement had on the loop inductance and current distribution. In Fig. 3.11(a) it can be seen that any current flowing through the decoupling capacitors must flow through the bridge at the top of the busbar, resulting in the majority of the current tending to flow through the two top capacitors shown in the orange and red areas in Fig. 3.11(b). The primary goal of this placement optimization was to reduce

29 Figure 3.13 (a) Current path in in the busbar and decoupling capacitor current loop, (b) DC current density in decoupling capacitor current loop at 100 A. Notice the hot spots in the top two ceramic capacitors. Note the AC layers in the busbar and middle terminal in the module were eliminated in (a) for clarity.

the total power loop inductance from 12.8 nH to below 10 nH and the secondary goal was to place the decoupling capacitors in such a way that the current is not biased to ﬂow through only a small portion of the decoupling capacitors. The customized heavy duty connectors used to connect the module to the PCB busbar provide an opportunity to further reduce the localized commutation loop inductance. Because each connector can safely conduct 150 A and the power modules will draw less than 150 A at maximum power output, the connectors in the middle can be removed. Making this change in the busbar design allowed for not only an improvement in the inverter’s total loop inductance, but also a more balanced current distribution among the decoupling capacitors leading to higher reliability.

The first busbar design iteration, busbar-B, is shown in Fig. 3.14(a). This figure shows the removal of the middle row of module connectors and the placement of the decoupling capacitors directly over the module near the DC+ and DC- terminals. The new decoupling current loop path is visualized in Fig. 3.14(b). This design was simulated in Q3D and extracted components are shown in (3.5) and using 3.3, the total loop inductance for this design, LCCL B1 , was 7.0 nH. The reduction in loop inductance is − primarily due to the fact the current path through the decoupling capacitors is now much wider than busbar-A, resulting in lower magnetic flux and therefore lower inductance. Additionally, the placement of the capacitors directly over the module increased the mutual flux cancellation component of the inductance as seen by comparing the M value in (3.5) and (3.4).

LDS MB 10.46 nH 4.4 nH = (3.5) MB LP 1 B 4.4 nH 5.40 nH − However, as seen in Fig. 3.14(c), the current density in each decoupling capacitor is unequal because the decoupling capacitors placed on the right side of the module conduct more current than the capacitors on the left side. Therefore, the goal of the 2nd busbar design iteration, busbar-C, was to keep the

30 (a) PCB busbar-B design with (b) Current path in busbar-B and (c) Current density in decoupling lower self-inductance. decoupling capacitor current capacitor current loop. Notice the loop. difference in current distribution amongst the decoupling capacitors.

Figure 3.14 PCB busbar-B.

loop inductance low like busbar-B and also allow the current to ﬂow equally through each decoupling capacitor. To achieve better current sharing, the decoupling capacitors were placed as close to the module connectors as possible while still keeping the required clearance for 2 kV as shown in Fig. 3.15(a). Using this placement scheme, the current path from either DC+ terminal to the DC- bus in Fig. 3.15(b) is essentially the same length and width for each decoupling capacitor. As seen in Fig. 3.15(c) the current density in each capacitor is approximately equal, therefore it is assumed the current is no longer biased towards ﬂowing through one particular set of decoupling capacitor over the others. The power loop using busbar-C was simulated in Q3D and the results are shown in (3.6) with the current commutation loop inductance,LCCL C 1 , coming out to be 7.4 nH. − Table 3.3 shows a summary of the three busbar design iterations. Busbar-A had the highest total loop inductance due to the high self-inductance of the busbar itself while also having an unbalanced distribution of current amongst the decoupling capacitors. The layout in busbar-B improved the loop inductance by 45% which proved that changing the decoupling capacitor layout can drastically alter the loop inductance, but the decoupling capacitor distribution was still unbalanced which would lead to reliability issues. Although the loop using busbar-C achieved a slightly higher inductance than busbar-B, the current distribution was more balanced than the other two designs.

31 (a) PCB busbar-C design with lower (b) Current path in busbar-C and (c) Current density in decoupling self-inductance. decoupling capacitor current loop. capacitor current loop. Notice the uniformity in current distribution amongst the decoupling capacitors.

Figure 3.15 PCB busbar-C.

LDS MC 10.46 nH 4.33 nH = (3.6) MC LP 1 C 4.33 nH 5.62 nH −

Table 3.3 Summary of Q3D Results for Busbar Design Iterations

Element Busbar-A Busbar-B Busbar-C

LCCL 12.8 nH 7.00 nH 7.4 nH

Lb us b a r 10.40 nH 5.40 nH 5.62 nH Mutual 4.30 nH 4.40 nH 4.33 nH Current Distribution Unbalanced Unbalanced Balanced

To validate the reduction in loop inductance a single-phase version of busbar-C was manufactured; however, the busbar-B design was not manufacured due to its inferiority to the busbar-C design. Whereas the original busbar-A design was manufactured as an 8-layer PCB with 4 Oz. copper layers for use in system testing, the single-phase busbar-C PCB was manufactured using only 4 layers with 2 Oz. copper as a cost-effective way to take experimental data including double pulse tests (DPT) and impedance measurements to directly measure the inductance.

32 3.5 Experimental Results

The following section will discuss two experimental methods used to validate the design improvement described above.

3.5.1 Loop Inductance Extraction using an Impedance Analyzer

NCSU facilities do not have an impedance analyzer appropriate for the required measurements. Therefore, the hardware was sent to a PhD student under Dr. Andrew Lemmon at the University of Alabama in March 2018 because that lab owns a Keysight E4990A impedance analzer. The actual measurements were performed by the student under the guidance of the author. The power loop inductance was measured using a Keysight E4990A impedance analyzer when using busbar-A and busbar-C to validate the simulation results. The system was connected to the impedance analyzer through an adapter board whose design will be further discussed in the next subsection. First, measurements were taken on the adapter alone, shown in Fig. 3.16, to allow the machine to com- pensate for its parasitic impedance described in Section 2.4.1. With the compensation measurements taken the module, adapter, and busbar-A were assembled to perform the impedance measurement shown in Fig. 3.17. The impedance was swept between 20 Hz and 120 MHz and the single resonant point shown in Fig. 3.17(b) indicates a single capacitance resonating with an inductance. Analysis of the results result in a parasitic loop inductance of 12.2 nH.

Figure 3.16 Adapter compensation measurement.

The same measurements were taken using busbar-C in place of busbar-A. The impedance was

33 (a) Busbar-A measurement setup. (b) Busbar-A impedance measurement results.

Figure 3.17 Busbar-A impedance measurement.

(a) Busbar-C measurement setup. (b) Busbar-C impedance measurement results.

Figure 3.18 Busbar-C impedance measurement.

swept between 20 Hz and 120 MHz and the single resonant point shown in Fig. 3.18(b) indicates a single capacitance, the output capacitance of the lower switch of the power module, resonating with an inductance. Analysis of the results result in a parasitic loop inductance of 7.39 nH. A summary of the simulation and measurement results are shown in Table 3.4.

34 Table 3.4 Loop Inductance Results Summary

Busbar Simulation Measurement A 12.8 nH 12.17 nH C 7.4 nH 7.39 nH

3.5.2 Switching Characteristics using the Double Pulse Test

To characterize the switching behavior of the SiC inverter and measure the overvoltage seen by the devices under a worst case scenario, double pulse tests (DPT) were performed on a 800 V bus. Two sets of loads were used with the 1.2 kV SiC module. The first set included a load inductor sized to provide 220 A while the second set included two of these inductors to source 440 A. Both busbars were tested under both load conditions. The first two tests using the busbar-A design with the first test having only the DC-link capacitors populated and the second having both DC-link and decoupling capacitors to show the benefits in overvoltage reduction decoupling provides. To validate the improvement in loop inductance with the iterated design compared to the original, a third test was performed using busbar-C along with the DC-link and decoupling capacitors.

Table 3.5 DPT Results (800 V bus voltage)

Busbar Turn-Off Current Peak Voltage Overshoot A1 220 A 910 V 13.75 % A2 220 A 870 V 8.75 % C2 220 A 857 V 7.13 % A2 440 A 983 V 22.88 % C2 440 A 963 V 20.38 % 1 DC-link capacitors only 2 DC-link and decoupling capacitors

The DPT waveforms are shown for all three tests in Fig. 3.19(left) and the gate-source and drain- source voltages at turn-off are highlighted in Fig. ??(right). The voltage overshoot results are summarized in Table 3.5. The results in Table 3.5 clearly show the impact decoupling capacitors have on the voltage overshoot. With the addition of decoupling capacitors, the voltage overshoot from the ﬁrst test was reduced by 40 V. By optimizing the layout of the decoupling capacitors, the overshoot from the second test was reduced by another 13 V using busbar-C. An additional DPT was performed using the same bus voltage, but at 440 A at turn-off resulting in a 22.88% voltage overshoot using busbar-A and a 20.38% overshoot using busbar-C.

35 (a)

(b)

(c)

Figure 3.19 Left: Full DPT waveforms.

Right: VDS and VGS at turn-off. DPT waveforms with a 800 V source and 220 A at turn-off for (a) busbar-A with only DC-link capacitors, (b) busbar-A with DC-link and decoupling capacitors, and (c) busbar-C with DC-link and decoupling capacitors installed. Scaling for VDS in (b) was incorrectly set to 100 V/div, while the others are are 250 V/div.

36 3.5.3 DPT Simulation

The DPT circuit was also simulated in Simetrix and implements the parasitics model extracted from Ansys Q3D as well as MOSFET and diode models from Wolfspeed. The Simetrix schematic is shown in the Appendices. The simulation was done after the actual measurements had been performed to determine if such a simulation could be useful in the design stage of future work for predicting overvoltage stress on a system. Results are shown in Fig. 3.20 for the tests using both the DC-link and decoupling capacitors and the key results are summarized in Table 3.6.

(a)

(b)

Figure 3.20 DPT simulation results showing VDS (green) and VGS (red) for the lower switch of the half-bridge module in a run with a 800 V source and 220 A at turn-off. (a) Busbar-A: 871 V peak (b) busbar-C: 850 V peak

The results in the Table 3.6 can be compared to the results found in Table 3.5 and the reader can see there is good agreement in both the simulation and measured voltage overshoot. This agreement shows the DPT simulation can potentially be used in the future to predict switching performance to provide

37 Table 3.6 DPT Simulation Results (800 V, 220 A)

Busbar Peak Voltage Overshoot Rise Time A 871 V 8.88 % 31.9 ns C 850 V 6.25 % 31 ns

insight during the design stage of a project.

3.6 Benchmark Comparison

A 250 kW inverter was reported in 2017 using the same 1.2 kV SiC half-bridge module mentioned above with a traditional laminated busbar [41]. This section will brieﬂy describe that work and compare its performance to the current work. Table 3.7 compares the current work’s system with the benchmark system. The authors of the 250 kW inverter paper discuss their busbar’sdesign and presented simulations using FEA software to estimate the commutation loop inductance of their system including the busbar and interconnects. The authors measured their system’sloop inductance using a metal ﬁxture resembling the DBC in the power module without decoupling capacitors to be 10.8 nH.

Table 3.7 System Comparison between NCSU Inverter and Benchmark Inverter[41]

NCSU Benchmark Rated Power 135 kW 250 kW Operating DC-Link Voltage 1000 V 900 V Power Module HT-3231-R CAS325M12HM2 Power Density by Weight 16.46 kW/kg 15.63 kW/kg

Table 3.8 DPT Comparison between NCSU Inverter and Benchmark Inverter [41]

NCSU Benchmark DC Voltage 800 V 900 V Current 440 A 300 A RG ,EXT (on/off) 1Ω/2Ω 5Ω/5Ω Loop Inductance 7.4 nH 10.8 nH Voltage Overshoot 20.4 % 23.2 %

Wijenayake et. al performed DPT for their system using a 900 V bus voltage with a turn-off current

38 Figure 3.21 (Left) 135 kW NCSU Inverter and (right) 250 kW Benchmark Inverter [41] of 300 A and reported a 23.2% voltage overshoot. These results are summarized in Table 3.8 along with the high current DPT from the current work. It is important to point out the comparison in Table 3.8 is not exactly an "apples-to-apples" comparison because the two tests are not identical therefore limiting the types of conclusions that can be drawn. However there are enough similarities, such as the fact both systems used the CAS325M12HM2 power module for high current DPT, to stimulate discussion. Due to the fact NCSU’s turn-off current was higher and the gate resistance lower than in the benchmark inverter’s DPT, the NCSU inverter experienced a higher di/dt scenario. Regardless, the voltage overshoot was lower in the NCSU inverter. This result shows the PCB busbar with decoupling capacitors can achieve equivalent performance in terms of overvoltage suppression compared to a traditional laminated busbar. Additionally, this work has demonstrated an approach to directly measure loop inductance using impedance measurements with high accuracy.

3.7 Discussion

The design and analysis of the bussing for a 135 kW SiC inverter with low parasitic loop inductance using a PCB busbar and customized heavy duty connectors has been discussed in this chapter. Because the devices used in the power module of this inverter can have high edge rates, the loop inductance must be understood to improve the busbar’s design. The inductance contributed by the module, busbar, and interconnects to the commutation loop has been studied in depth. Based on the analysis using Ansys Q3D, an improved PCB busbar was designed using an iterative approach. The improved busbar design contributed to the low loop inductance by optimizing the placement of the decoupling capacitors. This optimization resulted in a parasitic decoupling loop inductance reduction from 12.8 nH in the original design to 7.4 nH in the optimized design. The extracted inductance values from Q3D simulations have been validated experimentally through impedance measurements with less than 5% difference between measurement and simulation, conﬁrming the Q3D simulation is reliable. The improvment in the busbar

39 design was validated experimentally by also using DPT, which showed a 19% relative reduction in voltage overshoot from the original design. A continuous high current test was performed to determine the expected temperature proﬁle of the busbar and interconnects during worst-case operation, which showed a 30 C rise in PCB busbar temperature. < ◦ The system in this study, having a PCB busbar and decoupling capacitors, was compared to a 250 kW inverter utilizing the same 1.2 kV SiC half-bridge power module, having a traditional laminated busbar without decoupling capacitors, in terms of voltage overshoot from experimental resuklts. This work underscores how a busbar’sdesign affects the system and highlights how understanding its parasitic loop inductance leads to insights useful in improving the system’s performance. The approach to simulating the power loop using Ansys Q3D for parasitic extraction and Simetrix for DPT performance prediction was validated after experimental tests were performed and will be used in the next chapter.

3.7.1 Measurement Adapter Design Lessons Learned

As described in Section 2.4.1, an adapter PCB must be designed to facilitate the connection between the busbar, module, and impedance analyzer for loop inductance measurements. Several papers discuss the results of busbar impedance measurements, but few discuss the details of their measurement setup in enough detail for others to perform similar measurements [32][19]. Lemmon and Grave’s work [27][28] was used as a reference for designing the initial adapter PCB. However, the goal of their work was to measure the self inductance of power modules whereas the goal of the current work was to measure the total loop inductance. Initial attempts to measure the busbar’s inductance were unsuccessful due to an inappropriate layout of the measurement adapter.

(a) Measurement adapter V1 (b) Measurement adapter V1 current distribution.

Figure 3.22 Measurement adapter designs.

40 An initial measurement adapter was developed based on Lemmon and Grave’s design shown in Fig. 3.22(a). Two copper areas exist to connect busbar’s DC+ and DC- terminals to four BNC connectors. A measurement of the parasitic loop inductance was attempted using this original measurement adapter design and busbar-A; the resulting difference between the simulated and measured inductance was greater than 50%. The adapter PCB and power loop were simulated together in Q3D, shown in Fig. 3.22(b) to investigate the source of this unacceptable difference and it was found that there was nearly 6 nH of mutual inductance cancellation between the adapter and busbar. This mutual inductance was unable to be compensated, which is according to (2.18).

(a) Measurement adapter V2 top (red) and (b) Q3D setup including the busbar-A DC+ bottom (blue) layers. (red), DC- (blue), module (yellow), and measurement adapter V2 (dark grey).

Figure 3.23 Measurement adapter V2

The philosophy of the ﬁrst adapter design was to measure the loop inductance created by the busbar and adapter, but this is not actually a useful method. Because the adapter is not actually part of the system when the inverter is operating, the actual loop consisting of the power module, busbar, interconnects, and decoupling capacitors must be measured. Therefore, a redesign of the adapter was needed. The new design’s approach consisted of breaking the power loop such that a small signal could be injected, as described in Section 2.4.1. The solution was to break the loop at the interface between one set of the power module terminals and busbar connectors. The layout of the second version of the adapter is shown in Fig. 3.23(a). The large holes near the center of the large copper pads were not meant to be plated, causing the top and bottom layers to be isolated from each other. This isolation forced current to ﬂow in one direction, shown in Fig. 3.24. Nylon screws were selected to mechanically connect

41 the busbar to the module to prevent the adapter layers from being shorted together.

Figure 3.24 Circuit diagram showing the current path in the impedance measurement. The decoupling capacitors were shorted using copper strips.

A shorted version of the new adapter and the total measurement system, shown in Fig. 3.23(b), was simulated in Q3D to determine if the new adapter design would improve measurement results. When the adapter is shorted, its extracted parasitic inductance from Q3D was 9.6 nH at 10 MHz. When the total measurement loop including the power module, PCB busbar-A, heavy duty interconnects, shorted decoupling capacitors, and measurement adapter PCB was simulated using Q3D, the extracted parasitic loop inductance was 21 nH at 10 MHz. Referring to (2.18), these extracted inductance values correspond to ZS and ZXM . The impedance of the total power loop is ZDUT . If the system is assumed to be purely inductive, the load and open measurements in (2.18) can be ignored. Therefore, estimation of the expected loop measurement using (2.18) simpliﬁes to the following:

ZDUT = ZXM ZS (3.7) − which, for a purely inductive system, is equivalent to:

LDUT = LXM LS (3.8) − where LDUT is equivalent to the expected LCCL A measurement, which was 11.4 nH at 10 MHz using − (3.8) and the extracted inductances above. Therefore, the expected difference between the inductance measurement and Q3D results was predicted to be nearly 11% for busbar-A. This simulation result

42 gave enough conﬁdence in the adapter’s design to manufacture and use it to perform impedance measurements. As shown in the measurement results, the actual measurement difference was around 5% for busbar-A. Therefore, the second version of the measurement adapter allowed for successful inductance measurements of the power loop. Based on the lessons learned in this measurement work, several recommendations can be made to ensure an appropriate measurement adapter is designed in the future. This knowledge will be applied to the work discussed in Chapter 4.

1. The power module must be present in the measurement setup to form a closed loop.

2. The physical size of the break in the loop where the adapter is connected must be kept small to reduce parasitic inductance contributed by the ﬁxture, resulting in higher measurement accuracy.

3. Mutual inductance between the adapter and other conductors can be kept low by minimizing the amount of overlap between it and other loop components

4. If possible, external BNC connectors should be placed in such a way that the adapter can be directly attached to the measurement equipment, eliminating the need for cables contributing to measurement error.

43 CHAPTER 4

DESIGN AND ANALYSIS OF A PCB BUSBAR SYSTEM FOR A 125 KVA SIC INVERTER

4.1 Introduction

This chapter will focus on applying the analysis techniques from the previous chapter to a new system. While the FEA analysis of the previous system was done after the ﬁrst design was manufactured, this chapter will use the same FEA approach to evaluate a bussing design prior to manufacturing. Additionally, this chapter will extend the analysis approach from the previous chapter by using the extracted decoupling loop inductance to determine the minimum required decoupling capacitance. In order to demonstrate the applicability of the loop inductance measurement method to other systems, a new loop inductance measurement PCB will be developed. This chapter will also add a thermal-electric FEA simulation to verify the busbar and interconnect thermal performance.

4.2 System Overview

The system in this chapter will be a 125 kVA SiC inverter used in an active harmonic ﬁlter having a DC bus that will ﬂuctuate between 800 and 900 V. The system will use three, 1.2 kV SiC six-pack modules [43] to create nine interleaved phases. A two-stage bussing approach will be used for the inverter consisting of a local busbar and global busbar. The local busbar is a small PCB having two main functions: 1) to provide electrical and mechanical connections between the power module and global busbar and 2) to allow placement of decoupling capacitors close to the power module thereby minimizing the decoupling commutation loop inductance. The purpose of the global busbar is to facilitate low impedance connections between the DC source, DC-link capacitors, and DC pins of the power module as well as the phase outputs from the modules and the load inductors. Figure 4.1 shows the bussing scheme graphically. The global level includes the global busbar and all external connections to the inverter. The local level includes three sets of local busbars and decoupling capacitors and is connected to the global busbar via heavy duty

44 connector screw terminals. The module level consists of the six-pack modules and each module is soldered into a local busbar. The design and analysis of the local busbar will now be discussed.

Figure 4.1 Wolfspeed’s 1.2 V Six-Pack power module.

4.3 Local Busbar Design

Figure 4.2 Wolfspeed’s 1.2 V Six-Pack power module.

The power module used in the AHF design is Wolfspeed’s CCS050M12CM2, consisting of three

45 separate 1.2 kV, 50 A half-bridges in a single package shown in Fig. 4.2. The devices for the three phases as well as the module’s pins are clearly shown in the figure. The fact this module has pins that must be soldered presents a problem: if every single pin is soldered into a busbar, removing the module without damaging the pins becomes difficult. Additionally, the six-pack module in Fig. 4.2 has a parasitic inductance equal to 30 nH, according to its datasheet [43]. The module pins are long and thin, thus they contribute significantly to its parasitic inductance. Any busbar connected to the module should be placed as close as possible to the face of the module to minimize the contribution of the module pins to the power loop inductance. Therefore, the local busbar was also designed to replace the module’s cover to minimize the decoupling loop inductance. However, to facilitate a low inductance connection between the global and local busbars, a low profile interconnect must be used in the local busbar design. Therefore, a local busbar was designed for "plug-n-play" operation by replacing the module’s pins with screw terminal connectors.

Based on the purpose of the local busbar discussed above, the board was designed to carry 50 ADC on the DC+ and DC- layers under worst case conditions. However, under normal operation of the system, only small rippler currents (<10 ARMS ) were expected to ﬂow through the board. The board is a 2 layer PCB with 4 Oz. layers and the widths of the DC+ and DC- plane were designed according to IPC-2221 to achieve an estimated 40 C temperature rise under worst case conditions. To achieve the ◦ required ampacity, the minimum width of the bus layers was determined using (3.1) to be 7.2 mm. The layout for the local busbar is shown in Figure 4.3.

4.3.1 Optimized Heavy Duty Interconnect Design

To achieve the low inductance, "plug-n-play" connection scheme for the power modules, screw terminal connectors needed to be designed into the local busbar. The two most important parameters when choosing the interconnects were (1) current carrying capability of at least 50 A, continuous, and (2) connector size. Due to voltage isolation requirements and the desire to not increase the footprint of the power module, there was very little room on the local busbar to place connectors. Most commercial connectors with the required current rating were simply too large to include in the design. Therefore, custom connectors were needed to achieve the current rating and size requirements. Initial designs were similar to the connector for the 135 kW system because previous thermal tests showed promising results for the temperature rise in the connector. The main goal for the design was to minimize the footprint of the connector while achieving the required current rating. Because the local busbar was designed to ﬁt within the cover of the module, space on the board was at a premium. The cover is only 32 mm wide, according to the module’s datasheet. That space must ﬁt several heavy duty connectors and have 3 mm of isolation between the DC power planes, phase outputs, and gate pins to sustain 4 kV. It was eventually determined a connector with a diameter of 8 mm would be small enough to achieve the required voltage isolation in the design. The

46 (a)

(b)

Figure 4.3 (a) Local busbar layout highlighting the top (DC+) layer, (b) local busbar layout highlighting the bottom (DC-) layer and pads for small ceramic decoupling capacitors near the DC source terminals.

parameter impacting the current rating the most is the surface area contact between the connector copper layers in the busbar and the pins on the connector. The main metric used to compare designs was the total contact surface area of the posts, calculated using (4.1).

SAt o t = N 2πr hC u (4.1) × Where N is the total number of posts, r is the radius of the posts in mm, and hC u is the total height of the PCB copper layers into which the connector is soldered. For a 2-layer, 4 Oz. board, this height is nearly 0.28 mm. The reasoning behind using this metric for connector design comparison is based on two assumptions: (1) all current ﬂowing out of the connector into the PCB will do so through the connector posts and negligible current will ﬂow through the large inner cylinder, therefore (2) a larger area in contact with the PCB layers will have lower current density at the connector-PCB interface resulting in a lower temperature rise. With these two points in mind, the goal for the connector design

47 is to maximize the above equation by optimizing the number of posts and post radii assuming the copper layer height is constant across designs. The caveat in using the surface area metric is that it only allows for the comparison of designs; more parameters must be considered to analytically predict the temperature rise in the connector which were not considered.

(a) (b) (c)

Figure 4.4 (Top)reference connector, (a) connector design A, (b) connector design B, (c) connector design C

Several design iterations, shown in Fig.4.4, were considered for the heavy duty interconnect which are summarized in Table 4.1 with more details in the Appendix. The reference connector is the connector from the previous chapter. Both design-A and design-B were able to conduct the required amount of current, however they were too large because manufacturing methods placed constraints on minimum feature sizes. Because the distance between posts in the connectors is small (<2 mm), when a machine shop attempts to manufacture these connectors they must use an appropriately sized high precision bit. Because of that requirement, manufacturing these connectors was prohibitively expensive and alternative designs were explored. Instead of designing the posts to be features of the connector, the posts were instead designed to be part of the circuit board as small plated holes ﬁlled with solder. Printed circuit board manufacturers have the ability to make very small features on circuit boards compared to machining services [2]. By moving the posts from the connector to the PCB, a much smaller connector could be designed resulting in design-C which was ultimately manufactured. To facilitate the connection between the local and global busbar, two sets of connectors were manufactured with one set having M3 threads at 0.5 mm pitch and the other unthreaded. The assembled module and local busbar is shown in Fig. 4.5.

48 Table 4.1 Summary of Heavy Duty Interconnect Design Iterations

Parameter Reference Connector Design A Design B Design C Connector Size 14 mm 8.8 mm 10 mm 8 mm Screw Size M4 M4 M3 M3 2 2 2 2 SAt o t 15.80 mm 13.46 mm 21.10 mm 17.87 mm

Figure 4.5 Assembled power module and local busbar showing "plug-n-play" conﬁguration.

4.4 Design Analysis using FEA

The local busbar and power module were simulated using FEA tools to estimate the power loop inductance and thermal performance of the local busbar.

4.4.1 Model Preparation for FEA Analysis

For the purpose of FEA analysis, a 3D model of the local busbar, heavy duty interconnects, and power module were created. The models for the local busbar and heavy duty interconnect were made using the process described in 2.3.5. The power module model was reused from previous work by Xu [45]. An example of the model is shown in Fig. 4.6. The model in this ﬁgure shows the inner DBC, devices, wirebonds, and pins within the module along with the DC+ and DC- layers in the local busbar PCB. It is important to note the model used in Ansys Q3D disregards any conductors related to the phase outputs or gate signals because they have negligible effect on the parasitic loop inductance. However, the model used in the Ansys thermal-electric simulations requires a full model of the local busbar, including its FR-4 substrate, to accurately predict the temperature rise in the board. The only materials in the Q3D simulation were conductors, but the thermal conductivity of all materials including module and PCB substrates, encapsulant, and conductors must also be modeled.

49 Figure 4.6 FEA model showing local busbar and power module used in Ansys Q3D for parasitic inductance extraction.

Table 4.2 Decoupling Loop Inductance Extraction Considering Different Phases

Phase Loop Inductance A 33.6 nH B 30.0 nH C 33.6 nH

4.4.2 Decoupling Power Loop Parasitic Extraction

The parasitic loop inductance extraction procedure is the same as the procedure described in 2.3.5. However, unlike the power module in the previous chapter, the three phases in this power module are separate and thus must be simulated separately to extract their loop inductances. Because the decoupling capacitors are placed at either end of the local busbar, phases A and C were assumed to have the same current path with respect to the local busbar. However, the middle phase B current path is different. Therefore, an extraction of parasitic loop inductance for the three phases can be accomplished in two simulations: (1) a phase A/C simulation and (2) a phase B simulation. In these two cases, the phases not being simulated are simply ignored by the simulation. For both simulations, an assumption was made about the current path of the loop. In the phase A/C simulation, it is assumed the current will only ﬂow only through the set of DC source terminals closest to the phase. Whereas in the phase B simulation, current ﬂow is assumed to split between the two sets of DC source terminals because phase B is in the middle of the module. The assumption for the phase B simulation was made because it was expected there will be some amount of energy storage capacitance on both sides of the module. Lumped parameter results are shown in Fig. 4.2. Only the loop inductance including phase A will be considered from this point on because it’s the easiest phase to analyze.

50 Figure 4.7 Current density of phase A/C and the local busbar from Ansys Q3D at 50 ADC

Figure 4.8 Current density of phase B and the local busbar from Ansys Q3D at 50 ADC .

LDS MLo c al 31.40 nH 1.39 nH = (4.2) MLo c al LLo c al 1.39 nH 5.00 nH

Equation (4.2) breaks out the lumped loop inductance value into the self and mutual values. LDS is the inductance contributed by phase A of the module, LLo c al is the inductance from the local busbar and is the same as LP 1 in Fig. 4.9, and MLo c al is the mutual inductance between the power module and local busbar PCB.

4.4.3 Required Decoupling Capacitance

As mentioned in Section 2.3.1, decoupling capacitors are discussed as a way to reduce overvoltage stress on switching devices by providing a low impedance path. One approach to selecting decoupling capacitors for a system is to simply maximize the amount of decoupling capacitance, given size constraints. This certainly works, but there should be some understanding of the decoupling method to place a minimum requirement on the decoupling capacitors to ensure reliability. Chen et al. recom-

51 mends decoupling capacitance to be 50 times greater than COSS to achieve sufﬁcient decoupling as a general blanket statement [14]. According to the power module datasheet, the output capacitance for one switch in the power module is 393 pF at 800 V bias, therefore requiring a minimum decoupling capacitance of 19.65 nF per the Chen paper. This is a good starting point in determining the minimum decoupling capacitance for the system, but the following discussion will use the extracted parasitic inductance from Q3D to deﬁne the minimum decoupling capacitance using the same analysis used in the paper to verify Chen et. al’s recommendation for this study’s system.

4.4.3.1 Minimum Decoupling Capacitance Analysis

Figure 4.9 Equivalent circuit of parasitic inductance in a single leg of an inverter with DC-link and decoupling capacitors.

Recall the ﬁgure from previous chapters showing the equivalent parasitic inductance circuit for a power loop including a half-bridge phase leg, decoupling capacitors, and DC-link capacitors shown in

Fig. 4.9. There are two inductive loops shown in that ﬁgure with one loop (LCCL 1) consisting of the − power module, local busbar, and decoupling capacitor parasitics and the other (LCCL 2) including the − power module, global busbar, and DC-link capacitor parasitic elements:

LCCL 1 = LDS + LLo c al 2MLo c al (4.3) − − The decoupling capacitor’s ESL will be ignored for this analysis because multiple small ceramic capacitors are typically placed in parallel, thus minimizing their total ESL.

LCCL 2 = LDS + LP 2 + LP 5 + LESL 2MG l o b al (4.4) − −

52 Where LP 2 and LP 5 are the partial inductances from the global busbar, and MG l o b al is the mutual inductance between the global busbar and power module. From Fig. 4.9, it is apparent there will be parallel resonance between the decoupling loop induc- (COSS +C J ) tance and the output capacitance of the devices and diode, 2 . The resonant frequency can be approximated simply under the assumption any parasitic resistance is negligible:

1 ωPR = p (4.5) LCCL 1 (COSS + C J ) − × Because the decoupling capacitor is present in the circuit, there is an additional low frequency resonance between the inductance from the global busbar current path and the decoupling capacitor, approximated using:

1 ωLF = p (4.6) (LP 2 + LP 5 + LESL ) Cd e c × Therefore, the general approach to determining the required minimum decoupling capacitance is to ensure Cd e c is large enough such that the inductance from the DC-link current path does not affect the high frequency ringing. The impedance circuit in Fig. 4.10(a) can be used as a tool to conceptualize this approach. ZDS is the impedance from the power module’s parasitic inductance, Z1 is the impedance of the decoupling capacitor, and Z2 is the impedance from the DC-link current path’s inductance,

LP 2 + LP 5 + LESL . All of these impedances (4.7-4.9) are calculated at the parallel resonant frequency,

ωPR .

ZDS = j ωPR LDS (4.7)

1 Z1 = (4.8) j ωPR CD e c

Z2 = j ωPR (LP 2 + LP 5 + LESL ) (4.9)

To clarify this approach, the parallel impedances should be much less (<5%) than the power module’s impedance, such that:

Z1 Z2 << ZDS (4.10) | k | | | LCCL 1 was extracted using Ansys Q3D to be 33.6 nH in the previous section. Therefore, the expected − parallel resonant frequency, ωPR is expected to be 43.8 MHz. At the time this is written, the global Busbar has not been designed nor simulated; therefore, LP 2 + lP 5 was assumed to be 15 nH and the DC-link ESL to be 5 nH.

53 (a) Equivalent impedance circuit in a single leg of the (b) Equivalent circuit of parasitic inductance in a single leg of inverter for decoupling capacitance analysis. an inverter with DC-link and decoupling capacitors.

Figure 4.10 Decoupling Impedance Analysis

A script was written in Matlab to sweep decoupling capacitor values to determine when (4.10) is satisﬁed.The ratio of the parallel impedance to module impedance was compared against the decoupling to output capacitance ratio, plotted in Fig. 4.10(b). From the plot, the impedance ratio is reduced to nearly 5% when the decoupling capacitor is roughly 20 times higher than the output capacitance. Therefore, the minimum capacitance required to acheive a reduction in voltage spike for the assumptions stated above is 7.86 nF,but should be maximized to ensure low voltage spikes. Chen et. al’s recommendation to make the decoupling capacitance at least 20 times higher than the output capacitance is valid for this system.

4.4.4 DPT Simulation

An equivalent circuit of the parasitics in the local busbar and power module was exported from Q3D and used in a Simetrix simulation to verify the decoupling capacitor analysis and predict voltage spikes for the system. As in the previous chapter, the circuit for this simulation is in the Appendix. It was assumed a 1.5 mF DC-link capacitor with an ESL of 5 nH will be used in the system and the parasitic inductance from the global busbar will be 15 nH as in the analysis above. A double pulse test was simulated at a DC-link voltage of 800 V and a turn-off current of 50 A.

Figure 4.11 shows plots of the device VDS , VGS , and load inductor current. The VDS chart for the case in which no decoupling capacitor shows a 207 V spike and a single ringing frequency of 33 MHz. In this case, the only loop inductance present is LCCL 2, which was assumed to be around 51 nH in total from − (4.4). Therefore the ringing is a result of the resonance between LCCL 2 and COSS . Figure 4.11(b) shows − a case where there are two clearly two different frequency oscillations occurring and a voltage spike 49 V lower than the case without a decoupling capacitor. The simulation shows the high and low frequency ringing to be 37.0 MHz and 5.8 MHz, respectively. These values agree with the theoretical values from

54 (4.5) and (4.6), which are 36.5 MHz and 5.68 MHz. This case can be considered fully decoupled because the two frequencies are nearly a decade apart from each other.

Table 4.3 DPT Simulation Results for Different Decoupling Capacitance Values

CDEC /COSS Peak Voltage Overshoot 0 1.007 kV V 25.9 % 20 (CDEC =7.86 nF) 969 V 21.1 % 100 (CDEC =39.3 nF) 958 V 19.8 % 1000 (CDEC =393 nF) 939 V 17.4 % VDC = 800 V, IL = 50 A Assumed RG = 1 Ω, LCCL 2 = 51 nH −

Table 4.3 summarizes the results for several other simulations, including the minimum recommended decoupling capacitance of 7.86 nF.The results in the table indicate the device will experience less than a 170 V spike when it switches 50 A with proper decoupling. At the time of writing, it is expected the DC-link voltage will ﬂuctuate between 800 V and 900 V during operation due to voltage ripple. Therefore, in the worst case where the DC-link voltage is 900 V and one phase is conducting 50 A, the DPT simulation suggests there will be at least a 130 V margin for the 1.2 kV devices. Larger decoupling capacitance values will further reduce the voltage spike, but with diminishing beneﬁts; reducing the decoupling capacitance will also decrease ωLF according to (4.6).

55 (a)

(b)

Figure 4.11 DPT simulation results for the power loop in the 125 kVA inverter for (a) no decoupling capacitor and (b) CDEC = 39.3 nF.

4.4.5 Local Busbar Thermal-Electric Analysis

The temperature ratings of PCB substrate materials are commonly described in terms of glass transition temperature (Tg ), decomposition temperature (Td ), or both [3]. The glass transition temperature describes the temperature at which a polymer transitions from a rigid to a softened state. The decomposition temperature describes the temperature at which a material chemically decomposes; it will also most likely lose mass. A study by Oriol et. al studied the effect of exceeding the Tg value for two common PCB substrate types, FR-4 and polyimide, for long amounts of time (> 100 h). Their tests

56 showed signiﬁcant changes in substrate weight, via resistance, and capacitance for both materials [7]. Therefore, long-term reliability of a PCB is affected by high temperatures and if a system is implenting a PCB busbar it is important to understand the expected temperature rise to determine the appropriate substrate material. One method of understanding the temperature rise in a PCB busbar is to perform a thermal-electric simulation using FEA software. A thermal-electric simulation couples the electrical and thermal behavior of the circuit two accounts for the fact that electrical conductivity changes withe temperature. This behavior affects power loss and temperature rise in a busbar. One objective of the thermal-electric simulation was to determine where the highest temperature rise in the local busbar would be and to validate that that temperature rise is acceptable under expected operating conditions. Additionally, this simulation would also allow for the determination of whether the power module cooling effects local busbar cooling. Ambient conditions for the simulation assumed the surrounding air would be 40 C. It was assumed the ◦ cold plate for the inverter would be able to keep the bottom side of the DBC at a constant 50 C. ◦

(a) Model of the local busbar and power module (b) Model showing volumes of air (top) and geometry for thermal analysis. encapsulate (bottom) in the model.

Figure 4.12 Thermal-electric simulation model.

The geometric model for thermal-electric analysis differs from the Q3D model used in two ways: (1) it models all of the relevant geometry in the busbar and module and (2) each material is deﬁned to

57 Table 4.4 Assumed thermal conductivity of thermal-electric simulation materials.

Material Thermal Conductivity (W/mK) AlN [16] 170 FR-4 [8] 0.29 1 Silicone gel [30] 2.8 4H-SiC [31] 400 1No details were given about the gel in the module’s datasheet, so details were used from a silicone gel material that could have been used in its manufacturing.

obtain more reliable results. Although the material of the PCB substrate in the local busbar is irrelevant in the Q3D simulation, the material must be defined for a thermal-electric simulation because heat also flows into and out of this substrate. Similarly, the substrate and device materials must be defined for of the power module for the same reason. The material in the substrate of the local busbar is FR-4, while the substrate material in the power module is aluminum nitride (AlN). Therefore, these materials were modeled in Ansys along with the silicone gel in the power module. Table 4.4 lists the thermal conductivity these materials along with the silicon carbide dies. A copper alloy from the materials database in the software was used to define the PCB layers and the DBC. Figure 4.12(a) shows a model of the local busbar and power module for a thermal-electric simulation. A volume of air having the same thickness as the distance between global and local busbars, about 3 mm, was modeled to estimate the effects of air cooling. It had a roughly 20% larger surface area compared to the local busbar model was also created for simulating the thermal interface between the surrounding air and PCB. It was assumed this convection would dominate any cooling of the PCB from the power module’s cold plate because the thermal resistance from the local busbar to the module’s baseplate was assumed to be very high. Figure 4.12(b) shows the air (top box) and gel (bottom box) in the module. Although the air and gel were present in the simulations, the results will not show them the sake of simplicity. Figure 4.12(c) shows an example the meshing used for the local busbar and power module. Two different scenarios were simulated. The first considered 50 A flowing from the DC positive connection in the local busbar through one phase of the power module and out through the AC connection. The current density and thermal profile are shown in Fig. 4.13. As seen in the image, the hottest point in the local busbar is the AC connector because the surrounding copper area on the PCB is small in area which limits heat transfer between the copper and air. However, there was only a 32 C temperature rise ◦ in this connector which is good considering the connectors were designed for a 40 C temperature rise. ◦ This serves as partial validation of the connector and local busbar design.

58 (a) Temperature proﬁle of the local busbar PCB and (b) Current density of the local busbar PCB and

power module when conducting 50 ADC power module when conducting 50 ADC

Figure 4.13 Thermal-electric simulation results

4.4.6 Power Loop Inductance Measurement PCB Design and Analysis

Similarly to the loop inductance measurements in the previous chapter, loop inductance measurements for the current system were also desired for design validation. Because of the current project uses a different power module and busbar, the exact same measurement adapter cannot be used to make loop inductance measurements. However, the bussing system in the current study also utilizes PCB busbars; a similar approach as the previous study to developing a loop inductance measurement adapter PCB was used. Although the primary goal of this effort was to measure the decoupling loop inductance, secondary goals included the measurement of the parasitic inductance of the loop composed of the power module and DC-link capacitor as well as the gate-source loop inductance of the power module. To achieve these goals, 3 sets of BNC connectors were designed to be placed onto the PCB. Because the local busbar was designed to replace the original cover of the power module, that PCB could be no larger than that case. Measuring the loop inductance would require placement of BNC connectors onto a board which would become to big to fit inside the module. Therefore a measurement border design approach was adopted that replicates the local busbar on a different PCB that also includes BNC connector pads. Therefore during the measurement, only this inductance measurement PCB would be connected to the power module instead of the approach in the previous chapter where an adapter PCB was placed between the power module and the busbar. The initial design’s layout is shown in Figure 4.15. The layout shown in the figure can be described in four parts. The first part is in the center of the board which is basically the same geometry as the local busbar described above. The next three parts include three sets of four BNC connectors to allow for the measurements of three different loops using the same impedance measurement method that as the previous chapter . The set of connectors on the left side the board are for measuring the decoupling loop inductance composed of the local busbar,

59 Figure 4.14 Diagram highlighting where three separate loops in the system will be broken to measure their inductance using the ZA and measurement PCB.

Figure 4.15 Design 1: Loop inductance measurement PCB layout. Numbered annotations refer to the numbered loops in Fig. 4.14.

power module, and decoupling capacitors. The set of connectors on the bottom edge of the board will measure the gate-source inductance contributed by the power module.The ﬁnal set of BNC connectors on the right hand side of the board measure of the loop composed of the power module, global busbar, and DC-link capacitors. This design was evaluated similarly to the measurement adapter PCB in the previous chapter. First, the design was modeled in Q3D. The traces on the left side of the board attached to the decoupling loop BNC connectors were shorted using rectangular block at the position of the decoupling capacitors. The board was simulated to extract the inductance of the ﬁxture. This process was repeated for the two others sets of BNC connectors where each set of faces was shorted together before simulation.Then the six-pack power module model was attached to the measurement PCB’s model and the two were simulated together to extract the total loop inductance of the measurement PCB, local busbar, and power module. With these two extracted parameters simulated, the same method of determining the expected difference between the simulation and measurement results was employed. The expected

60 measured inductance value for the decoupling and gate loop along with the expected difference from Q3D simulation are summarized in Table 4.5 which shows an expected 22.5 % and 7.0 % difference, respectively, between the original Q3D simulated and expected measurement value. For comparison, the expected difference in the previous chapter’s measurement was 11% when, in reality, it was 5%.

Figure 4.16 Ansys Q3D model of the power module with the measurement PCB attached.

One source of difference between measured and simulated DUT inductance is the impedance contributed by parasitic elements from the measurement ﬁxture. In this case, the DUT is whichever loop is being measured: the decoupling loop, gate loop, or DC-link loop. In the case of the decoupling and gate loops, the physical hardware for the DUT is the local busbar copper and power module, while the DC-link loop includes the power module, local busbar, heavy duty interconnects, and global busbar. Only the decoupling and gate loops will be considered in the current discussion. The measurement ﬁxturing in this study includes the BNC connectors themselves and the copper traces on the measurement PCB connecting the BNC connectors to the DUT. Both of these components have self-inductance,

LS , which is compensated using the short portion of the OPEN-SHORT-LOAD technique described in previous chapters. A short compensation for a ﬁxture would exactly mimic the current path in the actual measurement; in such a case, the compensated residuals would equal the actual impedance of the residuals. The difference between measured and simulated loop inductance is most likely proportional to the difference between the compensated and actual residual impedances. Therefore, the approach to improving this measurement PCB’s design was focused on reducing the parasitic inductance of the ﬁxturing on the measurement PCB. An attempt was made to modify the design of the measurement PCB to reduce its contributed

61 parasitic inductance to the measurement loop. To achieve this goal, the BNC connectors were placed as close as reasonably possible to the module’s pins. This placement reduces the length, and therefore inductance, of the traces connecting the BNC sockets to the DUT.Using this consideration, modiﬁcations to the measurement PCB were made and the second design is shown in Fig. 4.17. This design was evaluated the same way as the original, and the results are summarized in Table 4.5.

Figure 4.17 Design 2: Loop inductance measurement PCB layout. Numbered annotations refer to the numbered loops in Fig. 4.14

Table 4.5 Busbar Measurement PCB Analysis Summary

Parameter Design 1 Value1 Design 2 Value1

LS,d e c o upl i ng 17.48 nH 10.93 nH LS,g a t e 11.74 nH 11.13 nH LS,l i nk 12.21 nH 11.23 nH LXM ,d e c o upl i ng 42.52 nH 38.47 nH LXM ,g a t e 32.56 nH 33.89 nH LDUT,d e c o upl i ng 25.04 nH 27.54 nH LDUT,g a t e 21.07 nH 22.76 nH Expected Difference (Decoupling Loop)2 22.5 % 14.7 % Expected Difference (Gate Loop)3 7.0 % 1.7 % 1Values were extracted from Ansys Q3D for a 10 MHz simulation. 2A 33.6 nH decoupling loop inductance was extracted using Ansys Q3D for phase A . 3 A 22.28 nH gate loop inductance was extracted using Ansys Q3D and agrees with Xu’s work [45].

62 The improvement in the expected difference between the measured and simulated loop inductance using the second measurement PCB is shown in Table 4.5. For the decoupling loop, the expected difference using the improved measurement PCB is 14.7% compared to the ﬁrst design’s 22.5% difference. Similarly, the gate loop measurement is expected to differ from simulation results by only 1.7% using the second design; compared to the ﬁrst design’s expected 7.0% difference, this is a 76% improvement. Based on these metrics, the second design was manufactured for use in the impedance measurements because it was expected to be more accurate.

4.5 Experimental Results

At the time of writing, the project this work is a part of is still in the design phase. As such, the global busbar’s design has not been ﬁnalized or manufactured. Therefore, experimental tests that can be performed on the current hardware is limited to the measurement of the decoupling and gate loop inductances.

4.5.1 Parasitic Inductance Extraction using Impedance Measurements

The loop inductance measurement PCB design from Fig. 4.17 was manufactured and is shown in Fig. 4.18. The board in the ﬁgure connects to the Keysight E4990A impedance analyzer in exactly the same way as the previous chapter’s PCB shown in Figs. 3.17 and 3.18. As in the measurements from the previous chapter, the frequency was swept from 1.2 kHz to 120 MHz and the impedance was recorded. Unfortunately, only the parasitic inductance of

(a) Manufactured measurement board.

Figure 4.18 Impedance analyzer results using the local busbar measurement PCB.

Impedance results are shown in Fig. 4.19 for the gate loop and decoupling loop measurement and the extracted inductance values from Q3D and these measurements are compared in Table 4.6. As

63 shown in the table, the difference between the extracted parasitic gate inductance inductance from the Q3D simulation and impedance measurements is 6.8 %.

Table 4.6 Local Busbar Extracted Inductance Summary

Parameter Simulated Value Measurement Value Difference Gate Loop Inductance 22.28 nH 23.8 nH 6.8 %

(a) Impedance analyzer results for the gate loop measurement with ﬁtted RLC parameters. The internal gate resistor is apparent in the impedance plot.

Figure 4.19 Impedance analyzer results using the local busbar measurement PCB.

4.6 Discussion

This chapter discussed the design, analysis using FEA tools, and veriﬁcation of a portion of the bussing system for a 125 kVA inverter. The local busbar, the focus of this chapter, was designed to achieve three goals: (1) to allow the power module to have external connections using screw terminals, (2) to allow for the placement of ceramic decoupling capacitors close to the power module source terminals to achieve a low decoupling loop inductance, and (3) to be able to connect and safely conduct

50 ADC between the two sets of DC source terminals of the power module. The ﬁrst goal was achieved by designing specialized heavy duty interconnects with tapped holes capable of carrying 50 A. The second goal was achieved by designing pads allowing the placement of ceramic capacitors on the bottom side

64 of the local busbar; extraction of the power loop inductance using Q3D allowed for the determination of the minimum decoupling capacitance value for limiting transient voltage spikes. The third goal was addressed during the design phase of the board by making the copper plans as large as possible. Thermal-electric simulations were used to predict the PCB’s expected temperature proﬁle at maximum current; the simulation results indicate the local busbar will have a 40 C temperature rise above < ◦ ambient under these conditions. Impedance measurements were used to experimentally extract some of the parasitic loop inductances of the system. The main focus of the simulations in this chapter was the extraction of the decoupling loop inductance, however the gate loop inductance was also extracted. The decoupling and gate loops were measured and their loop inductances were extracted. Simulation results from Q3D indicated the decoupling and gate loop inductances were 33.6 nH and 22.3 nH, respectively. Extracted inductance values from impedance measurements showed a X % and 6.8 % difference, respectively, from the FEA results.

65 CHAPTER 5

CONCLUSION

5.1 Summary

The primary focus of the previous chapters was to demonstrate an approach to analyzing the parasitic loop inductance in a high power system for the purpose of optimizing the PCB busbar design. The first chapter introduced the topic of high power inverters and the performance advantages SiC has over Si technology. In particular, the use of PCB busbars was discussed as a means to create power dense systems. The design of PCB busbars is important to ensure reliability in terms of device voltage spikes and PCB temperature rise; these concerns can be addressed through finite element analysis. The second chapter starts with a review of other works on the topic of busbar analysis and optimization and then discusses some of the theory of parasitic elements. The bulk of the chapter wass focused on providing general descriptions of simulation and experimental-based approaches to analysing PCB busbar designs. Chapter 3 focused on applying the approaches from Chapter 2 to analyze and optimize a PCB busbar in an actual system. A 135 kW SiC EV traction inverter with a PCB busbar was used for this study. The components comprising the current commutation loop for the inverter were modeled in Ansys Q3D to gain a full understanding of the parasitic loop inductance. The loop inductance using the first PCB busbar design was 12.8 nH and by optimizing the decoupling capacitor layout on the PCB, it was reduced to 7.4 nH. The busbar design was experimentally validated using two methods: impedance measurements and double pulse tests. Impedance measurements using a Keysight E4990A were used to extract the parasitic loop inductance. The extracted values were in agreement with Q3D results having less than 5 % difference between the measured and simulated loop inductance. The double pulse test results indicated a 19 % relative reduction in voltage spike using the optimized busbar design compared to the original. The inverter in this study was compared to a 250 kW benchmark inverter having a traditional laminated busbar. The comparison highlights the fact the PCB busbar can have equivalent performance as a laminated busbar in terms of loop inductance and voltage spikes. Chapter 4 built on the work in Chapter 3 using a 125 kVA inverter with a PCB busbar for the study.

66 Whereas Chapter 3 focused on analysing a PCB busbar that had already been manufactured, the study in Chapter 4 considered the analysis of the PCB busbar during the design phase of the project. This focus allowed for the assurance that the PCB busbar will not negatively affect system performance or reliability. The design of part of a PCB bussing system and custom heavy duty interconnects was discussed. The current commutation loop was modeled in the same way as Chapter 3 and the parasitic loop inductance was extracted to be 33.6 nH. This chapter extended the analysis of the previous section by using the extracted loop inductance to determine the required minimum decoupling capacitance for reduced voltage spikes. Some assumptions were made about the parasitic inductance in a PCB still under development and a DPT simulation was performed to estimate the voltage spike. These results showed the expected device voltage spike will be less than 157 V without proper decoupling capacitors. When proper decoupling is present, the spike can be decreased by at least 8 %. Additionally, a thermal-electric simulation was performed using Ansys to predict the PCB busbar’s thermal performance for design validation. The simulation predicts a < 40 C temperature rise in the busbar and heavy duty interconnect, which is acceptable. Finally, the ◦ design of another measurement PCB is discussed and analyzed using Ansys Q3D. From this analsis, it was predicted the extracted decoupling loop inductance from impedance measurements will differ by almost 15 % from Q3D and the gate loop inductance will differ by less than 2 %. In reality, the difference was 6.8 %. The agreement between simulation and experimental methods of extracting loop inductance indicates FEA modeling provides a high degree of accuracy in determining parasitic inductance.

5.1.1 PCB Busbar Design and Analysis Methodology

Like many other engineer and problems, the design of PCB busbars is a delicate balance between several requirements including voltage isolation, current carrying capability, parasitic elements, and mechanical connections. Although the electrical engineer can design for the first two items, it is not always easy to ensure low loop inductance and capacitance analytically; experience designing low inductance power loops is valuable in this respect. However, systems are often multidisciplinary and require mechanical mounting and cooling or they might have vibration requirements. These are the realm of the mechanical engineer and require placement of holes and slots into the board which can negatively impact current flow and loop inductance. Although the impact mechanical footprints have on these effects may be obvious in a qualitative sense, quantifying these effects may be more difficult. The desire to understand the effects of complex geometries on the thermal and electromagnetic behavior in the busbar makes FEA tools very useful. The iterative design and analysis methodology for PCB busbar design is summarized below and in the block diagram in Fig. 5.1: 1. Determine PCB busbar requirements in terms of voltage sustainability, ampacity, and mechanical mountings. The required voltage isolation will most likely be much higher than the operating voltage of the system because moisture, temperature, and elevation can reduce the ability for materials to insulate

67 Figure 5.1 Block diagram describing an iterative busbar design process using simulation tools.

conductors [37]. 2. Lay out the components that will take up the most space first, such as power devices and DC-link capacitors. This allows the engineer to readily identify critical current paths affecting the PCB’s current carrying capability and loop inductance. By focusing on these areas, the engineer can avoid narrow copper paths that negatively affect ampacity and loop inductance. 3. Model the busbar using an FEA tool to better understand the current flow in the busbar alone. Overlaying the current density on the surface of the busbar’s model allows the engineer to visualize the critical current paths in the busbar. This effort will provide better understanding of the critical current paths in the busbar and may or may not validate the engineer’s ideas from the previous point. Thermal- electric simulations can also be performed at this point to verify the design’s thermal performance. 4. If three-dimensional models of other conductive components constituting the power loop exist (e.g. power modules/devices, DC-link capacitors, interconnects), combine them with the PCB busbar’smodel to simulate the power loop inductance for the system. It is imperative to simulate the major conductive components together for a full understanding of the power loop because mutual flux cancellation, as discussed in this document, plays a large part in determining inductance. A quantitative description of the effect on loop inductance from mutual flux cancellation is likely difficult otherwise. 5. Once the parasitic loop inductance is extracted from FEA simulation, those values can be used to predict aspects of system performance, such as voltage overshoot and EMI, via circuit simulations. 6. If the results of the parasitic extraction and thermal-electric simulations are not acceptable, the busbar’s design can be modified until it produces acceptable results. 7. Regardless of whether the design was iterated upon or not, if simulation results point towards acceptable behavior then the busbar can be manufactured. Loop inductance measurements and DPT, both of which are discussed in this document, can be employed prior to the integration of the busbar into the full system. These tests serve to validate simulation results and provide full understanding of

68 the busbar’s effect on system performance.

5.1.2 The Role of Busbar FEA Analysis in System Design and Analysis

Electrical power systems can include many different components including batteries, power converters, and loads. Successful projects will model most of these systems to predict overall performance and validate design goals. Figure 5.2 below shows a hierarchy describing models used in a system and is adapted from Wheeler’s discussion of more electric aircraft [40]. As model become more detailed, they are able to more accurately predict the dynamic behavior of systems at the cost of model complexity and simulation time. The device layer might include power semiconductor models for parasitic networks. These models will have the highest bandwidth and are used for component level veriﬁcation. Behavior models might include circuit simulations with lumped parameters and bandwidth in the hundreds of kilohertz. These models can predict switching behavior of the system. A functional simulation contain- ing averaged models may only have a bandwidth in the thousands of kilohertz range and can be used to determine control system performance. Architectural layer simulations are the least complex, capable of only steady state results, and can be used in system-level design.

Figure 5.2 Modeling levels of electrical systems. Adapted from [40].

The FEA models described in the previous chapters surely ﬁt in the device layer because they are complex and serve to only inform the design of the PCB busbar. However, the results from these models, such as lumped parasitic values and switching energy loss, can be used in behavioral layer models to predict their effect on the system power loss and component temperature rise. By using FEA models to fully understand how a PCB busbar will affect the system, performance estimations can be made more accurate. In summary, the value proposition for using FEA tools to model and simulate a PCB busbar is assurance of busbar performance at the design stage of a project as opposed to after it has been manufactured.

69 References

[1] Aberg, B. et al. “Estimation and minimization of power loop inductance in 135 kW SiC traction inverter”. 2018 IEEE Applied Power Electronics Conference and Exposition (APEC). 2018, pp. 1772– 1777.

[2] Advanced Circuits. PCB Design Speciﬁcations. URL: https://www.4pcb.com/pcb-design- specifications/.

[3] Advanced Circuits. PCB Laminate Material - Properties Guide. URL: https://www.4pcb.com/ AC-AdvanedTechnologyMaterialsMatrix.pdf.

[4] Allocco, J. M. “Laminated bus bars for power system interconnects”. Applied Power Electronics Conference. Vol. 2. 1997, 585–589 vol.2.

[5] Ansys. Q3D Extractor. Version 2015.2.0. [6] Anwar, M. et al. “Development of a power dense and environmentally robust traction power inverter for the second-generatio chevrolet VOLT extended-range EV”. 2015 IEEE Energy Conversion Congress and Exposition (ECCE). 2015, pp. 6006–6013.

[7] Avino-Salvado, Oriol et al. “Evauluation of printed-circuit boards materials for high temperature operation”. International Conference and Exhibition on High Temperature Electronics Network. 2017.

[8] Azar, K. and Graebner, J. E. “Experimental determination of thermal conductivity of printed wiring boards”. Twelfth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings. 1996, pp. 169–182.

[9] Beukes, H. J. et al. “Busbar design considerations for high power IGBT converters”. IEEE Power Electronics Specialists Conference. Vol. 2. 1997, pp. 847–853.

[10] Buschendorf, M. et al. “Comprehensive design of DC busbars for medium voltage applications”. 2013 IEEE Energy Conversion Congress and Exposition. 2013, pp. 1880–1885.

[11] Callegaro, A. D. et al. “Bus Bar Design for High-Power Inverters”. IEEE Transactions on Power Electronics 33.3 (2018), pp. 2354–2367.

[12] Caponet, M. C. et al. “Low stray inductance bus bar design and construction for good EMC performance in power electronic circuits”. IEEE Transactions on Power Electronics 17.2 (2002), pp. 225–231.

[13] Chen, C. et al. “Modeling and optimization of high power inverter three-layer laminated busbar”. IEEE Energy Conversion Congress and Exposition (ECCE). 2012, pp. 1380–1385.

[14] Chen, Z. et al. “A frequency-domain study on the effect of DC-link decoupling capacitors”. 2013 IEEE Energy Conversion Congress and Exposition. 2013, pp. 1886–1893.

70 [15] Chiampi, M. et al. “FEM analysis and modelling of busbar systems under AC conditions”. 1991 International Conference on Computation in Electromagnetics. 1991, pp. 252–255.

[16] Dettmer, E. S. et al. “Steady-state thermal conductivity measurements of AlN and SiC substrate materials”. IEEE Transactions on Components, Hybrids, and Manufacturing Technology 12.4 (1989), pp. 543–547.

[17] Gant, L. et al. “System Level Comparison of Si IGBTs and SiC MOSFETs”. PCIM Europe 2017; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. 2017, pp. 1–8.

[18] Generic Standard on Printed Board Design. Northbrook, IL: IPC, 2003.

[19] Geng, Chengfei et al. “Partial Stray Inductance Modeling and Measuring of Asymmetrical Parallel Branches on the Bus-Bar of Electric Vehicles”. Energies 10.10 (2017).

[20] Guichon, J. et al. “Busbar Design: How to Spare Nanohenries ?” IEEE Industry Applications Con- ference. Vol. 4. 2006, pp. 1865–1869.

[21] Guru, Bhag S. and Hiziroglu, Huseyin R. Electromagnetic Field Theory Fundamentals. Boston: PWS Publishing Company, 1997.

[22] Henry, J. et al. “Modeling and simulation of the 2016 Chevy Volt in dual PMSM EV mode”. 2017 IEEE International Conference on Smart Energy Grid Engineering (SEGE). 2017, pp. 56–61.

[23] Keysight Technologies. Keysight Technologies Impedance Measurement Handbook. 2016.

[24] Keysight Technologies. Keysight Technologies E4990A Impedance Analyzer. 2018.

[25] Kim, H. et al. “Impact of 1.2kV SiC-MOSFET EV traction inverter on urban driving”. 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2016, pp. 78–83.

[26] Kizilyalli, I. C. et al. “Current and future directions in power electronic devices and circuits based on wide band-gap semiconductors”. 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2017, pp. 417–417.

[27] Lemmon, A. and Graves, R. “Parasitic extraction procedure for silicon carbide power modules”. 2015 IEEE International Workshop on Integrated Power Packaging (IWIPP). 2015, pp. 91–94.

[28] Lemmon, A. N. and Graves, R. C. “Comprehensive Characterization of 10-kV Silicon Carbide Half-Bridge Modules”. IEEE Journal of Emerging and Selected Topics in Power Electronics 4.4 (2016), pp. 1462–1473.

[29] Lemmon, A. N. et al. “Methodology for Characterization of Common-Mode Conducted Electro- magnetic Emissions in Wide-Bandgap Converters for Ungrounded Shipboard Applications”. IEEE Journal of Emerging and Selected Topics in Power Electronics 6.1 (2018), pp. 300–314.

[30] LORD Corporation. CoolTherm MG-122 Thermally Conductive Gel.

71 [31] Lundqvist, B. et al. “Thermal conductivity of isotopically enriched silicon carbide”. 19th Inter- national Workshop on Thermal Investigations of ICs and Systems (THERMINIC). 2013, pp. 58– 61.

[32] Olejniczak, K. et al. “A compact 110 kVA, 140C ambient, 105C liquid cooled, all-SiC inverter for electric vehicle traction drives”. 2017 IEEE Applied Power Electronics Conference and Exposition (APEC). 2017, pp. 735–742.

[33] Paul, Clayton R. “Loop Inductance vs. Partial Inductance”. Inductance:Loop and Partial. Wiley- IEEE Press, 2010, pp. 247–306.

[34] Rahman, D. et al. “Design methodology for a planarized high power density EV/HEV traction drive using SiC power modules”. 2016 IEEE Energy Conversion Congress and Exposition (ECCE). 2016, pp. 1–7.

[35] Ross, Edward B. “The Self and Mutual Inductance of Linear Conductors” (1908).

[36] Skibinski, G. L. and Divan, D. M. “Design methodology and modeling of low inductance planar bus structures”. 1993 Fifth European Conference on Power Electronics and Applications. 1993, 98–105 vol.3.

[37] Tarzwell, Robert and Bahl, Ken. High voltage printed circuit design and manufacturing notebook. Sierra Proto Express, 2004.

[38] Teulings, W. et al. “MOSFET switching behaviour under inﬂuence of PCB stray inductance”. Industry Applications Conference. Vol. 3. 1996, 1449–1453 vol.3.

[39] Wang, Jianing et al. “Effect of key physical structures on the laminated bus bar inductance”. 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia). 2016, pp. 3689–3694.

[40] Wheeler, P.“Technology for the more and all electric aircraft of the future”. 2016 IEEE International Conference on Automatica (ICA-ACCA). 2016, pp. 1–5.

[41] Wijenayake, A. H. et al. “Design of a 250 kW, 1200 V SiC MOSFET-based three-phase inverter by considering a subsystem level design optimization approach”. 2017 IEEE Energy Conversion Congress and Exposition (ECCE). 2017, pp. 939–946.

[42] Winslow, A M. “MAGNETIC FIELD CALCULATIONS IN AN IRREGULAR TRIANGLE MESH” (1965).

[43] Wolfspeed. 1.2-kV, 50-A, Silicon Carbide, 45-mm, Six-Pack (Three-Phase) Module. URL: https: //www.wolfspeed.com/ccs050m12cm2.

[44] Xiao, Y. et al. “Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics”. Applied Power Electronics Conference and Exposition, 2004. APEC ’04. Nineteenth Annual IEEE. Vol. 1. 2004, 516–521 Vol.1.

72 [45] Xu, Yang. “Development of Advanced SiC Power Modules”. PhD thesis. North Carolina State University, 2017.

[46] Zhang, N. et al. “Develop Parasitic Inductance Model for the Planar Busbar of an IGBT H Bridge in a Power Inverter”. IEEE Transactions on Power Electronics 30.12 (2015), pp. 6924–6933.

73 APPENDICES

74 DPT Simulation Schematic for a 135 kW EV Inverter

75 DPT Simulation Schematic for a 125 kVA AHF Inverter

76 Heavy Duty Interconnect Designs

Figure 3 Heavy Duty Interconnect for the 135 kW SiC EV Inverter

Figure 4 Heavy Duty Interconnect Design A for a 125 kVA SiC Inverter Local Busbar

77 Figure 5 Heavy Duty Interconnect Design B for a 125 kVA SiC Inverter Local Busbar

Figure 6 Heavy Duty Interconnect Design C for a 125 kVA SiC Inverter Local Busbar