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USE of FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY in FUTURE: SPACE AVIONICS Rosc~Ec

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USE of FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY in FUTURE: SPACE AVIONICS Rosc~Ec Source of Acquisition NASA Johnson Space Center USE OF FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY IN FUTURE: SPACE AVIONICS Rosc~eC. Fe;~gzsoiz,Robert T~te,LTfztted S'ace Alliazce, LLC Houston, Texas To investigate the flexibility of this Abstract technology, the core of the Central Processing Unit and InputIOutput Processor of the Space Shuttle Fulfilling NASA's new vision for space AP 101S Computer were prototyped in Verilog exploration requires the development of sustainable, HDL and synthesized into an Altera Stratix FPGA. flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware 1. Introduction boards with fixed processor and/or Digital Signal NASA's Constellation is the collection of Processing (DSP) components interconnected via a systems that work together to support the new standardized bus system. This is foliowed by the vision for the exploration of the Moon, Mars, and purchase and/or development of software. the outer solar system. These systems include Th-iradigm has several disadvantages fF-- launch veh3les,i~l~icles,crew the development of systems to support NASA's habitats, robotic systems and ground systems. They new vision. Building a system to be fault tolerant are to be implemented in a long-term development increases the complexity and decreases the methodology. The goal of this strategy is "to performance of included software. Standard bus develop new capabilities in a manner that is design and conventional implementation produces pragmatic - so that new capabilities can be natural bottlenecks. Configuring hardware developed and used to advance exploration in the components in systems containing common near term - while also being flexible, in order to processors and DSPs is difficult initially and incorporate new technologies and respond with expensive or impossible to change later. agility to scientific discoveries.. NASA's acquisition strategy encourages the use of open- The existence of Hardware Description systems architectures that facilitate upgrades and Languages (HDLs), the recent increase in augmentation while enabling interoperability performance, density and radiation tolerance of among systems6'[1]. Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the These systems will require advanced and high technology for reprogrammable Systems on a Chip performance data processing elements due to the (SOC). This technology supports a paradigm better distance of mission and the need for more advanced suited for NASA's vision. Hardware and software and autonomous operations. Furthermore, these production are melded for more effective systems must be highly reliable and evolvable. For development; they can both evolve together over data processing, the traditional development time. paradigm of using hardware with fixed processing elements followed by software development is Designers incorporating this technology into acceptable, but provides less flexibility in support future avionics can benefit from its flexibility. of NASA's development strategy. The primary Systems can be designed with improved fault culprit is the use of fixed processing elements and isolation and tolerance using hardware instead of configurations that are more difficult to change and software. Also, these designs can be protected from evolve after they have been established. The obsolescence problems where maintenance is existence of Hardware Description Languages compromised via component and vendor (HDLs), the recent increase in performance, density availability. and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual property (IP) Cores provides the technology for reprogrammable vendor selections and purchases drive vendor Systems on a Chip (SOC). This technology selection and purchases. A long-term marriage provides for more flexible and evolvable designs. between these fixed processing elements and s~ftx~ireresults frem the develepme~teffert, which This paper discusses the advantages of can mean that the longevity of a system can come to incorporzting SOC technology into future space depend on these ve~dorsfor both iipgades zfid avionics. It also suggests some approaches to long-term support. There is no guarzntee that fume simplifying the software of systems by removing versions of the fixed processing elements will be complexity from applications, and moving Real backwards compatible or that they will continue to Time Operating Systems from a single processor to be supported. Using high-level languages for a collection of FPGAs. It includes a demonstration software can remedy these dependencies; however, of the flexibility of this technology via the this is not totally true for embedded systems. These implementation of the major components of the systems usually interface with low-level hardware Space Shuttle APlOlS Computer in Verilog HDL and for performance reasons contain software and its synthesis into an Altera Stratix FPGA. It written in the native language of the fixed processor closes with a discussion of how this implementation elements. could be incorporated into the avionics of a future launch vehicie reusing components of the existing The use offnese fixed processing elements is Space Shuttle Transportation System. usually accompanied by other components to -- -su~o~~ter~ome~~i~-usiagastand system. This topology is a centralized architecture 2. Traditional Development where a processing element communicates with Paradigms1 Platforms And NASA's peripherals and memory over a memory bus and a New Vision shared I/O bus. However, the drawback to this architecture is that the shared bus concept results in The traditional development process for bottleneck problems [2]. This can be a hindrance embedded data processing systems begins with the for data processing systems that need to process purchase or fabrication of hardware boards with high volumes of data. fixed processor and/or Digital Signal Processing (DSP) components interconnected via a A standardized bus system requires standardized bus system. This is followed by the components to support interconnectivity in fixed purchase and/or development of software. processing elements. This results in a centralized Development of the entire system proceeds in a architecture where a processing element stepwise fashion with the initially established communicates with peripherals and memory over a hardware platform later constraining the software memory bus and a shared I/O bus. This traditional development effort. The inflexibility of the fixed shared bus architecture can result in bottleneck hardware components along with the inherent problems [2], which is a hindrance for data bottlenecks of standardized bus systems often processing systems that need to process high constrains on the adaptability and performance of volumes of data. Such systems can end up with the data processing system. hardware-dependent software to overcome these bottlenecks NASA will need to develop flexible and sustainable systems to implement its space A standard architecture for software in exploration vision. This effort must provide very embedded systems consists of application software reliable systems that are evolvable for long-term layered on top of a real time operating system. The development and maintenance. These systems must primary job of the real time operating system is to be highly automated and self-sustaining to support interface with the hardware and provide an missions beyond low Earth orbit. environment where multiple applicztions can execute on a processor as if each were the sole The traditional approach to embedded system owner of the processor. This architecture also helps development can be inefficient in a long-term protect the applications from each others' faults.. development environment. Early decisions on fixed These systems must be designed carefully to processing elements (Processors and/or DSPs) drive manage against problems such as process starvation and Field Programmable Arrays (FPGAs). ASICs in a single processor. have traditionally been expensive to implement, so the rise in the density and performance of The development effort of the recently F?GAi 2nd thgir !ow cost are mking them the cancelled Space Shuttle Cockpit Avionics Upgrade favorite option [3]. This paper will focus on the Project provides real world examples of the -7- n- n An ;r\n shortcoming of traditional stepwise development of ~aeof FPGAs as the target lo5i \, U~VICICIS. Hardware Description Lmguages are processing systems. The goal of this project was to increase the situational awareness of the crew via specialized programming languages used to model and design digital hardware. Large increased on-board intelligence and automation, similar to what will be needed for NASA's new companies use them to design complex digital systems such as computer central processing vision. The core-processing element for the system units, computer peripherals and cell phones. An was the PowerPC 7455 processor. This was the HDL allows the engineer to model hardware best available processor in its class for speed and functionality as a software program. The model radiation tolerance, and the architecture of the can then be run on a computer to see if the design single board computer was based on this family of processors. However, while the PowerPC 7455 will work as intended. Problems can be corrected in the model, and the corrections verified in cache memory
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