Video Encoder with Six 10-Bit DACs, 54 MHz a Oversampling and Progressive Scan Inputs ADV7192
FEATURES APPLICATIONS Six High-Quality 10-Bit Video DACs DVD Playback Systems 10-Bit Internal Digital Video Processing PC Video/Multimedia Playback Systems Multistandard Video Input Progressive Scan Playback Systems Multistandard Video Output 4 Oversampling with Internal 54 MHz PLL GENERAL DESCRIPTION Programmable Video Control Includes: The ADV7192 is part of the new generation of video encoders Digital Noise Reduction from Analog Devices. The device builds on the performance of Gamma Correction previous video encoders and provides new features like interfac- Black Burst ing progressive scan devices, Digital Noise Reduction, Gamma LUMA Delay Correction, 4× Oversampling and 54 MHz operation, Average CHROMA Delay Brightness Detection, Black Burst Signal Generation, Chroma Multiple Luma and Chroma Filters Delay, an additional Chroma Filter, and other features. Luma SSAF™ (Super Subalias Filter) Average Brightness Detection The ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N, Field Counter PAL M, PAL-B/D/G/H/I and PAL-60 standards. Input standards Macrovision Rev. 7.1 supported include ITU-R.BT656 4:2:2 YCrCb in 8-bit or 16-bit × CGMS (Copy Generation Management System) format and 3 10-Bit YCrCb progressive scan format. WSS (Wide Screen Signaling) The ADV7192 can output Composite Video (CVBS), S-Video Closed Captioning Support. (Y/C), Component YUV or RGB and analog progressive scan in Teletext Insertion Port (PAL-WST) YPrPb format. The analog component output is also compatible 2-Wire Serial MPU Interface (I2C®-Compatible with Betacam, MII, and SMPTE/EBU N10 levels, SMPTE and Fast I2C) 170 M NTSC, and ITU–R.BT 470 PAL. 2 I C Interface Please see Detailed Description of Features for more informa- Supply Voltage 5 V and 3.3 V Operation tion about the ADV7192. 80-Lead LQFP Package
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VIDEO VIDEO VIDEO DIGITAL ANALOG INPUT SIGNAL OUTPUT INPUT OUTPUT PROCESSING PROCESSING PROCESSING
PLL 27MHz AND CLOCK 54MHz
CHROMA 10-BIT DEMUX LPF DAC COLOR CONTROL ITU–R.BT 2 AND DNR 10-BIT 656/601 OVERSAMPLING DAC YCrCb- GAMMA COMPOSITE VIDEO 8-BIT YCrCb TO- CORRECTION SSAF 10-BIT Y [S-VIDEO] TV SCREEN IN 4:2:2 FORMAT LPF DAC C [S-VIDEO] OR YUV OR MATRIX 10-BIT RGB PROGRESSIVE DAC YUV SCAN DISPLAY YPrPb VBI 4 10-BIT LUMA OVERSAMPLING DAC TELETEXT LPF CLOSED CAPTION 10-BIT CGMS/WSS DAC
I2C INTERFACE ADV7192
SSAF is a trademark of Analog Devices Inc.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). I2C is a registered trademark of Philips Corporation. Throughout the document YUV refers to digital or analog component video. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADV7192
CONTENTS MPU PORT DESCRIPTION ...... 28 FEATURES ...... 1 REGISTER ACCESSES ...... 29 APPLICATIONS ...... 1 REGISTER PROGRAMMING ...... 29 GENERAL DESCRIPTION ...... 1 MODE REGISTERS 0–9 ...... 30–35 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM ...... 1 TIMING REGISTERS 0–1 ...... 36 SPECIFICATIONS SUBCARRIER FREQUENCY AND Static Performance 5 V ...... 3 PHASE REGISTERS ...... 37 Static Performance 3.3 V ...... 4 CLOSED CAPTIONING REGISTERS ...... 37 Dynamic Specifications 5 V ...... 5 NTSC PEDESTAL/PAL TELETEXT CONTROL Dynamic Specifications 3.3 V ...... 5 REGISTERS ...... 37 Timing Characteristics 5 V ...... 6 TELETEXT REQUEST CONTROL REGISTER ...... 38 Timing Characteristics 3.3 V ...... 7 CGMS_WSS REGISTERS ...... 38 ABSOLUTE MAXIMUM RATINGS ...... 9 CONTRAST CONTROL REGISTER ...... 39 PIN CONFIGURATION ...... 9 COLOR CONTROL REGISTERS ...... 39 ORDERING GUIDE ...... 9 CC1 AND CC2 BIT DESCRIPTIONS ...... 39 PACKAGE THERMAL PERFORMANCE ...... 9 HUE ADJUST CONTROL REGISTER (HCR) ...... 40 PIN FUNCTION DESCRIPTIONS ...... 10 HCR BIT DESCRIPTION ...... 40 DETAILED DESCRIPTION OF FEATURES ...... 11 BRIGHTNESS CONTROL REGISTER (BCR) ...... 40 GENERAL DESCRIPTION ...... 11 BCR BIT DESCRIPTION ...... 40 DATA PATH DESCRIPTION ...... 12 SHARPNESS RESPONSE REGISTER (PR) ...... 41 INTERNAL FILTER RESPONSE ...... 13 PR BIT DESCRIPTION ...... 41 FEATURES: FUNCTIONAL DESCRIPTION ...... 17 DNR REGISTERS ...... 41 BLACK BURST OUTPUT ...... 17 DNR BIT DESCRIPTIONS ...... 41 BRIGHTNESS DETECT ...... 17 GAMMA CORRECTION REGISTERS ...... 43 CHROMA/LUMA DELAY ...... 17 BRIGHTNESS DETECT REGISTER ...... 44 CLAMP OUTPUT ...... 17 OUTPUT CLOCK REGISTER ...... 44 CSO, HSO, AND VSO OUTPUTS ...... 17 OCR BIT DESCRIPTIONS ...... 44 COLOR BAR GENERATION ...... 17 APPENDIX 1 Board Design and Layout Considerations ...... 45 COLOR BURST SIGNAL CONTROL ...... 17 APPENDIX 2 COLOR CONTROLS ...... 17 Closed Captioning ...... 47 CHROMINANCE CONTROL ...... 17 APPENDIX 3 UNDERSHOOT LIMITER ...... 18 Copy Generation Management System (CGMS) ...... 48 DIGITAL NOISE REDUCTION ...... 18 APPENDIX 4 DOUBLE BUFFERING ...... 18 Wide Screen Signaling ...... 49 GAMMA CORRECTION CONTROL ...... 18 APPENDIX 5 NTSC PEDESTAL CONTROL ...... 18 Teletext Insertion ...... 50 POWER-ON RESET ...... 18 APPENDIX 6 PROGRESSIVE SCAN INPUT ...... 18 Optional Output Filter ...... 51 REAL-TIME CONTROL, SUBCARRIER RESET, AND APPENDIX 7 TIMING RESET ...... 19 DAC Buffering ...... 52 SCH PHASE MODE ...... 19 APPENDIX 8 Recommended Register Values ...... 53 SLEEP MODE ...... 19 APPENDIX 9 SQUARE PIXEL MODE ...... 19 NTSC Waveforms (With Pedestal) ...... 57 VERTICAL BLANKING DATA INSERTION NTSC Waveforms (Without Pedestal) ...... 58 AND BLANK INPUT ...... 19 PAL Waveforms ...... 59 YUV LEVELS ...... 20 Video Measurement Plots ...... 60 16-BIT INTERFACE ...... 20 UV Waveforms ...... 64 4× OVERSAMPLING AND INTERNAL PLL ...... 20 Output Waveforms ...... 65 VIDEO TIMING DESCRIPTION ...... 20 APPENDIX 10 RESET SEQUENCE ...... 20 Vector Plots ...... 68 OUTLINE DIMENSIONS ...... 69
–2– REV. A ADV7192 SPECIFICATIONS 2 1(VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX 5 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity3 1.0 LSB Differential Nonlinearity3 1.0 LSB Guaranteed Monotonic DIGITAL INPUTS Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Input Current, IIN 0 ±1 µAVIN = 0.4 V or 2.4 V Input Capacitance, CIN 610pF Input Leakage Current4 1 µA Input Leakage Current5 200 µA DIGITAL OUTPUTS Output High Voltage, VOH 2.4 V ISOURCE = 400 µA Output Low Voltage, VOL 0.8 0.4 V ISINK = 3.2 mA Three-State Leakage Current6 10 µA Three-State Leakage Current7 200 µA Three-State Output Capacitance 6 10 pF ANALOG OUTPUTS Output Current (Max) 4.125 4.33 4.625 mA RL = 300 Ω Output Current (Min) 2.16 mA RL = 600 Ω RSET1, RSET2 = 2400 Ω DAC-to-DAC Matching3 0.4 2.5 % Output Compliance, VOC 0 1.4 V Output Impedance, ROUT 100 kΩ Output Capacitance, COUT 6pFIOUT = 0 mA VOLTAGE REFERENCE 8 Reference Range, VREF 1.112 1.235 1.359 V POWER REQUIREMENTS VAA 4.75 5.0 5.25 V Normal Power Mode 9 IDAC (Max) 29 35 mA 10, 11 ICCT (2× Oversampling) 80 120 mA 10, 11 ICCT (4× Oversampling) 120 170 mA IPLL 610mA Sleep Mode IDAC 0.01 µA ICCT 85 µA NOTES 1All measurements are made in 4× Oversampling Mode unless otherwise specified. 2 Temperature range TMIN to TMAX: 0°C to 70°C. 3Guaranteed by characterization. 4For all inputs but PAL_NTSC and ALSB. 5For PAL_NTSC and ALSB inputs. 6For all outputs but VSO/TTX/CLAMP. 7For VSO/TTX/CLAMP output. 8Measurement made in 2× Oversampling Mode. 9 IDAC is the total current required to supply all DACs including the VREF Circuitry. 10All six DACs ON. 11 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice.
REV. A –3– ADV7192–SPECIFICATIONS 2 1 (VAA = 3.3 V, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity 1.0 LSB Differential Nonlinearity 1.0 LSB Guaranteed Monotonic DIGITAL INPUTS Input High Voltage, VINH 2V Input Low Voltage, VINL 0.8 V Input Leakage Current3 1 µA Input Leakage Current4 200 µA Input Current, IIN ±1 µAVIN = 0.4 V or 2.4 V Input Capacitance, CIN 610pF DIGITAL OUTPUTS Output High Voltage, VOH 2.4 V ISOURCE = 400 µA Output Low Voltage, VOL 0.4 V ISINK = 3.2 mA Three-State Leakage Current5 10 µA Three-State Leakage Current6 200 µA Three-State Output Capacitance 6 10 pF ANALOG OUTPUTS Output Current (Max) 4.125 4.33 4.625 mA RL = 300 Ω Output Current (Min) 2.16 mA RL = 600 Ω, RSET1,2 = 2400 Ω DAC-to-DAC Matching 0.4 2.5 % Output Compliance, VOC 1.4 V Output Impedance, ROUT 100 kΩ Output Capacitance, COUT 6pFIOUT = 0 mA VOLTAGE REFERENCE 7 Reference Range, VREF 1.235 V IVREFOUT = 20 µA POWER REQUIREMENTS VAA 3.15 3.3 3.6 V Normal Power Mode 8 IDAC (Max) 29 mA 9, 10 ICCT (2× Oversampling) 42 54 mA 9, 10 ICCT (4× Oversampling) 68 86 mA IPLL 6mA Sleep Mode 10 IDAC 0.01 µA ICCT 85 µA NOTES 1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 × Oversampling Mode, power require- ment for the ADV7192 is typically 3.0 V. 2 Temperature range TMIN to TMAX: 0°C to 70°C. 3For all inputs but PAL_NTSC and ALSB. 4For PAL_NTSC and ALSB inputs. 5For all outputs but VSO/TTX/CLAMP. 6For VSO/TTX/CLAMP output. 7Measurement made in 2× Oversampling Mode. 8 IDAC is the total current required to supply all DACs including the VREF Circuitry. 9All six DACs ON. 10 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice.
–4– REV. A ADV7192 (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All 1 2 5 V DYNAMIC–SPECIFICATIONS specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions Hue Accuracy 0.5 Degrees Color Saturation Accuracy 0.7 % Chroma Nonlinear Gain 0.7 0.9 ±% Referenced to 40 IRE Chroma Nonlinear Phase 0.5 ±Degrees Chroma/Luma Intermod 0.1 ±% Chroma/Luma Gain Ineq 1.7 ±% Chroma/Luma Delay Ineq 2.2 ns Luminance Nonlinearity 0.6 0.7 ±% Chroma AM Noise 82 dB Chroma PM Noise 72 dB Differential Gain3 0.1 (0.4) 0.3 (0.5) % Differential Phase3 0.4 (0.15) 0.5 (0.3) Degrees SNR (Pedestal)3 78.5 (78) dB rms RMS 78 (78) dB p-p Peak Periodic SNR (Ramp)3 61.7 (61.7) dB rms RMS 62 (63) dB p-p Peak Periodic NOTES 1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range TMIN to TMAX: 0°C to 70°C. 3Values in parentheses apply to 2× Oversampling Mode. Specifications subject to change without notice.
(VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All 1 2 3.3 V DYNAMIC–SPECIFICATIONS specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions Hue Accuracy 0.5 Degrees Color Saturation Accuracy 0.8 % Luminance Nonlinearity 0.6 ±% Chroma AM Noise 83 dB Chroma PM Noise 71 dB Chroma Nonlinear Gain 0.7 ±% Referenced to 40 IRE Chroma Nonlinear Phase 0.5 ±Degrees Chroma/Luma Intermod 0.1 ±% Differential Gain3 0.2 (0.5) % Differential Phase3 0.5 (0.2) Degrees SNR (Pedestal)3 78.5 (78) dB rms RMS 78 (78) dB p-p Peak Periodic SNR (Ramp)3 62.3 (62) dB rms RMS 61 (62.5) dB p-p Peak Periodic NOTES 1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range TMIN to TMAX: 0°C to 70°C. 3Values in parentheses apply to 2× Oversampling Mode. Specifications subject to change without notice.
REV. A –5– ADV7192 (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 V unless otherwise noted. All 1 5 V TIMING CHARACTERISTICS specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions MPU PORT2 SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t1 0.6 µs SCLOCK Low Pulsewidth, t2 1.3 µs Hold Time (Start Condition), t3 0.6 µs After This Period the First Clock Is Generated Setup Time (Start Condition), t4 0.6 µs Relevant for Repeated Start Condition Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 µs ANALOG OUTPUTS2 Analog Output Delay 8 ns DAC Analog Output Skew 0.1 ns CLOCK CONTROL AND PIXEL PORT3 fCLOCK 27 MHz Clock High Time, t9 82 ns Clock Low Time, t10 83 ns Data Setup Time, t11 6 2.5 ns Data Hold Time, t12 5 2.0 ns Control Setup Time, t11 6ns Control Hold Time, t12 4ns Digital Output Access Time, t13 13 ns Digital Output Hold Time, t14 12 ns Pipeline Delay, t15 (2× Oversampling) 57 Clock Cycles Pipeline Delay, t15 (4× Oversampling) 67 Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 11 ns Data Setup Time, t17 3ns Data Hold Time, t18 6ns RESET CONTROL RESET Low Time 3 20 ns PLL2 PLL Output Frequency 54 MHz NOTES 1 Temperature range TMIN to TMAX: 0°C to 70°C. 2Guaranteed by characterization. 3Pixel Port consists of: Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4Teletext Port consists of: Digital Output: TTXREQ Data: TTX Specifications subject to change without notice.
–6– REV. A ADV7192
(VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All 1 2 3.3 V TIMING CHARACTERISTICS specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions MPU PORT SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t1 0.6 µs SCLOCK Low Pulsewidth, t2 1.3 µs Hold Time (Start Condition), t3 0.6 µs After This Period the First Clock Is Generated Setup Time (Start Condition), t4 0.6 µs Relevant for Repeated Start Condition Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 2 µs ANALOG OUTPUTS Analog Output Delay 8 ns DAC Analog Output Skew 0.1 ns CLOCK CONTROL AND PIXEL PORT 3 fCLOCK 27 MHz Clock High Time, t9 82 ns Clock Low Time, t10 83 ns Data Setup Time, t11 64 ns Data Hold Time, t12 4 2.0 ns Control Setup Time, t11 2, 5 ns Control Hold Time, t12 3ns Digital Output Access Time, t13 13 ns Digital Output Hold Time, t14 12 ns Pipeline Delay, t15 (2× Oversampling) 37 Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 11 ns Data Setup Time, t17 3ns Data Hold Time, t18 6ns RESET CONTROL RESET Low Time 3 20 ns PLL PLL Output Frequency 54 MHz NOTES 1 Temperature range TMIN to TMAX: 0°C to 70°C. 2Guaranteed by characterization. 3Pixel Port consists of: Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4Teletext Port consists of: Digital Output: TTXREQ Data: TTX Specifications subject to change without notice.
REV. A –7– ADV7192
t5 t t3 3 SDA
t6 t1
SCL
t2
t7 t4 t8 Figure 1. MPU Port Timing Diagram
CLOCK
t9 t10 t12 HSYNC, CONTROL I/PS VSYNC, BLANK
PIXEL INPUT DATA Cb Y Cr Y Cb Y t t HSYNC, 11 13 VSYNC, CONTROL O/PS BLANK, CSO_HSO, VSO, CLAMP t14 Figure 2. Pixel and Control Data Timing Diagram
TTXREQ
t16 CLOCK
t17 t18
TTX
4 CLOCK 4 CLOCK 4 CLOCK 3 CLOCK 4 CLOCK CYCLES CYCLES CYCLES CYCLES CYCLES
Figure 3. Teletext Timing Diagram
CLOCK
t12 t9 t10 Y0–Y9 INCLUDING Y0 Y1 Y2 Y3 Y4 Y5 SYNC PROGRESSIVE INFORMATION SCAN INPUT Cb0–Cb9 Cb0 Cb1 Cb2 Cb3 Cb4 Cb5
Cr0–Cr9 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5
t11
Figure 4. Progressive Scan Input Timing
–8– REV. A ADV7192
ABSOLUTE MAXIMUM RATINGS1 PACKAGE THERMAL PERFORMANCE VAA to GND ...... 7 V The 80-lead package is used for this device. The junction-to- Voltage on any Digital Input Pin . . GND – 0.5 V to VAA + 0.5 V ambient (θJA) thermal resistance in still air on a four-layer PCB Storage Temperature (TS) ...... –65°C to +150°C is 24.7°C. Junction Temperature (T ) ...... 150°C J To reduce power consumption when using this part the user Body Temperature (Soldering, 10 secs) ...... 220°C 2 can run the part on a 3.3 V supply, turn off any unused DACs. Analog Outputs to GND ...... GND – 0.5 V to VAA NOTES The user must at all times stay below the maximum junction 1Stresses above those listed under Absolute Maximum Ratings may cause perma- temperature of 110°C. The following equation shows how to nent damage to the device. This is a stress rating only; functional operation of the calculate this junction temperature: device at these or any other conditions above those listed in the operational sections × × θ ° of this specification is not implied. Exposure to absolute maximum rating condi- Junction Temperature = (VAA (IDAC + ICCT)) JA + 70 C TAMB tions for extended periods may affect device reliability. IDAC = 10 mA + (sum of the average currents consumed by 2Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. each powered-on DAC) Average current consumed by each powered-on DAC =
(VREF × K )/RSET
VREF = 1.235 V K = 4.2146 PIN CONFIGURATION /TTX/CLAMP DD DD DGND V Cb[3] Cb[2] Cb[1] Cb[0] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] DGND V Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] VSO CSO_HSO 80 79 78 77 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC 1 60 PIN 1 RESET NC 2 IDENTIFIER 59 PAL_NTSC P0 3 58 RSET1 P1 4 57 VREF P2 5 56 COMP 1 P3 6 55 DAC A P4 7 54 DAC B P5 8 53 V ADV7192 AA P6 9 LQFP 52 AGND P7 10 TOP VIEW 51 DAC C Y[0]/P8 11 (Not to Scale) 50 DAC D Y[1]/P9 12 49 AGND Y[2]/P10 13 48 VAA Y[3]/P11 14 47 DAC E Y[4]/P12 15 46 DAC F Y[5]/P13 16 45 COMP 2 17 Y[6]/P14 44 RSET2 Y[7]/P15 18 43 DGND Y[8] 19 42 ALSB Y[9] 20 41 SCRESET/RTC/TR
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AA DD DD V V V SCL SDA
NC = NO CONNECT Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] AGND DGND DGND CLKIN VSYNC HSYNC BLANK TTXREQ CLKOUT
ORDERING GUIDE
Model Temperature Range Package Description Package Option ADV7192KST 0°C to 70°C 80-Lead Quad Flatpack ST-80
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although WARNING! the ADV7192 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE
REV. A –9– ADV7192
PIN FUNCTION DESCRIPTIONS
Pin Input/ No. Mnemonic Output Function 1, 2 NC No Connect. 3–10 P0–P7 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0 (Pin Number 3). 11–18 Y0/P8–Y7/P15 I 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (Bits 8–15). 1 × 10-Bit Progressive Scan Input for Ydata (Bits 0–7). 19, 20 Y8–Y9 1 × 10-Bit Progressive Scan Input Is Ydata (Bits 8 and 9).
21, 34, 68, 79 VDD P Digital Power Supply (3.3 V to 5 V). 22, 33, 43, 69, DGND G Digital Ground. 80 23 HSYNC I/O HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync Signals. 24 VSYNC I/O VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input (Slave Mode) and accept VSYNC as a Control Signal. 25 BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking and Data Insertion Blanking Input section. 26–31, 75–78 Cb4–Cb9, Cb0–Cb3 I 1 × 10-Bit Progressive Scan Input Port for Cb Data. 32 TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer. 35, 49, 52 AGND G Analog Ground. 36 CLKIN I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. 37 CLKOUT O Clock Output Pin.
38, 48, 53 VAA P Analog Power Supply (3.3 V to 5 V). 39 SCL I MPU Port Serial Interface Clock Input. 40 SDA I/O MPU Port Serial Data Input/Output. 41 SCRESET/ I Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier RTC/TR Reset input. 42 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.
44 RSET2 I A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes of the Video Signals from the DAC D, E, F. 45 COMP 2 O Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP2 to VAA. 46 DAC F O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. 47 DAC E O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. 50 DAC D O Composite/Y (Progressive Scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output. 51 DAC C O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. 54 DAC B O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. 55 DAC A O Composite/Y(Progressive Scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output.
56 COMP 1 O Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP1 to VAA.
57 VREF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external VREF cannot be used in 4× Oversampling Mode.
58 RSET1 I A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes of the Video Signals from the DAC A, B, C. 59 PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. 60 RESET I The input resets the on-chip timing generator and sets the ADV7192 into default mode. See Appendix 8 for Default Register settings. 61 CSO_HSO O Dual function CSO or HSO Output Sync Signal at TTL Level. 62 VSO/TTX/CLAMP I/O Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin. CLAMP TTL output signals can be used to drive external circuitry to enable clamping of all video signals. 63–67, 70–74 Cr0–Cr4, Cr5–Cr9 I 1 × 10-Bit Progressive Scan Input Port for Cr Data.
–10– REV. A ADV7192 ϫ DETAILED DESCRIPTION OF FEATURES to input video data in 3 10-bit YCrCb progressive scan format Clocking: to facilitate interfacing devices such as progressive scan systems. Single 27 MHz Clock Required to Run the Device Six DACs are available on the ADV7192, each of which is capable 4 Oversampling with Internal 54 MHz PLL of providing 4.33 mA of current. In addition to the composite Square Pixel Operation output signal there is the facility to output S-Video (Y/C Video), Advanced Power Management RGB Video and YUV Video. All YUV formats (SMPTE/EBU Programmable Video Control Features: N10, MII or Betacam) are supported. Digital Noise Reduction The on-board SSAF (Super Subalias Filter) with extended lumi- Black Burst Signal Generation nance frequency response and sharp stopband attenuation Pedestal Level enables studio quality video playback on modern TVs, giving Hue, Brightness, Contrast, and Saturation optimal horizontal line resolution. An additional sharpness Clamping Output Signal control feature allows high-frequency enhancement on the VBI (Vertical Blanking Interval) luminance signal. Subcarrier Frequency and Phase LUMA Delay DNR MODE CHROMA Delay DNR CONTROL GAIN Gamma Correction BLOCK SIZE CONTROL CORING GAIN DATA Luma And Chroma Filters BORDER AREA CORING GAIN BORDER BLOCK OFFSET Luma SSAF (Super Subalias Filter) NOISE SIGNAL PATH SUBTRACT SIGNAL IN THRESHOLD Average Brightness Detection RANGE FROM ORIGINAL SIGNAL Field Counter INPUT FILTER BLOCK Interlaced/Noninterlaced Operation FILTER OUTPUT Complete On-Chip Video Timing Generator Y DATA
PAL_NTSC VSO/CLAMP CSO_HSO SCL SDA ALSB Cr0–Cr9 Cb0–Cb9 Y0–Y9
HSYNC CGMS/WSS M I VSYNC VIDEO TIMING AND 10-BIT I2C MPU PORT U N DAC A BLANK GENERATOR CLOSED CAPTIONING DAC CONTROL YUV-TO-RGB L T MATRIX T E 10-BIT RESET DAC B AND I R DAC YUV LEVEL P P TTX TELETEXT BRIGHTNESS PROGRAMMABLE CONTROL L O 10-BIT INSERTION CONTROL DAC C TTXREQ LUMA FILTER BLOCK E L DAC BLOCK AND AND X A ADD SYNC SHARPNESS E T V AND I DAC REF 10 10 FILTER R O CONTROL RSET2 YCrCb- Y DNR Y INTERPOLATOR N R BLOCK COMP2 TO- 10 AND 10 T SATURATION E YUV U GAMMA U CONTROL R 10-BIT MATRIX 10 CORRECTION 10 PROGRAMMABLE MODULATOR DAC D AND DAC V V CHROMA AND P ADD BURST FILTER HUE CONTROL O 10 10 10 AND 10-BIT L DAC F INTERPOLATOR DAC P0 A T DEMUX 10-BIT O DAC E DAC P15 R REAL-TIME SIN/COS DAC ADV7192 CONTROL DDS CONTROL R CLKIN PLL CIRCUIT BLOCK SET1 BLOCK CLKOUT COMP1
SCRESET/RTC/TR Figure 5. Detailed Functional Block Diagram REV. A –11– ADV7192
Digital Noise Reduction allows improved picture quality in remov- The Output Video Frames are synchronized with the incoming ing low amplitude, high frequency noise. Figure 6 shows the DNR data Timing Reference Codes. Optionally, the Encoder accepts functionality in the two modes available. (and can generate) HSYNC, VSYNC, and FIELD timing signals. Programmable gamma correction is also available. The figure below These timing signals can be adjusted to change pulsewidth and shows the response of different gamma values to a ramp signal. position while the part is in master mode. HSO/CSO and VSO TTL outputs are also available and are timed 300 to the analog output video. GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES A separate teletext port enables the user to directly input teletext 250 data during the vertical blanking interval. SIGNAL OUTPUTS The ADV7192 also incorporates WSS and CGMS-A data control 200 0.3 generation. 0.5 The ADV7192 modes are set up over a 2-wire serial bidirectional 150 port (I2C-compatible) with two slave addresses, and the device is register-compatible with the ADV7172. 100 1.5 The ADV7192 is packaged in an 80-lead LQFP package. SIGNAL INPUT 1.8
GAMMA-CORRECTED AMPLITUDE 50 DATA PATH DESCRIPTION For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb 0 0 50 100 150 200 250 4:2:2 data is input via the CCIR-656/601-compatible Pixel Port LOCATION at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form Figure 7. Signal Input (Ramp) and Selectable Gamma three data paths. Y typically has a range of 16 to 235, Cr and Cb Output Curves typically have a range of 128Ϯ112; however, it is possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7192 The device is driven by a 27 MHz clock. Data can be output at supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with 27 MHz or 54 MHz (on-board PLL) when 4ϫ oversampling is and without Pedestal) and PAL60 standards. enabled. Also, the output filter requirements in 4ϫ oversampling and 2ϫ oversampling differ, as can be seen in Figure 8. Digital noise reduction can be applied to the Y signal. Pro- grammable gamma correction can also be applied to the Y
2 FILTER signal if required. 0dB REQUIREMENTS The Y data can be manipulated for contrast control and a setup
4 FILTER level can be added for brightness control. The Cr, Cb data can REQUIREMENTS be scaled to achieve color saturation control. All settings become effective at the start of the next field when double buffering is enabled. –30dB 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz The appropriate sync, blank, and burst levels are added to the YCrCb data. Macrovision antitaping, closed-captioning and × Figure 8. Output Filter Requirements in 4 Oversampling teletext levels are also added to Y and the resultant data is inter- Mode polated to 54 MHz (4ϫ Oversampling Mode). The interpolated data is filtered and scaled by three digital FIR filters. 2 ADV7192 The U and V signals are modulated by the appropriate Subcarrier 6 Sine/Cosine waveforms and a phase offset may be added onto I D N the color subcarrier during active video to allow hue adjustment. A T PIXEL BUS ENCODER C The resulting U and V signals are added together to make up MPEG2 E 27MHz CORE R 54MHz the Chrominance signal. The Luma (Y) signal can be delayed O P OUTPUT U O RATE by up to six clock cycles (at 27 MHz) and the Chroma signal T L P can be delayed by up to eight clock cycles (at 27 MHz). A U T T The Luma and Chroma signals are added together to make up I S 54MHz O the Composite Video Signal. All timing signals are controlled. PLL N The YCrCb data is also used to generate RGB data with appropri- ate sync and blank levels. The YUV levels are scaled to output Figure 9. PLL and 4× Oversampling Block Diagram the suitable SMPTE/EBU N10, MII, or Betacam levels. The ADV7192 also supports both PAL and NTSC square pixel Each DAC can be individually powered off if not required. A operation. In this case the encoder requires a 24.5454 MHz Clock complete description of DAC output configurations is given in for NTSC or 29.5 MHz Clock for PAL square pixel mode opera- the Mode Register 2 section. tion. All internal timing is generated on-chip. Video output levels are illustrated in Appendix 9. An advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes.
–12– REV. A ADV7192
When to used to interface progressive scan systems, the ADV7192 several different frequency responses including five low-pass allows to input YCrCb signals in Progressive Scan format responses, a CIF response, and a QCIF response, as can be seen in (3ϫ 10-bit) before these signals are routed to the interpolation the following figures. All filter plots show the 4ϫ Oversampling filters and the DACs. responses. INTERNAL FILTER RESPONSE In Extended Mode there is the option of 12 responses in the range The Y Filter supports several different frequency responses from –4 dB to +4 dB. The desired response can be chosen by the 2 including two low-pass responses, two notch responses, an user by programming the correct value via the I C. The variation Extended (SSAF) response with or without gain boost/attenuation, of frequency responses can be seen in the Tables I and II. For a CIF response, and a QCIF response. The UV filters support more detailed filter plots refer to Analog Devices’ Application Note AN-562.
Table I. Luminance Internal Filter Specifications (4 Oversampling)
Passband 3 dB Bandwidth2 Filter Type Filter Selection Ripple1 (dB) (MHz) MR04 MR03 MR02 Low-Pass (NTSC) 0 0 0 0.16 4.24 Low-Pass (PAL) 0 0 1 0.1 4.81 Notch (NTSC) 0 1 0 0.09 2.3/4.9/6.6 Notch (PAL) 0 1 1 0.1 3.1/5.6/6.4 Extended (SSAF) 1 0 0 0.04 6.45 CIF 1 0 1 0.127 3.02 QCIF 1 1 0 Monotonic 1.5 NOTES 1Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points. 23 dB bandwidth refers to the –3 dB cutoff frequency.
Table II. Chrominance Internal Filter Specifications (4 Oversampling)
Passband 3 dB Bandwidth2 Filter Type Filter Selection Ripple1 (dB) (MHz) MR07 MR06 MR05 1.3 MHz Low-Pass 0 0 0 0.09 1.395 0.65 MHz Low-Pass 0 0 1 Monotonic 0.65 1.0 MHz Low-Pass 0 1 0 Monotonic 1.0 2.0 MHz Low-Pass 0 1 1 0.048 2.2 3.0 MHz Low-Pass 1 1 1 Monotonic 3.2 CIF 1 0 1 Monotonic 0.65 QCIF 1 1 0 Monotonic 0.5 NOTES 1Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points. 23 dB bandwidth refers to the –3 dB cutoff frequency.
REV. A –13– ADV7192–Typical Performance Characteristics
0 0
–10 –10
–20 –20 dB dB – – –30 –30
–40 –40 MAGNITUDE MAGNITUDE
–50 –50
–60 –60
–70 –70 0 2 468 10 12 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 1. NTSC Low-Pass Luma Filter TPC 4. PAL Notch Luma Filter
0 0
–10 –10
–20 –20 dB dB – – –30 –30
–40 –40 MAGNITUDE MAGNITUDE –50 –50
–60 –60
–70 –70 0 2 468 10 12 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 2. PAL Low-Pass Luma Filter TPC 5. Extended Mode (SSAF) Luma Filter
0 4
–10 2
0 –20 dB dB – – –2 –30 –4 –40
MAGNITUDE –6 MAGNITUDE –50 –8
–60 –10
–70 –12 0 2 468 10 12 0 1 2 3 4 5 67 FREQUENCY – MHz FREQUENCY – MHz
TPC 3. NTSC Notch Luma Filter TPC 6. Extended SSAF Luma Filter and Programmable Gain/Attenuation Showing +4 dB/–12 dB Range
–14– REV. A ADV7192
1 0
0 –10
–1 –20 dB dB – – –30 –2
–40 MAGNITUDE MAGNITUDE –3 –50
–4 –60
–5 –70 0 1 2 3 4 5 67 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 7. Extended SSAF and Programmable Attenuation, TPC 10. Luma QCIF Filter Showing Range 0 dB/–4 dB
5 0
4 –10
3 –20 dB dB – – –30 2
–40 MAGNITUDE 1 MAGNITUDE –50
0 –60
–1 –70 0 1 2 3 4 5 67 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 8. Extended SSAF and Programmable Gain, Showing TPC 11. Chroma 0.65 MHz Low-Pass Filter Range 0 dB/+4 dB
0 0
–10 –10
–20 –20 dB dB – – –30 –30
–40 –40 MAGNITUDE MAGNITUDE
–50 –50
–60 –60
–70 –70 0 2 468 10 12 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 9. Luma CIF Filter TPC 12. Chroma 1.0 MHz Low-Pass Filter
REV. A –15– ADV7192
0 0
–10 –10
–20 –20 dB dB – – –30 –30
–40 –40 MAGNITUDE MAGNITUDE
–50 –50
–60 –60
–70 –70 0 2 468 10 12 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 13. Chroma 1.3 MHz Low-Pass Filter TPC 16. Chroma CIF Filter
0 0
–10 –10
–20 –20 dB dB – – –30 –30
–40 –40 MAGNITUDE MAGNITUDE –50 –50
–60 –60
–70 –70 0 2 468 10 12 0 2 468 10 12 FREQUENCY – MHz FREQUENCY – MHz
TPC 14. Chroma 2 MHz Low-Pass Filter TPC 17. Chroma QCIF Filter
0
–10
–20 dB – –30
–40 MAGNITUDE
–50
–60
–70 0 2 468 10 12 FREQUENCY – MHz
TPC 15. Chroma 3 MHz Low-Pass Filter
–16– REV. A ADV7192
FEATURES: FUNCTIONAL DESCRIPTION CSO, HSO, AND VSO OUTPUTS BLACK BURST OUTPUT The ADV7192 supports three output timing signals, CSO It is possible to output a black burst signal from two DACs. This (composite sync signal), HSO (Horizontal Sync Signal) and signal output is very useful for professional video equipment VSO (Vertical Sync Signal). These output TTL signals are aligned since it enables two video sources to be locked together. (Mode with the analog video outputs. See Figure 14 for an example Register 9.) of these waveforms. (Mode Register 7.)
EXAMPLE:- NTSC DIGITAL DATA ADV7192 5251234567891011–19 GENERATOR OUTPUT CVBS VIDEO BLACK BURST OUTPUT CSO CVBS DIGITAL DATA ADV7192 HSO GENERATOR VSO
Figure 10. Possible Application for the Black Burst Output Figure 14. CSO, HSO, VSO Timing Diagram Signal COLOR BAR GENERATION BRIGHTNESS DETECT The ADV7192 can be configured to generate 100/7.5/75/7.5 This feature is used to monitor the average brightness of the color bars for NTSC or 100/0/75/0 color bars for PAL. (Mode incoming Y video signal on a field by field basis. The information Register 4.) is read from the I2C and based on this information the color saturation, contrast and brightness controls can be adjusted (for COLOR BURST SIGNAL CONTROL example to compensate for very dark pictures). (Brightness Detect The burst information can be switched on and off the composite Register.) and chroma video output. (Mode Register 4.)
CHROMA/LUMA DELAY COLOR CONTROLS The luminance data can be delayed by maximum of six clock The ADV7192 allows the user to control the brightness, contrast, cycles. Additionally the Chroma can be delayed by a maximum hue and saturation of the color. The control registers may be of eight clock cycles (one clock cycle at 27 MHz). (Timing Reg- double-buffered, meaning that any modification to the registers ister 0 and Mode Register 9.) will be done outside the active video region and, therefore, changes made will not be visible during active video. Contrast Control Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 150%. (Contrast Control Register.) CHROMA DELAY LUMA DELAY Brightness Control The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the setup can vary from –7.5 IRE to +15 IRE. (Brightness Control Figure 11. Chroma Delay Figure 12. Luma Delay Register.) Color Saturation CLAMP OUTPUT Color adjustment is achieved by scaling the Cr and Cb input The ADV7192 has a programmable clamp TTL output signal. data by a factor programmed by the user. This factor allows the This clamp signal is programmable to the front and back porch. data to be scaled between 0% and 200%. (U Scale Register and The clamp signal can be varied by one to three clock cycles in a V Scale Register.) positive and negative direction from the default position. Hue Adjust Control (Mode Register 5, Mode Register 7.) The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the CLAMP O/P SIGNALS active video but leaving the color burst unmodified, i.e., only
CVBS the phase between the video and the colorburst is modified and OUTPUT PIN hence the hue is shifted. The ADV7192 provides a range of ± 22° in increments of 0.17578125°. (Hue Adjust Register.)
MR57 = 1 CLAMP CHROMINANCE CONTROL MR57 = 0 OUTPUT PIN The color information can be switched on and off the com- posite, chroma and color component video outputs. (Mode Figure 13. Clamp Output Timing Register 4.)
REV. A –17– ADV7192
UNDERSHOOT LIMITER POWER-ON RESET A limiter is placed after the digital filters. This prevents any After power-up, it is necessary to execute a RESET operation. A synchronization problems for TVs. The level of undershoot is reset occurs on the falling edge of a high-to-low transition on the programmable between –1.5 IRE, –6 IRE, –11 IRE when oper- RESET pin. This initializes the pixel port such that the data on ating in 4× Oversampling Mode. In 2× Oversampling Mode the the pixel inputs pins is ignored. See Appendix 8 for the register limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing settings after RESET is applied. Register 0.) PROGRESSIVE SCAN INPUT DIGITAL NOISE REDUCTION It is possible to input data to the ADV7192 in progressive scan DNR is applied to the Y data only. A filter block selects the format. For this purpose the input pins Y0/P8–Y7/P15, Y8–Y9, high frequency, low amplitude components of the incoming Cr0–Cr9 and Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data signal (DNR Input Select). The absolute value of the filter output and 10-bit Cr data. The data is clocked into the part at 27 MHz. is compared to a programmable threshold value (DNR Thresh- The data is then filtered and sinc corrected in an 2ϫ Interpo- old Control). There are two DNR modes available: DNR Mode lation filter and then output to three video DACs at 54 MHz and DNR Sharpness Mode. (to interface to a progressive scan monitor). In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable 0 amount (Coring Gain Control) of this noise signal will be sub- –10 tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output –20 is less than the programmed threshold, it is assumed to be noise, dB as before. Otherwise, if the level exceeds the threshold, now – –30 being identified as a valid signal, a fraction of the signal (Coring Gain Control) will be added to the original signal in order to boost –40 high frequency components and to sharpen the video image. AMPLITUDE –50 In MPEG systems it is common to process the video information in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16 pixels –60 for MPEG1 systems ('Block Size Control'). DNR can be applied to the resulting block transition areas that are known to contain –70 0305 10 15 20 25 noise. Generally the block transition area contains two pixels. It FREQUENCY – MHz is possible to define this area to contain four pixels (Border Area Figure 15. Plot of the Interpolation Filter for the Y Data Control).
It is also possible to compensate for variable block positioning or 0 differences in YCrCb pixel timing with the use of the Block Offset Control. (Mode Register 8, DNR Registers 0–2.) –10
DOUBLE BUFFERING –20
Double buffering can be enabled or disabled on the following dB registers: Closed Captioning Registers, Brightness Control Reg- – –30 ister, V-Scale, U-Scale Contrast Control Register, Hue Adjust Register, Macrovision Registers, and the Gamma Curve Select –40 bit. These registers are updated once per field on the falling AMPLITUDE –50 edge of the VSYNC signal. Double Buffering improves the overall performance of the ADV7192, since modifications to register –60 settings will not be made during active video, but take effect on the start of the active video. (Mode Register 8.) –70 0305 10 15 20 25 FREQUENCY – MHz GAMMA CORRECTION CONTROL Gamma correction may be performed on the luma data. The Figure 16. Plot of the Interpolation Filter for the CrCb Data user has the choice to use either of two different gamma curves, It is assumed that there is no color space conversion or any other A or B. At any one time one of these curves is operational if such operation to be performed on the incoming data. Thus if gamma correction is enabled. Gamma correction allows the these DAC outputs are to drive a TV, all relevant timing and mapping of the luma data to a user-defined function. (Mode synchronization data should be contained in the incoming digital Register 8, Gamma Correction Registers 0–13.) Y data. An FPGA can be used to achieve this,
NTSC PEDESTAL CONTROL The block diagram below shows a possible configuration for In NTSC mode it is possible to have the pedestal signal gener- progressive scan mode using the ADV7192. ated on the output video signal. (Mode Register 2.)
–18– REV. A ADV7192
error would be maintained forever, but in reality, this is impos- ENCODER ADV7192 sible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. 54MHz PLL I Resetting the SCH phase every four or eight fields avoids the N 27MHz T O accumulation of SCH phase error, and results in very minor SCH E 6 U R T phase jumps at the start of the four or eight field sequence. MPEG2 ENCODER P D P PIXEL BUS CORE 2 A U O Resetting the SCH phase should not be done if the video source L C T A S does not have stable timing or the ADV7192 is configured in RTC T PROGRESSIVE I mode. Under these conditions (unstable video) the Subcarrier SCAN 30-BIT INTERFACE O DECODER N Phase Reset should be enabled but no reset applied. In this configuration the SCH Phase will never be reset; this means that the output video will now track the unstable input video. The Sub- Figure 17. Block Diagram Using the ADV7192 in Progres- carrier Phase Reset when applied will reset the SCH phase to Field sive Scan Mode 0 at the start of the next field (e.g., Subcarrier Phase Reset applied The progressive scan decoder deinterlaces the data from the in Field 5 (PAL) on the start of the next field SCH phase will be MPEG2 decoder. This now means that there are 525 video lines reset to Field 0). (Mode Register 4.) per field in NTSC mode and 625 video lines per field in PAL mode. The duration of the video line is now 32 µs. SLEEP MODE If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins It is important to note that the data from the MPEG2 decoder are both set high, the ADV7192 will power up in Sleep Mode to is in 4:2:2 format. The data output from the progressive scan facilitate low power consumption before all registers have been decoder is in 4:4:4 format. Thus it is assumed that some form of initialized. interpolation on the color component data is performed in the progressive scan decoder IC. (Mode Register 8.) If Power-up in Sleep Mode is disabled, Sleep Mode control passes to the Sleep Mode control in Mode Register 2 (i.e., con- 2 REAL-TIME CONTROL, SUBCARRIER RESET, AND trol via I C). (Mode Register 2 and Mode Register 6.) TIMING RESET Together with the SCRESET/RTC/TR pin and Mode Register 4 SQUARE PIXEL MODE (Genlock Control), the ADV7192 can be used in (a) Timing The ADV7192 can be used to operate in square pixel mode. For Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode. NTSC operation an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz (a) A TIMING RESET is achieved in holding this pin high. In is required. The internal timing logic adjusts accordingly for this state the horizontal and vertical counters will remain reset. square pixel mode operation. Square pixel mode is not available On releasing this pin (set to low), the internal counters will in 4× Oversampling mode. (Mode Register 2.) commence counting again. The minimum time the pin has to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise VERTICAL BLANKING DATA INSERTION AND BLANK the reset signal might not be recognized. INPUT (b) The SUBCARRIER PHASE will reset to that of Field 0 at It is possible to allow encoding of incoming YCbCr data on the start of the following field when a low to high transition those lines of VBI that do not have line sync or pre-/post-equal- occurs on this input pin. ization pulses . This mode of operation is called Partial Blanking. It (c) In RTC MODE, the ADV7192 can be used to lock to an allows the insertion of any VBI data (Opened VBI) into the external video source. encoded output waveform, this data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS The real-time control mode allows the ADV7192 to auto- etc.). Alternatively the entire VBI may be blanked (no VBI data matically alter the subcarrier frequency to compensate for line inserted) on these lines. VBI is available in all timing modes. length variations. When the part is connected to a device that outputs a digital datastream in the RTC format (such as It is possible to allow control over the BLANK signal using a ADV7185 video decoder, see Figure 21), the part will Timing Register 0. When the BLANK input is enabled (TR03 = automatically change to the compensated subcarrier frequency 0 and input pin tied low), the BLANK input can be used to on a line-by-line basis. This digital datastream is 67 bits input externally generated blank signals in Slave Mode 1, 2, or wide and the subcarrier is contained in Bits 0 to 21. Each bit 3. When the BLANK input is disabled (TR03 = 1 and input pin is two clock cycles long. 00Hex should be written into all four tied low or tied high) the BLANK input is not used and the Subcarrier Frequency registers when using this mode. (Mode ADV7192 automatically blanks all normally blank lines as per Register 4.) CCIR-624. (Timing Register 0.)
SCH PHASE MODE The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase
REV. A –19– ADV7192
YUV LEVELS 2 FILTER This functionality allows the ADV7192 to output SMPTE levels 0dB REQUIREMENTS or Betacam levels on the Y output when configured in PAL or 4 FILTER NTSC mode. REQUIREMENTS Sync Video Betacam 286 mV 714 mV SMPTE 300 mV 700 mV –30dB MII 300 mV 700 mV 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz × × As the data path is branched at the output of the filters, the luma Figure 19. Output Filter Requirements in 2 and 4 Over- signal relating to the CVBS or S-Video Y/C output is unaltered. sampling Mode Only the Y output of the YCrCb outputs is scaled. This control allows color component levels to have a peak-peak amplitude of VIDEO TIMING DESCRIPTION 700 mV, 1000 mV or the default values of 934 mV in NTSC and The ADV7192 is intended to interface to off-the-shelf MPEG1 700 mV in PAL. (Mode Register 5.) and MPEG2 Decoders. As a consequence, the ADV7192 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has 16-BIT INTERFACE several Video Timing Modes of operation that allow it to be It is possible to input data in 16-bit format. In this case, the configured as either System Master Video Timing Generator or interface only operates if the data is accompanied by separate a Slave to the System Video Timing Generator. The ADV7192 HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not generates all of the required horizontal and vertical timing periods available in Slave Mode 0 since EAV/SAV timing codes are and levels for the analog video outputs. used. (Mode Register 8.) The ADV7192 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color 4 OVERSAMPLING AND INTERNAL PLL bursts are disabled on appropriate lines and serration and equal- It is possible to operate all six DACs at 27 MHz (2× Oversam- ization pulses are inserted where required. × pling) or 54 MHz (4 Oversampling). In addition the ADV7192 supports a PAL or NTSC square pixel The ADV7192 is supplied with a 27 MHz clock synced with the operation. The part requires an input pixel clock of 24.5454 MHz incoming data. Two options are available: to run the device for NTSC square pixel operation and an input pixel clock of throughout at 27 MHz or to enable the PLL. In the latter case, 29.5 MHz for PAL square pixel operation. The internal horizontal even if the incoming data runs at 27 MHz, 4× Oversampling and line counters place the various video waveform sections in the cor- the internal PLL will output the data at 54 MHz. rect location for the new clock frequencies. NOTE The ADV7192 has four distinct Master and four distinct Slave In 4× Oversampling Mode the requirements for the optional timing configurations. Timing Control is established with output filters are different from those in 2× Oversampling. (Mode the bidirectional HSYNC, BLANK and VSYNC pins. Tim- Register 1, Mode Register 6.) See Appendix 6. ing Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. (Mode Regis-
2 ter 2, Timing Register 0, 1.) ENCODE ADV7192 6 I RESET SEQUENCE D N A When RESET becomes active the ADV7192 reverts to the default T PIXEL BUS ENCODER C MPEG2 E output configuration (see Appendix 8 for register settings). The 27MHz CORE R O 54MHz ADV7192 internal timing is under the control of the logic level P U OUTPUT O on the NTSC_PAL pin. T L P A U When RESET is released Y, Cr, Cb values corresponding to a T T I black screen are input to the ADV7192. Output timing signals S 54MHz O are still suppressed at this stage. DACs A, B, C are switched off PLL N and DACs D, E, F are switched on. Figure 18. PLL and 4× Oversampling Block Diagram When the user requires valid data, Pixel Data Valid Control is enabled (MR26 = 1) to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Regis- ters. If at this stage, the user wishes to select a different video standard to that on the NTSC_PAL pin, Standard I2C Control should be enabled (MR25 = 1) and the video standard required is selected by programming Mode Register 0 (Output Video Stan- dard Selection). Figure 20 illustrates the RESET sequence timing.
–20– REV. A ADV7192
RESET
DAC D, BLACK VALUE WITH SYNC VALID VIDEO DAC E XXXXXXX XXXXXXX
DAC F XXXXXXX XXXXXXX BLACK VALUE VALID VIDEO
DAC A, DAC B, XXXXXXX OFF VALID VIDEO DAC C
MR26 PIXEL_DATA_VALID XXXXXXX 0 1
DIGITAL TIMING XXXXXXX DIGITAL TIMING SIGNALS SUPPRESSED TIMING ACTIVE
Figure 20. RESET Sequence Timing Diagram
ADV7192 CLOCK
COMPOSITE LCC1 GLL SCRESET/RTC/TR GREEN/COMPOSITE/Y VIDEO e.g., VCR VIDEO BLUE/LUMA/U OR CABLE DECODER RED/CHROMA/V ADV7185 P19–P12 P7–P0 GREEN/COMPOSITE/Y BLUE/LUMA/U RED/CHROMA/V
SEQUENCE BIT2 5 BITS RESET H/L TRANSITION 4 BITS COUNT START RESERVED BIT3 RESERVED LOW 14 BITS RESERVED 128 RESERVED F PLL INCREMENT1 13 0 21 SC 0
RTC
TIME SLOT: 01 14 19 67 68 NOT USED IN VALID INVALID 8/LINE ADV7192 SAMPLE SAMPLE LOCKED CLOCK NOTES: 1 FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7192 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7192. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3RESET BIT RESET ADV7192’s DDS Figure 21. RTC Timing and Connections
REV. A –21– ADV7192
Mode 0 (CCIR–656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7192 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 22. The HSYNC, VSYNC and BLANK (if not used) pins should be tied high during this mode. Blank output is available.
ANALOG VIDEO
EAV CODE SAV CODE C F 0 0 X 8 1 8 1 0 F F A A A 8 1 8 1 F 0 0 X C C C C C INPUT PIXELS Y r Y F 0 0 Y 0 0 0 0 0 F F B B B 0 0 0 0 F 0 0 Y b Y r Y b Y r Y b ANCILLARY DATA (HANC) 4 CLOCK 4 CLOCK NTSC/PAL M SYSTEM 268 CLOCK (525 LlNES/60Hz) 1440 CLOCK 4 CLOCK PAL SYSTEM 4 CLOCK (625 LINES/50Hz) 280 CLOCK 1440 CLOCK END OF ACTIVE START OF ACTIVE VIDEO LINE VIDEO LINE Figure 22. Timing Mode 0, Slave Mode
Mode 0 (CCIR–656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7192 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 23 (NTSC) and Figure 24 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 25.
DISPLAY DISPLAY VERTICAL BLANK
522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22
H
V
F EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
H
V
F ODD FIELD EVEN FIELD
Figure 23. Timing Mode 0, NTSC Master Mode
–22– REV. A ADV7192
DISPLAY DISPLAY VERTICAL BLANK
622 623 624 625 1 2 3 4 5 67 21 22 23
H
V
F EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
309 310 311 312313 314 315 316 317 318 319 320 334 335 336
H
V
F ODD FIELD EVEN FIELD
Figure 24. Timing Mode 0, PAL Master Mode
ANALOG VIDEO
H
F
V
Figure 25. Timing Mode 0 Data Transitions, Master Mode
REV. A –23– ADV7192
Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7192 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 26 (NTSC) and Figure 27 (PAL).
DISPLAY DISPLAY VERTICAL BLANK
522 523 524 525 12345 6789 10 11 20 21 22
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
FIELD ODD FIELD EVEN FIELD
Figure 26. Timing Mode 1, NTSC
DISPLAY DISPLAY VERTICAL BLANK
62262362462512345 67 21 22 23
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
FIELD ODD FIELD EVEN FIELD
Figure 27. Timing Mode 1, PAL
–24– REV. A ADV7192
Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7192 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 26 (NTSC) and Figure 27 (PAL). Figure 28 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2
BLANK
PIXEL Cb Y Cr Y DATA PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 28. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7192 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 29 (NTSC) and Figure 30 (PAL).
DISPLAY DISPLAY VERTICAL BLANK
522 523 524 525 12345 6789 10 11 20 21 22
HSYNC
BLANK
VSYNC EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
VSYNC ODD FIELD EVEN FIELD
Figure 29. Timing Mode 2, NTSC
REV. A –25– ADV7192
DISPLAY DISPLAY VERTICAL BLANK
62262362462512345 67 21 22 23
HSYNC
BLANK
VSYNC EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
VSYNC ODD FIELD EVEN FIELD
Figure 30. Timing Mode 2, PAL
Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7192 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 29 (NTSC) and Figure 30 (PAL). Figure 31 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 32 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2
BLANK
PIXEL Cb Y Cr Y DATA PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 31. Timing Mode 2, Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2
BLANK
PIXEL Cb Y Cr Y Cb DATA
PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 32. Timing Mode 2, Odd-to-Even Field Transition Master/Slave
–26– REV. A ADV7192
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7192 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 33 (NTSC) and Figure 34 (PAL).
DISPLAY DISPLAY VERTICAL BLANK
522 523 524 525 12345 6789 10 11 20 21 22
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
FIELD ODD FIELD EVEN FIELD
Figure 33. Timing Mode 3, NTSC
DISPLAY DISPLAY VERTICAL BLANK
622 623 624 625 1 2 3 4 5 67 21 22 23
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
DISPLAY DISPLAY VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
Figure 34. Timing Mode 3, PAL
REV. A –27– ADV7192
MPU PORT DESCRIPTION The ADV7192 acts as a standard slave device on the bus. The 2 The ADV7192 support a two-wire serial (I C-compatible) data on the SDA pin is eight bits long supporting the 7-bit microprocessor bus driving multiple peripherals. Two inputs, addresses plus the R/W bit. It interprets the first byte as the device Serial Data (SDA) and Serial Clock (SCL), carry information address and the second byte as the starting subaddress. The between any device connected to the bus. Each slave device is subaddresses autoincrement allowing data to be written to or read recognized by a unique address. The ADV7192 has four possible from the starting subaddress. A data transfer is always terminated slave addresses for both read and write operations. These are by a stop condition. The user can also access any unique subaddress unique addresses for each device and are illustrated in Figure 35 register on a one-by-one basis without having to update all the and Figure 37. The LSB sets either a read or write operation. registers. There is one exception. The Subcarrier Frequency Logic Level 1 corresponds to a read operation while Logic Level Registers should be updated in sequence, starting with Subcarrier 0 corresponds to a write operation. A1 is set by setting the ALSB Frequency Register 0. The autoincrement function should be pin of the ADV7192 to Logic Level 0 or Logic Level 1. When then used to increment and access Subcarrier Frequency Registers 2 ALSB is set to 0, there is greater input bandwidth on the I C 1, 2, and 3. The Subcarrier Frequency Registers should not be lines, which allows high speed data transfers on this bus. When accessed independently. ALSB is set to 1, there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass Stop and start conditions can be detected at any stage during into the I2C internal controller. This mode is recommended for the data transfer. If these conditions are asserted out of sequence noisy systems. with normal read and write operations, then, these cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one start condition, one stop 1 10101A1X condition, or a single stop condition followed by a single start ADDRESS condition. If an invalid subaddress is issued by the user, the CONTROL ADV7192 will not issue an acknowledge and will return to the SETUP BY ALSB idle condition. If, in autoincrement mode, the user exceeds the
READ/WRITE highest subaddress, then the following action will be taken: CONTROL 0 WRITE 1. In Read Mode, the highest subaddress register contents 1 READ will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A Figure 35. Slave Address no-acknowledge condition is where the SDA line is not pulled To control the various devices on the bus the following protocol low on the ninth pulse. must be followed. First, the master initiates a data transfer by 2. In Write Mode, the data for the invalid byte will be not be establishing a start condition, defined by a high-to-low transition loaded into any subaddress register, a no-acknowledge will on SDA while SCL remains high. This indicates that an address/ be issued by the ADV7192 and the part will return to the data stream will follow. All peripherals respond to the start con- idle condition. dition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data SDATA line low during the ninth clock pulse. This is known as an acknowl- edge bit. All other devices withdraw from the bus at this point SCLOCK S 1 7 89 1 789 1789 P and maintain an idle condition. The idle condition is where START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit Figure 36. Bus Data Transfer determines the direction of the data. Figure 36 illustrates an example of data transfer for a read A Logic 0 on the LSB of the first byte means that the master sequence and the start and stop conditions. will write information to the peripheral. A Logic 1 on the LSB Figure 37 shows bus write and read sequences. of the first byte means that the master will read information from the peripheral.
WRITE SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P LSB = 0 LSB = 1
READ A(M) SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M ) P S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO ACKNOWLEDGE BY MASTER Figure 37. Write and Read Sequences
–28– REV. A ADV7192
REGISTER ACCESSES Subaddress Register (SR7–SR0) The MPU can write to or read from all of the registers of the The Communications Register is an eight bit write-only register. ADV7192 with the exception of the Subaddress Registers which After the part has been accessed over the bus and a read/write are write only registers. The Subaddress Register determines operation is selected, the subaddress is set up. The Subaddress Reg- which register the next read or write operation accesses. All com- ister determines to/from which register the operation takes place. munications with the part through the bus start with an access Figure 38 shows the various operations under the control of the to the Subaddress Register. Then a read/write operation is per- Subaddress Register 0 should always be written to SR7. formed from/to the target address which then increments to the next address until a stop command on the bus is performed. Register Select (SR6–SR0) These bits are set up to point to the required starting address. REGISTER PROGRAMMING The following section describes each register. All registers can be read from as well as written to.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
SR7 ADV7192 SUBADDRESS REGISTER ZERO SHOULD ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR0 BE WRITTEN HERE 00H 0 0 0 0 0 0 0 MODE REGISTER 0 01H 0 0 0 0 0 0 1 MODE REGISTER 1 02H 0 0 0 0 0 1 0 MODE REGISTER 2 03H 0 0 0 0 0 1 1 MODE REGISTER 3 04H 0 0 0 0 1 0 0 MODE REGISTER 4 05H 0 0 0 0 1 0 1 MODE REGISTER 5 06H 0 0 0 0 1 1 0 MODE REGISTER 6 07H 0 0 0 0 1 1 1 MODE REGISTER 7 08H 0 0 0 1 0 0 0 MODE REGISTER 8 09H 0 0 0 1 0 0 1 MODE REGISTER 9 0AH 0 0 0 1 0 1 0 TIMING REGISTER 0 0BH 0 0 0 1 0 1 1 TIMING REGISTER 1 0CH 0 0 0 1 1 0 0 SUBCARRIER FREQUENCY REGISTER 0 0DH 0 0 0 1 1 0 1 SUBCARRIER FREQUENCY REGISTER 1 0EH 0 0 0 1 1 1 0 SUBCARRIER FREQUENCY REGISTER 2 0FH 0 0 0 1 1 1 1 SUBCARRIER FREQUENCY REGISTER 3 10H 0 0 1 0 0 0 0 SUBCARRIER PHASE REGISTER 11H 0 0 1 0 0 0 1 CLOSED CAPTIONING EXTENDED DATA BYTE 0 12H 0 0 1 0 0 1 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 13H 0 0 1 0 0 1 1 CLOSED CAPTIONING DATA BYTE 0 14H 0 0 1 0 1 0 0 CLOSED CAPTIONING DATA BYTE 1 15H 0 0 1 0 1 0 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0 16H 0 0 1 0 1 1 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1 17H 0 0 1 0 1 1 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2 18H 0 0 1 1 0 0 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3 19H 0 0 1 1 0 0 1 CGMS/WSS 0 1AH 0 0 1 1 0 1 0 CGMS/WSS 1 1BH 0 0 1 1 0 1 1 CGMS/WSS 2 1CH 0 0 1 1 1 0 0 TELETEXT REQUEST CONTROL REGISTER 1DH 0 0 1 1 1 0 1 CONTRAST CONTROL REGISTER 1EH 0 0 1 1 1 1 0 U SCALE REGISTER 1FH 0 0 1 1 1 1 1 V SCALE REGISTER 20H 0 1 0 0 0 0 0 HUE ADJUST CONTROL REGISTER 21H 0 1 0 0 0 0 1 BRIGHTNESS CONTROL REGISTER 22H 0 1 0 0 0 1 0 SHARPNESS RESPONSE REGISTER 23H 0 1 0 0 0 1 1 DNR REGISTER 0 24H 0 1 0 0 1 0 0 DNR REGISTER 1 25H 0 1 0 0 1 0 1 DNR REGISTER 2 26H 0 1 0 0 1 1 0 GAMMA CORRECTION REGISTER 0 27H 0 1 0 0 1 1 1 GAMMA CORRECTION REGISTER 1 28H 0 1 0 1 0 0 0 GAMMA CORRECTION REGISTER 2 29H 0 1 0 1 0 0 1 GAMMA CORRECTION REGISTER 3 2AH 0 1 0 1 0 1 0 GAMMA CORRECTION REGISTER 4 2BH 0 1 0 1 0 1 1 GAMMA CORRECTION REGISTER 5 2CH 0 1 0 1 1 0 0 GAMMA CORRECTION REGISTER 6 2DH 0 1 0 1 1 0 1 GAMMA CORRECTION REGISTER 7 2EH 0 1 0 1 1 1 0 GAMMA CORRECTION REGISTER 8 2FH 0 1 0 1 1 1 1 GAMMA CORRECTION REGISTER 9 30H 0 1 1 0 0 0 0 GAMMA CORRECTION REGISTER 10 31H 0 1 1 0 0 0 1 GAMMA CORRECTION REGISTER 11 32H 0 1 1 0 0 1 0 GAMMA CORRECTION REGISTER 12 33H 0 1 1 0 0 1 1 GAMMA CORRECTION REGISTER 13 34H 0 1 1 0 1 0 0 BRIGHTNESS DETECT REGISTER 35H 0 1 1 0 1 0 1 OUTPUT CLOCK REGISTER 36H 0 1 1 0 1 1 0 RESERVED 37H 0 1 1 0 1 1 1 RESERVED 38H 0 1 1 1 0 0 0 RESERVED 39H 0 1 1 1 0 0 1 RESERVED 3AH 0 1 1 1 0 1 0 MACROVISION REGISTER 3BH 0 1 1 1 0 1 1 MACROVISION REGISTER 3CH 0 1 1 1 1 0 0 MACROVISION REGISTER 3DH 0 1 1 1 1 0 1 MACROVISION REGISTER 3EH 0 1 1 1 1 1 0 MACROVISION REGISTER 3FH 1 1 1 1 1 1 1 MACROVISION REGISTER 40H 1 0 0 0 0 0 0 MACROVISION REGISTER 41H 1 0 0 0 0 0 1 MACROVISION REGISTER 42H 1 0 0 0 0 1 0 MACROVISION REGISTER 43H 1 0 0 0 0 1 1 MACROVISION REGISTER 44H 1 0 0 0 1 0 0 MACROVISION REGISTER 45H 1 0 0 0 1 0 1 MACROVISION REGISTER 46H 1 0 0 0 1 1 0 MACROVISION REGISTER 47H 1 0 0 1 1 1 1 MACROVISION REGISTER 48H 1 0 0 1 0 1 0 MACROVISION REGISTER 49H 1 0 0 1 0 0 1 MACROVISION REGISTER 4AH 1 0 0 1 0 0 0 MACROVISION REGISTER 4BH 1 0 0 1 0 1 1 MACROVISION REGISTER
Figure 38. Subaddress Register for the ADV7192
REV. A –29– ADV7192
MODE REGISTER 0 MODE REGISTER 1 MR0 (MR07–MR00) MR1 (MR17–MR10) (Address (SR4–SR0) = 00H) (Address (SR4–SR0) = 01H) Figure 39 shows the various operations under the control of Figure 40 shows the various operations under the control of Mode Register 0. Mode Register 1.
MR0 BIT DESCRIPTION MR1 BIT DESCRIPTION Output Video Standard Selection Control (MR00–MR01) DAC Control (MR10–MR15) These bits are used to set up the encoder mode. The ADV7192 Bits MR15–MR10 can be used to power-down the DACs. This are can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or used to reduce the power consumption of the ADV7192 or if any PAL N standard video. of the DACs are not required in the application. Luminance Filter Select (MR02–MR04) 4 Oversampling Control (MR16) These bits specify which luma filter is to be selected. The filter To enable 4× Oversampling this bit has to be set to 1. When selection is made independent of whether PAL or NTSC is enabled, the data is output at a frequency of 54 MHz. selected. Note that PLL Enable Control has to be enabled (MR61 = 0) in Chrominance Filter Select (MR05–MR07) 4× Oversampling mode. An external VREF is not recommended These bits select the chrominance filter. A low-pass filter can be in that mode. selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz, Reserved (MR17) 1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or A Logical 0 must be written to this bit. QCIF filters.
MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00
CHROMA FILTER SELECT OUTPUT VIDEO STANDARD SELECTION MR07 MR06 MR05 MR01 MR00 0 0 0 1.3 MHz LOW-PASS FILTER 0 0 1 0.65 MHz LOW-PASS FILTER 0 0 NTSC 0 1 0 1.0 MHz LOW-PASS FILTER 0 1 PAL (B, D, G, H, I) 0 1 1 2.0 MHz LOW-PASS FILTER 1 0 PAL (M) 1 0 0 RESERVED 1 1 PAL (N) 1 0 1 CIF 1 1 0 QCIF 1 1 1 3.0 MHz LOW-PASS FILTER
LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 LOW-PASS FILTER (NTSC) 0 0 1 LOW-PASS FILTER (PAL) 0 1 0 NOTCH FILTER (NTSC) 0 1 1 NOTCH FILTER (PAL) 1 0 0 EXTENDED MODE 1 0 1 CIF 1 1 0 QCIF 1 1 1 RESERVED
Figure 39. Mode Register 0, MR0
MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10
MR17 DAC A DAC C DAC E ZERO MUST DAC CONTROL DAC CONTROL DAC CONTROL BE WRITTEN MR15 MR13 MR11 TO THIS BIT 0 POWER-DOWN 0 POWER-DOWN 0 POWER-DOWN 1 NORMAL 1 NORMAL 1 NORMAL
4 OVERSAMPLING DAC B DAC D DAC F CONTROL DAC CONTROL DAC CONTROL DAC CONTROL MR16 MR14 MR12 MR10 02 OVERSAMPLING 0 POWER-DOWN 0 POWER-DOWN 0 POWER-DOWN 14 OVERSAMPLING 1 NORMAL 1 NORMAL 1 NORMAL
Figure 40. Mode Register 1, MR1
–30– REV. A ADV7192
MODE REGISTER 2 Standard I2C Control (MR25) MR2 (MR27–MR20) This bit controls the video standard used by the ADV7192. (Address (SR4–SR0) = 02H) When this bit is set to 1 the video standard is as programmed in Mode Register 2 is an 8-bit-wide register. Mode Register 0 (Output Video Standard Selection). When it is Figure 41 shows the various operations under the control of Mode set to 0, the ADV7192 is forced into the standard selected by Register 2. the NTSC_PAL pin. When NTSC_PAL is low, the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL. MR2 BIT DESCRIPTION—RGB/YUV Control (MR20) This bit enables the output from the DACs to be set to YUV or Pixel Data Valid Control (MR26) RGB output video standard. After resetting the device this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is DAC Output Control (MR21) output from the DACs. The ADV7192 will be set to Master Mode This bit controls the output from DACs A, B, and C. When this timing. When this bit is set to 1 by the user (via the I2C), pixel bit is set to 1, Composite, Luma and Chroma Signals are output data passes to the pins and the encoder reverts to the timing mode from DACs A, B, and C (respectively). When this bit is set to 0, defined by Timing Register 0. RGB or YUV may be output from these DACs. Sleep Mode Control (MR27) SCART Enable Control (MR22) When this bit is set (1), Sleep Mode is enabled. With this mode This bit is used to switch the DAC outputs from SCART to a enabled, the ADV7192 current consumption is reduced to typi- EUROSCART configuration. A complete table of all DAC out- cally 0.1 µA. The I2C registers can be written to and read from put configurations is shown below. when the ADV7192 is in Sleep Mode. Pedestal Control (MR23) When the device is in Sleep Mode and 0 is written to MR27, the This bit specifies whether a pedestal is to be generated on the ADV7192 will come out of Sleep Mode and resume normal NTSC composite video signal. This bit is invalid when the device operation. Also, if a RESET is applied during Sleep Mode the is configured in PAL mode. ADV7192 will come out of Sleep Mode and resume normal Square Pixel Control (MR24) operation. This bit is used to set up square pixel mode. This is available in For this to operate Power up in Sleep Mode control has to be Slave Mode only. For NTSC, a 24.54 MHz clock must be sup- enabled (MR60 is set to a Logic 0), otherwise Sleep Mode is plied. For PAL, a 29.5 MHz clock must be supplied. Square controlled by the PAL_NTSC and SCRESET/RTC/TR pins. pixel operation is not available in 4× Oversampling mode.
MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20
PIXEL DATA SQUARE PIXEL SCART ENABLE RGB/YUV VALID CONTROL CONTROL CONTROL CONTROL MR26 MR24 MR22 MR20 0 DISABLE 0 DISABLE 0 DISABLE 0 RGB OUTPUT 1 ENABLE 1 ENABLE 1 ENABLE 1 YUV OUTPUT
SLEEP MODE STANDARD I2C PEDESTAL DAC OUTPUT CONTROL CONTROL CONTROL CONTROL MR27 MR25 MR23 MR21 0 DISABLE 0 DISABLE 0 PEDESTAL OFF 0 RGB/YUV/COMP 1 ENABLE 1 ENABLE 1 PEDESTAL ON 1 COMP/LUMA/CHROMA
Figure 41. Mode Register 2, MR2
Table III. DAC Output Configuration
MR22 MR21 MR20 DAC A DAC B DAC C DAC D DAC E DAC F 0 0 0 G (Y) B (Pb) R (Pr) CVBS LUMA CHROMA 0 0 1 Y (Y) U (Pb) V (Pr) CVBS LUMA CHROMA 0 1 0 CVBS LUMA CHROMA G (Y) B (Pb) R (Pr) 0 1 1 CVBS LUMA CHROMA Y (Y) U (Pb) V (Pr) 1 0 0 CVBS B (Pb) R (Pr) G (Y) LUMA CHROMA 1 0 1 CVBS U (Pb) V (Pr) Y (Y) LUMA CHROMA 1 1 0 CVBS LUMA CHROMA G (Y) B (Pb) R (Pr) 1 1 1 CVBS LUMA CHROMA Y (Y) U (Pb) V (Pr) NOTE In Progressive Scan Mode (MR80 = 1) the DAC output configuration is stated in the brackets.
REV. A –31– ADV7192
MODE REGISTER 3 Genlock Control (MR41–MR42) MR3 (MR37–MR30) These bits control the Genlock feature and timing reset of the (Address (SR4–SR0) = 03H) ADV7192. Setting MR41 and MR42 to Logic 0 disables the Mode Register 3 is an 8-bit-wide register. Figure 42 shows the SCRESET/RTC/TR pin and allows the ADV7192 to operate various operations under the control of Mode Register 3. in normal mode. 1. By setting MR41 to zero and MR42 to one, a timing reset is MR3 BIT DESCRIPTION applied, resetting the horizontal and vertical counters. This Revision Code (MR30–MR31) has the effect of resetting the Field Count to Field 0. This bit is read only and indicates the revision of the device. If the SCRESET/RTC/TR pin is held high, the counters VBI Open (MR32) will remain reset. Once the pin is released the counters will This bit determines whether or not data in the Vertical Blanking commence counting again. For correct counter reset, the Interval (VBI) is output to the analog outputs or blanked. Note SCRESET/RTC/TR pin has to remain high for at least that this condition is also valid in Timing Slave Mode 0. For 37 ns (one clock cycle at 27 MHz). further information see Vertical Blanking Data Insertion and BLANK Input section. 2. If MR41 is set to one and MR42 is set to zero, the SCRESET/ RTC/TR pin is configured as a subcarrier reset input and Teletext Enable (MR33) the subcarrier phase will reset to Field 0 whenever a low-to- This bit must be set to 1 to enable teletext data insertion on the high transition is detected on the SCRESET/RTC/TR pin TTX pin. Note: TTX functionality is shared with VSO and (SCH phase resets at the start of the next field). CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP–VSO Output (MR76) have to be set accordingly. 3. If MR41 is set to one and MR42 is set to one, the SCRESET/ RTC/TR pin is configured as a real time control input and Teletext Bit Request Mode Control (MR34) the ADV7192 can be used to lock to an external video source This bit enables switching of the teletext request signal from a working in RTC mode. See Real-Time Control, Subcarrier continuous high signal (MR34 = 0) to a bitwise request signal Reset and Timing Reset section. (MR34 = 1). Active Video Line Duration (MR43) Closed Captioning Field Selection (MR35–MR36) This bit switches between two active video line durations. A zero These bits control the fields that closed captioning data is dis- selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one played on, closed captioning information can be displayed on selects ITU-R BT. 470 standard for active video duration (710 an odd field, even field or both fields. pixels NTSC, 702 pixels PAL). Reserved (MR37) Chrominance Control (MR44) A Logic 0 must be written to this bit. This bit enables the color information to be switched on and off the chroma, composite and color component outputs. MODE REGISTER 4 MR4 (MR47–MR40) Burst Control (MR45) (Address (SR4–SR0) = 04H) This bit enables the color burst to be switched on and off the Mode Register 4 is an 8-bit-wide register. Figure 43 shows the chroma and composite outputs. various operations under the control of Mode Register 4. Color Bar Control (MR46) This bit can be used to generate and output an internal color MR4 BIT DESCRIPTION bar test pattern. The color bar configuration is 100/7.5/75/7.5 VSYNC_3H Control (MR40) for NTSC and 100/0/75/0 for PAL. It is important to note that When this bit is enabled (1) in Slave Mode, it is possible to when color bars are enabled the ADV7192 is configured in a drive the VSYNC input low for 2.5 lines in PAL mode and Master Timing mode. The output pins VSYNC, HSYNC and three lines in NTSC mode. When this bit is enabled in Master BLANK are three-state during color bar mode. Mode the ADV7192 outputs an active low VSYNC signal for three Interlaced Mode Control (MR47) lines in NTSC mode and 2.5 lines in PAL mode. This bit is used to setup the output to interlaced or noninter- laced mode.
MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30
TTX BIT REQUEST MR37 MODE CONTROL VBI OPEN MR31 MR30 MR34 MR32 ZERO MUST BE RESERVED FOR WRITTEN TO 0 DISABLE 0 DISABLE REVISION CODE THIS BIT 1 ENABLE 1 ENABLE
CLOSED CAPTIONING TELETEXT FIELD SELECTION ENABLE MR36 MR35 MR33 0 0 NO DATA OUT 0 DISABLE 0 1 ODD FIELD ONLY 1 ENABLE 1 0 EVEN FIELD ONLY 1 1 DATA OUT (BOTH FIELDS)
Figure 42. Mode Register 3, MR3 –32– REV. A ADV7192
MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40
COLOR BAR CHROMINANCE GENLOCK CONTROL CONTROL CONTROL MR42 MR41 MR46 MR44 0 0 DISABLE GENLOCK 0 DISABLE 0 ENABLE COLOR 1 ENABLE 1 DISABLE COLOR 0 1 ENABLE SUBCARRIER RESET PIN 1 0 TIMING RESET 1 1 ENABLE RTC PIN
INTERLACE MODE BURST ACTIVE VIDEO VSYNC 3H CONTROL CONTROL LINE DURATION CONTROL MR47 MR45 MR43 MR40 0 INTERLACED 0 ENABLE BURST 0 720 PIXELS 0 DISABLE 1 NONINTERLACED 1 DISABLE BURST 1 710 PIXELS/702 PIXELS 1 ENABLE
Figure 43. Mode Register 4, MR4
MODE REGISTER 5 RGB Sync (MR53) MR5 (MR57–MR50) This bit is used to set up the RGB outputs with the sync infor- (Address (SR4–SR0) = 05H) mation encoded on all RGB outputs. Mode Register 5 is a 8-bit-wide register. Figure 44 shows the Clamp Delay (MR54–MR55) various operations under the control of Mode Register 5. These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7192. It is possible to delay or MR5 BIT DESCRIPTION advance the pulse by zero, one, two or three clock cycles. Y-Level Control (MR50) This bit controls the component Y output level on the ADV7192 Note: TTX functionality is shared with VSO and CLAMP on Pin If this bit is set (0), the encoder outputs Betacam levels when 62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP–VSO configured in PAL or NTSC mode. If this bit is set (1), the Output (MR76) have to be set accordingly. encoder outputs SMPTE levels when configured in PAL or Clamp Delay Direction (MR56) NTSC mode. This bit controls a positive or negative delay in the CLAMP sig- UV-Levels Control (MR51–MR52) nal. If this bit is set (1), the delay is negative. If it is set (0), the These bits control the component U and V output levels on the delay is positive. ADV7192. It is possible to have UV levels with a peak-to-peak Clamp Position (MR57) amplitude of either 700 mV (MR52 + MR51 = 01) or 1000 mV This bit controls the position of the CLAMP signal. If this bit is (MR52 + MR51 = 10) in NTSC and PAL. It is also possible to set (1), the CLAMP signal is located in the back porch position. have default values of 934 mV for NTSC and 700 mV for PAL If this bit is set (0), the CLAMP signal is located in the front (MR52 + MR51 = 00). porch position.
MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50
CLAMP DELAY RGB SYNC Y LEVEL DIRECTION CONTROL MR56 MR53 MR50 0 POSITIVE 0 DISABLE 0 DISABLE 1 NEGATIVE 1 ENABLE 1 ENABLE
CLAMP CLAMP DELAY UV LEVEL CONTROL POSITION MR55 MR54 MR52 MR51 MR57 0 0 NO DELAY 0 0 DEFAULT LEVELS 0 FRONT PORCH 011 PCLK 0 1 700mV 1 BACK PORCH 102 PCLK 1 0 1000mV 113 PCLK 1 1 RESERVED
Figure 44. Mode Register 5, MR5
REV. A –33– ADV7192
MR67 MR66 MR65 MR64 MR63 MR62 MR61 MR60
MR67 MR66 MR65 MR64 MR63 MR62 PLL ENABLE POWER-UP SLEEP CONTROL MODE CONTROL ZERO MUST FIELD COUNTER BE WRITTEN MR61 MR60 TO THESE BITS 0 ENABLED 0 ENABLED 1 DISABLED 1 DISABLED Figure 45. Mode Register 6, MR6
Mode Register 6 Luma Saturation Control (MR71) MR6 (MR67–MR60) When this bit is set (1), the luma signal will be clipped if it reaches (Address (SR4–SR0) = 06H) a limit that corresponds to an input luma value of 255 (after Mode Register 6 is a 8-bit-wide register. Figure 45 shows the scaling by the Contrast Control Register). This prevents the various operations under the control of Mode Register 6. chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is MR6 BIT DESCRIPTION set (0), this control is disabled. Power-Up Sleep Mode Control (MR60) Hue Adjust Control (MR72) After RESET is applied this control is enabled (MR60 = 0) if This bit is used to enable hue adjustment on the composite and both SCRESET/RTC/TR and NTSC_PAL pins are tied high. chroma output signals of the ADV7192. When this bit is set (1), The ADV7192 will then power up in Sleep Mode to facilitate the hue of the color is adjusted by the phase offset described in low power consumption before the I2C is initialized. When this the Hue Adjust Control Register. When this bit is set (0), hue control is disabled (MR60 = 1, via the I2C) Sleep Mode control adjustment is disabled. passes to Sleep Mode Control, MR27. Brightness Enable Control (MR73) PPL Enable Control (MR61) This bit is used to enable brightness control on the ADV7192. × The PLL control should be enabled (MR61 = 0 ) when 4 The actual brightness level is programmed in the Brightness Oversampling is enabled (MR16 = 1). When this bit is toggled, Control Register. This value or set-up level is added to the scaled it is also used to reset the PLL. Y data. When this bit is set (1), brightness control is enabled. Reserved (MR62, MR63, MR64) When this bit is set (0), brightness control is disabled. A Logical 0 must be written to these bits. Sharpness Filter Enable (MR74) Field Counter (MR65, MR66, MR67) This bit is used to enable the sharpness control of the luminance These three bits are read only bits. The field count can be read signal on the ADV7192 (Luma Filter Select has to be set to back over the I2C interface. In NTSC mode the field count goes Extended, MR04–MR02 = 100). The various responses of the from 0–3, in PAL Mode from 0–7. filter are determined by the Sharpness Control Register. When this bit is set (1), the luma response is altered by the amount described MODE REGISTER 7 in the Sharpness Control Register. When this bit is set (0), the MR7 (MR77–MR70) sharpness control is disabled. See Internal Filter Response section (Address (SR4–SR0) = 07H) for luma signal responses. Mode Register 7 is a 8-bit-wide register. Figure 46 shows the CSO_HSO Output Control (MR75) various operations under the control of Mode Register 7. This bit is used to determine whether HSO or CSO TTL output signal is output at the CSO_HSO pin. If this bit is set (1), the MR7 BIT DESCRIPTION CSO TTL signal is output. If this bit is set (0), the HSO TTL Color Control Enable (MR70) signal is output. This bit is used to enable control of contrast and saturation of color. If this bit is set (1) color controls are enabled (Contrast TTX Input/CLAMP–VSO Output (MR76) Control Register, U-Scale Register, V-Scale Register). If this bit This bit controls whether Pin 62 is configured as an output or as is set (0), the color control features are disabled. an input pin. A 1 selects Pin 62 to be an output for CLAMP or VSO functionality. A 0 selects this pin as a TTX input pin.
MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70
TTX INPUT/CLAMP–VSO SHARPNESS FILTER HUE ADJUST COLOR CONTROL OUTPUT CONTROL ENABLE CONTROL ENABLE MR76 MR74 MR72 MR70 0 TTX INPUT 0 DISABLE 0 DISABLE 0 DISABLE 1 CLAMP/VSO 1 ENABLE 1 ENABLE 1 ENABLE OUTPUT
CLAMP/ VSO CSO_HSO BRIGHTNESS LUMA SATURATION SELECT OUTPUT CONTROL ENABLE CONTROL CONTROL MR77 MR75 MR73 MR71 0 VSO OUTPUT 0 HSO OUT 0 DISABLE 0 DISABLE 1 CLAMP OUTPUT 1 CSO OUT 1 ENABLE 1 ENABLE
Figure 46. Mode Register 7, MR7
–34– REV. A ADV7192
MR87 MR86 MR85 MR84 MR83 MR82 MR81 MR80
GAMMA ENABLE MR84 DOUBLE BUFFER PROGRESSIVE CONTROL CONTROL SCAN CONTROL ZERO SHOULD MR86 BE WRITTEN MR82 MR80 0 DISABLE TO THIS BIT 0 DISABLE 0 DISABLE 1 ENABLE 1 ENABLE 1 ENABLE
GAMMA CURVE DNR ENABLE 16-PIXEL MR81 SELECT CONTROL CONTROL PORT CONTROL ZERO SHOULD MR87 MR85 MR83 BE WRITTEN 0 CURVE A 0 DISABLE 0 DISABLE TO THIS BIT 1 CURVE B 1 ENABLE 1 ENABLE
Figure 47. Mode Register 8, MR8
CLAMP/VSO Select (MR77) Gamma Curve Select Control (MR87) This bit is used to select the functionality of Pin 62. Setting this This bit selects which of the two programmable gamma curves is bit to 1 selects CLAMP as the output signal. A 0 selects VSO to be used. When setting MR87 to 0, the gamma correction curve as the output signal. Since this pin is also shared with the TTX selected is Curve A. Otherwise, Curve B is selected. Each curve functionality, TTX Input/CLAMP–VSO Output has to be set will have to be programmed by the user. For further information accordingly (MR76). on Gamma Correction controls see Gamma Correction Regis- ters section. MODE REGISTER 8 MR8 (MR87–MR80) MODE REGISTER 9 (Address (SR4–SR0) = 08H) MR9 (MR97–MR90) Mode Register 8 is an 8-bit-wide register. Figure 47 shows the (Address (SR4–SR0) = 09H) various operations under the control of Mode Register 8. Mode Register 9 is an 8-bit-wide register. Figure 49 shows the various operations under the control of Mode Register 9. MR8 BIT DESCRIPTION Progressive Scan Control (MR80) MR9 BIT DESCRIPTION This control enables the progressive scan inputs on pins Undershoot Limiter (MR90–MR91) Y(0)/P8–Y(7)/P15, Y(8)–Y(9), Cr(0)–Cr(9), Cb(0)–Cb(9). To This control ensures that no luma video data will go below a enable this control MR80 has to be set to 1. It is assumed that programmable level. This prevents any synchronization problems the incoming Y data contains all necessary sync information. due to luma signals going below the blanking level. Available limit levels are –1.5 IRE, –6 IRE, –11 IRE. Note that this facility is Note: Simultaneous progressive scan input and 16-bit pixel input only available in 4× Oversampling mode (MR16 = 1). When the is not possible. device is operated in 2× Oversampling mode (MR16 = 0) or RGB Reserved (MR81) output without RGB sync are selected, the minimum luma level is A 0 must be written to this bit. set in Timing Register 0, TR06 (Min Luma Control). Double Buffer Control (MR82) Black Burst Y DAC (MR92) Double Buffering can be enabled or disabled on the Contrast It is possible to output a Black Burst signal from the DAC Control Register, U Scale Register, V Scale Register, Hue Adjust which is selected to be the Luma DAC (MR22, MR21, MR20). Control Register, Closed Captioning Register, Brightness Control This signal can be useful for locking two video sources together Register, Gamma Curve Select Bit and the Macrovision Regis- using professional video equipment. See also Black Burst Out- ters. Double Buffer is not available in Master Mode. put section. 16-Bit Pixel Port (MR83) Black Burst Luma (MR93) This bit controls if the ADV7192 is operated in 8-bit or 16-bit It is possible to output a Black Burst signal from the DAC which mode. In 8-bit mode the input data will be set up on Pins P0–P7. is selected to be the Y-DAC (MR22, MR21, MR20). This signal In 16-bit mode the first eight bits are set up on Pin 3–10, with can be useful for locking two video sources together using pro- LSB on Pin 3. The second eight bits are set up on Pin 13–20. fessional video equipment. See also Black Burst Output section. Reserved (MR84) A Logic 0 must be written to this bit. 3.58MHz COLOR BURST NTSC BLACK BURST SIGNAL (9 CYCLES) DNR Enable Control (MR85) 20 IRE To enable the DNR process this bit has to be set to 1. If this bit 0 IRE is set to other DNR processing is bypassed. For further informa- –20 IRE tion on DNR controls see DNR Mode Control section. –40 IRE 4.43MHz Gamma Enable Control (MR86) COLOR BURST To enable the programmable gamma correction this bit has to be (10 CYCLES) PAL BLACK BURST SIGNAL 21.5 IRE set to enabled (MR86 = 1). For further information on Gamma 0 IRE Correction controls see Gamma Correction Registers section. –21.5 IRE –43 IRE
Figure 48. Black Burst Signals for PAL and NTSC Standards REV. A –35– ADV7192
MR97 MR96 MR95 MR94 MR93 MR92 MR91 MR90
MR97 MR96 CHROMA BLACK BURST BLACK BURST UNDERSHOOT DELAY CONTROL LUMA DAC Y DAC LIMITER ZERO MUST BE WRITTEN MR95 MR94 MR93 MR92 MR91 MR90 TO THESE BITS 0 0 0ns DELAY 0 DISABLE 0 DISABLE 0 0 DISABLED 1 ENABLE 1 ENABLE 0 1 148ns DELAY 0 1 –11 IRE 1 0 296ns DELAY 1 0 –6 IRE 1 1 RESERVED 1 1 –1.5 IRE
Figure 49. Mode Register 9 (MR9)
Chroma Delay Control (MR94–MR95) Timing Register Reset (TR07) The Chroma signal can be delayed by up to 8 clock cycles at Toggling TR07 from low to high and low again resets the inter- 27 MHz using MR94–95. For further information see also nal timing counters. This bit should be toggled after power-up, Chroma/Luma Delay Section. reset or changing to a new timing mode.
TIMING REGISTER 0 (TR07–TR00) TIMING REGISTER 1 (TR17–TR10) (Address (SR4–SR0) = 0AH) (Address (SR4–SR0) = 0BH) Figure 50 shows the various operations under the control of Timing Register 1 is a 8-bit-wide register. Timing Register 0. This register can be read from as well as Figure 51 shows the various operations under the control of written to. Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of TR0 BIT DESCRIPTION the master mode timing signals. Master/Slave Control (TR00) This bit controls whether the ADV7192 is in master or slave mode. TR1 BIT DESCRIPTION Timing Mode Selection (TR01–TR02) HSYNC Width (TR10–TR11) These bits control the timing mode of the ADV7192. These These bits adjust the HSYNC pulsewidth. modes are described in more detail in the Video Timing Descrip- TPCLK = one clock cycle at 27 MHz. tion section of the data sheet. HSYNC to VSYNC Delay (TR13–TR12) BLANK Input Control (TR03) These bits adjust the position of the HSYNC output relative to This bit controls whether the BLANK input is used to accept the VSYNC output. blank signals or whether blank signals are internally generated. TPCLK = one clock cycle at 27 MHz. Note: When this input pin is tied high (to 5 V), the input is dis- abled regardless of the register setting. It, therefore, should be HSYNC to VSYNC Rising Edge Delay (TR14–TR15) tied low (to Ground) to allow control over the I2C register. When the ADV7192 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the VSYNC output Luma Delay (TR04–TR05) rising edge. The luma signal can be delayed by up to 222 ns (or six clock cycles at 27 MHz) using TR04–TR05. For further information TPCLK = one clock cycle at 27 MHz. see Chroma/Luma Delay section. VSYNC Width (TR14–TR15) Min Luminance Value (TR06) When the ADV7192 is configured in Timing Mode 2, these bits This bit is used to control the minimum luma output value adjust the VSYNC pulsewidth. × × by the ADV7192 in 2 Oversampling mode and 4 Oversampling TPCLK = one clock cycle at 27 MHz. mode. When this bit is set to a Logic 1, the luma is limited to HSYNC to Pixel Data Adjust (TR16–TR17) 7IRE below the blank level. When this bit is set to (0), the luma This enables the HSYNC to be adjusted with respect to the value can be as low as the sync bottom level. pixel data. This allows the Cr and Cb components to be swapped.
TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00
TIMING BLANK INPUT MASTER / SLAVE REGISTER RESET CONTROL CONTROL TR03 TR00 TR07 0 ENABLE 0 SLAVE TIMING 1 DISABLE 1 MASTER TIMING
MIN LUMINANCE VALUE LUMA DELAY TIMING MODE SELECTION TR06 TR05 TR04 TR02 TR01 0 LUMA MIN = 0 0 0ns DELAY SYNC BOTTOM 0 1 74ns DELAY 0 0 MODE 0 1 LUMA MIN = 1 0 148ns DELAY 0 1 MODE 1 BLANK –7.5 IRE 1 1 222ns DELAY 1 0 MODE 2 1 1 MODE 3
Figure 50. Timing Register 0 –36– REV. A ADV7192
TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10
HSYNC TO PIXEL HSYNC TO VSYNC HSYNC TO HSYNC WIDTH DATA ADJUST RISING EDGE DELAY VSYNC DELAY (MODE 1 ONLY) TR17 TR16 TR13 TR12 TB TR11 TR10 TA TR15 TR14 T 0 0 0 TPCLK C 0 0 0 TPCLK 0 0 1 TPCLK 011 T PCLK 0 T 014 T PCLK 014 T PCLK 102 T B PCLK 1T+ 32 s 108 TPCLK 1 0 16 TPCLK 113 T B PCLK 1 1 18 TPCLK 1 1 128 TPCLK
VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 TPCLK 014 T PCLK 1 0 16 TPCLK 1 1 128 TPCLK
TIMING MODE 1 (MASTER/PAL) LINE 1 LINE 313 LINE 314
HSYNC TA
TB TC
VSYNC
Figure 51. Timing Register 1
This adjustment is available in both master and slave timing SUBCARRIER PHASE FPH7 FPH6 FPH5 FPH4 FPH3 FPH2 FPH1 FPH0 modes. REGISTER
TPCLK = one clock cycle at 27 MHz. Figure 53. Subcarrier Phase Register
SUBCARRIER FREQUENCY REGISTERS 3–0 CLOSED CAPTIONING EVEN FIELD (FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH) DATA REGISTER 1–0 (CCD15–CCD0) These 8-bit-wide registers are used to set up the Subcarrier Fre- (Address (SR4–SR0) = 11–12H) quency. The value of these registers are calculated by using the These 8-bit-wide registers are used to set up the closed captioning following equation: extended data bytes on Even Fields. Figure 54 shows how the high and low bytes are set up in the registers. 32 ()21– × fSCF Subcarrier Frequency Register = fCLK BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
Example: NTSC Mode, fCLK = 27 MHz, fSCF = 3.5795454 MHz BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0
()232– 1×× 3. 5795454 10 6 Figure 54. Closed Captioning Extended Data Register Subcarrier FrequencyV alue = × 6 27 10 CLOSED CAPTIONING ODD FIELD Subcarrier Register Value = 21F07C16 Hex DATA REGISTER 1–0 (CED15-CED0) (Subaddress (SR4–SR0) = 13–14H) Figure 52 shows how the frequency is set up by the four registers. These 8-bit-wide registers are used to set up the closed captioning data bytes on Odd Fields. Figure 55 shows how the high and low SUBCARRIER FREQUENCY FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 bytes are set up in the registers. REG 3 SUBCARRIER FREQUENCY FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 REG 2 BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8 SUBCARRIER FREQUENCY FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 REG 1 BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0 SUBCARRIER FREQUENCY FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 REG 0 Figure 55. Closed Captioning Data Register
Figure 52. Subcarrier Frequency Registers NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 SUBCARRIER PHASE REGISTER (FPH7–FPH0) (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0) (Address (SR4–SR0) = 10H) (Subaddress (SR4–SR0) = 15–18H) This 8-bit-wide register is used to set up the Subcarrier Phase. These 8-bit-wide registers are used to enable the NTSC pedestal/ ° Each bit represents 1.41 . For normal operation this register is PAL Teletext on a line-by-line basis in the vertical blanking set to 00Hex. interval for both odd and even fields. Figures 56 and 57 show the four control registers. A Logic 1 in any of the bits of these
REV. A –37– ADV7192 registers has the effect of turning the Pedestal OFF on the equiva- TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 lent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext ON on the TTXREQ TTXREQ equivalent line when used in PAL. RISING EDGE CONTROL FALLING EDGE CONTROL TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 0 0 0 0 0 PCLK 0 0 0 0 0 PCLK LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 0 0 0 1 1 PCLK 0 0 0 1 1 PCLK '' '' '' '' '' PCLK '' '' '' '' '' PCLK FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0 1 1 1 0 14 PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK 1 1 1 1 15 PCLK LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8 Figure 58. Teletext Control Register
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00) FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0 (Address (SR4–SR0) = 19H)
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 CGMS_WSS register 0 is an 8-bit-wide register. Figure 59 shows FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8 the operations under control of this register.
Figure 56. Pedestal Control Registers C/W0 BIT DESCRIPTION CGMS Data Bits (C/W00–C/W03) LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 These four data bits are the final four bits of CGMS data out- FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0 put stream. Note it is CGMS data ONLY in these bit positions, LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 i.e., WSS data does not share this location. FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8 CGMS CRC Check Control (C/W04) When this bit is enabled (1), the last six bits of the CGMS data, LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 i.e., the CRC check sequence, is internally calculated by the FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0 ADV7192. If this bit is disabled (0) the CRC values in the reg- LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 ister are output to the CGMS data stream. FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8 CGMS Odd Field Control (C/W05) Figure 57. Teletext Control Registers When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode. TELETEXT REQUEST CONTROL REGISTER TC07 CGMS Even Field Control (C/W06) (TC07–TC00) When this bit is set (1), CGMS is enabled for even fields. Note (Address (SR4–SR0) = 1CH) this is only valid in NTSC mode. Teletext Control Register is an 8-bit-wide register. See Figure 58. WSS Control (C/W07) TTXREQ Falling Edge Control (TC00–TC03) When this bit is set (1), wide screen signalling is enabled. Note These bits control the position of the falling edge of TTXREQ. this is only valid in PAL mode. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. This controls the active window for Teletext data. CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) Increasing this value reduces the amount of Teletext bits below the (Address (SR4–SR0) = 1AH) default of 360. If Bits TC00–TC03 are 00Hex when Bits TC04– CGMS_WSS register 1 is an 8-bit-wide register. Figure 60 shows TC07 are changed then the falling edge of TTREQ will track that the operations under control of this register. of the rising edge (i.e., the time between the falling and rising edge remains constant). C/W1 BIT DESCRIPTION PCLK = clock cycle at 27 MHz. CGMS/WSS Data (C/W10–C/W15) TTXREQ Rising Edge Control (TC04–TC07) These bit locations are shared by CGMS data and WSS data. In These bits control the position of the rising edge of TTXREQ. NTSC mode these bits are CGMS data. In PAL mode these bits It can be programmed from zero clock cycles to a maximum of 15 are WSS data. clock cycles. PCLK = clock cycle at 27 MHz.
C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00
WSS CONTROL CGMS ODD FIELD C/W03 – C/W00 CONTROL C/W07 C/W05 CGMS DATA BITS 0 DISABLE 0 DISABLE 1 ENABLE 1 ENABLE
CGMS EVEN FIELD CGMS CRC CHECK CONTROL CONTROL C/W06 C/W04 0 DISABLE 0 DISABLE 1 ENABLE 1 ENABLE
Figure 59. CGMS_WSS Register 0
–38– REV. A ADV7192
CGMS Data (C/W16–C/W17) COLOR CONTROL REGISTERS 1–2 (CC1–CC2) These bits are CGMS data bits only. (Address (SR4–SR0) = 1EH–1FH) The color control registers are 8-bit-wide registers used to scale
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10 the U and V output levels. Figure 63 shows the operations under control of these registers. C/W17 – C/W16 C/W15 – C/W10
CGMS DATA CGMS/WSS DATA CC17 CC16 CC15 CC14 CC13 CC12 CC11 CC10
Figure 60. CGMS_WSS Register 1 CC17 – CC10 U SCALE VALUE CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20) CC27 CC26 CC25 CC24 CC23 CC22 CC21 CC20 (Address (SR4–SR0) = 1BH) CGMS_WSS Register 2 is an 8-bit-wide register. Figure 61 shows CC27 – CC20 the operations under control of this register. V SCALE VALUE
C/W2 BIT DESCRIPTION Figure 63. Color Control Registers CGMS/WSS Data (C/W20–C/W27) These bit locations are shared by CGMS data and WSS data. In CC1 BIT DESCRIPTION NTSC mode these bits are CGMS data. In PAL mode these bits U Scale Value (CC10–CC17) are WSS data. These eight bits represent the value required to scale the U level from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20 U Scale Value = Scale Factor × 128 C/W27 – C/W20 Example: CGMS/WSS DATA Scale Factor = 1.18 Figure 61. CGMS_WSS Register 2 U Scale Value = 1.18 × 128 = 151.04 U Scale Value = 151 (rounded to the nearest integer) CONTRAST CONTROL REGISTER (CC00–CC07) U Scale Value = 10010111b (Address (SR4–SR0) = 1DH) U Scale Value = 97h The contrast control register is an 8-bit-wide register used to scale the Y output levels. Figure 62 shows the operation under CC2 BIT DESCRIPTION control of this register. V Scale Value (CC20–CC27) Y Scale Value (CC00–CC07) These eight bits represent the value required to scale the V pixel These eight bits represent the value required to scale the Y pixel data from 0.0 to 2.0 of its initial level. The value of these eight data from 0.0 to 1.5 of its initial level. The value of these eight bits is calculated using the following equation: bits is calculated using the following equation: V Scale Value = Scale Factor × 128 Y Scale Value = Scale Factor × 128 Example: Example: Scale Factor = 1.18 Scale Factor = 1.18 V Scale Value = 1.18 × 128 = 151.04 Y Scale Value = 1.18 × 128 = 151.04 V Scale Value = 151 (rounded to the nearest integer) Y Scale Value = 151 (rounded to the nearest integer) V Scale Value = 10010111b Y Scale Value = 10010111b V Scale Value = 97h Y Scale Value = 97h
CC07 CC06 CC05 CC04 CC03 CC02 CC01 CC00
CC07 – CC00
Y SCALE VALUE
Figure 62. Contrast Control Register
REV. A –39– ADV7192
HUE ADJUST CONTROL REGISTER (HCR) BRIGHTNESS CONTROL REGISTER (BCR) (Address (SR5–SR0) = 20H) (Address (SR5–SR0) = 21H) The hue control register is an 8-bit-wide register used to adjust The brightness control register is an 8-bit-wide register which the hue on the composite and chroma outputs. Figure 64 shows allows brightness control. Figure 65 shows the operation under the operation under control of this register. control of this register.
HCR7 HCR6 HCR5 HCR4 HCR3 HCR2 HCR1 HCR0 BCR BIT DESCRIPTION Brightness Value (BCR0–BCR6) HCR7 – HCR0 Seven bits of this 8-bit-wide register are used to control the
HUE ADJUST VALUE brightness level. The brightness is controlled by adding a pro- grammable setup level onto the scaled Y data. This brightness Figure 64. Hue Control Register level can be a positive or negative value. The programmable brightness levels in NTSC, without pedestal, HCR BIT DESCRIPTION and PAL are max 15 IRE and min –7.5 IRE, in NTSC pedestal Hue Adjust Value (HCR0–HCR7) max 22.5 IRE and min 0 IRE. These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during Table IV. Brightness Control Register Value active video with respect to the phase of the subcarrier during the colorburst. The ADV7192 provides a range of ±22.5° incre- Setup Setup Brightness ments of 0.17578125°. For normal operation (zero adjustment), Level in Level in Setup Control this register is set to 80Hex. FFHex and 00Hex represent the NTSC with NTSC No Level in Register upper and lower limit (respectively) of adjustment attainable. Pedestal Pedestal PAL Value ° ° × Hue Adjust [ ] = 0.17578125 (HCRd – 128); for positive Hue 22.5 IRE 15 IRE 15 IRE 1Eh Adjust Value 15 IRE 7.5 IRE 7.5 IRE 0Fh Example: 7.5 IRE 0 IRE 0 IRE 00h 0 IRE –7.5 IRE –7.5 IRE 71h To adjust the hue by 4° write 97h to the Hue Adjust Control Register: NOTE Values in the range from 3Fh to 44h might result in an invalid output signal. (4/0.17578125) + 128 = 151d* = 97h
To adjust the hue by (–4°) write 69h to the Hue Adjust Control Register:
(–4/0.17578125) + 128 = 105d* = 69h *Rounded to the nearest integer.
EXAMPLE 1. Standard: NTSC with Pedestal. To add 20 IRE brightness level write 28h into the Brightness Control Register:
[Brightness Control Register Value]h = [IRE Value ϫ 2.015631]h = [20 ϫ 2.015631]h = [40.31262]h = 28h
2. Standard: PAL. To add –7 IRE brightness level write 72h into the Brightness Control Register:
[|IRE Value| ϫ 2.015631] = [7 ϫ 2.015631] = [14.109417] = 0001110b
[0001110] into two’s complement = 1110010b = 72h
NTSC WITHOUT PEDESTAL +7.5 IRE 100 IRE
0 IRE –7.5 IRE
NO SETUP VALUE POSITIVE SETUP NEGATIVE SETUP ADDED VALUE ADDED VALUE ADDED WRITE TO BRIGHTNESS WRITE TO BRIGHTNESS CONTROL REGISTER: 12h CONTROL REGISTER: 6Eh
BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
BCR7 BCR6 – BCR0 ZERO MUST BE WRITTEN TO BRIGHTNESS VALUE THIS BIT
Figure 65. Brightness Control Register
–40– REV. A ADV7192
SHARPNESS RESPONSE REGISTER (PR) (Address (SR5–SR0) = 22H) DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00 The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to CORING GAIN DATA CORING GAIN BORDER select a desired filter response. Figure 66 shows the operation DNR DNR DNR DNR DNR DNR DNR DNR under control of this register. 07 06 05 04 03 02 01 00 0 0 0 0 0 0 0 0 0001+1/16 0001+1/16 0010+2/16 0010+2/16 PR BIT DESCRIPTION 0011+3/16 0011+3/16 Sharpness Response Value (PR3–PR0) 0100+4/16 0100+4/16 0101+5/16 0101+5/16 These four bits are used to select the desired luma filter response. The 0110+6/16 0110+6/16 0111+7/16 0111+7/16 option of twelve responses is given supporting a gain boost/ 1000+8/16 1000+8/16 attenuation in the range –4 dB to +4 dB. The value 12 (1100) written to these four bits corresponds to a boost of +4 dB while Figure 67. DNR Register 0 in DNR Sharpness Mode the value 0 (0000) corresponds to –4 dB. For normal operation these four bits are set to 6 (0110). Note: Luma Filter Select has DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00 to be set to Extended Mode and Sharpness Filter Control has to be enabled for settings in the Sharpness Control Register to take effect (MR02–04 = 100; MR74 = 1). CORING GAIN DATA CORING GAIN BORDER DNR DNR DNR DNR DNR DNR DNR DNR Reserved (PR4–PR7) 07 06 05 04 03 02 01 00 A Logical 0 must be written to these bits. 0 0 0 0 0 0 0 0 0 0 0001–1/8 0001–1/8 0010–2/8 0010–2/8 0011–3/8 0011–3/8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 0100–4/8 0100–4/8 0101–5/8 0101–5/8 0110–6/8 0110–6/8 PR7 – PR4 PR3 – PR0 0111–7/8 0111–7/8 1000–1 1000–1 ZERO MUST BE SHARPNESS WRITTEN TO RESPONSE VALUE THESE BITS Figure 68. DNR Register 0 in DNR Mode Figure 66. Sharpness Response Register DNR1 BIT DESCRIPTION DNR REGISTERS 2–0 DNR Threshold (DNR10–DNR15) (DNR2–DNR0) These six bits are used to define the threshold value in the range (Address (SR5–SR0) = 23H–25H) of 0 to 63. The range is an absolute value. The Digital Noise Reduction Registers are three 8-bit-wide Border Area (DNR16) register. They are used to control the DNR processing. See In setting DNR16 to a Logic 1 the block transition area can be Digital Noise Register section. defined to consist of four pixels. If this bit is set to a Logic 0 the Coring Gain Border (DNR00–DNR03) border transition area consists of two pixels, where one pixel These four bits are assigned to the gain factor applied to border refers to two clock cycles at 27 MHz. areas. Block Size Control (DNR17) In DNR Mode the range of gain values is 0–1, in increments of This bit is used to select the size of the data blocks to be processed 1/8. This factor is applied to the DNR filter output which lies (see Figure 69). Setting the block size control function to a Logic 1 below the set threshold range. The result is then subtracted defines a 16 × 16 pixel data block, a Logic 0 defines an 8 × 8 pixel from the original signal. data block, where one pixel refers to two clock cycles at 27 MHz. In DNR Sharpness Mode the range of gain values is 0–0.5, in 720 485 PIXELS 2 PIXEL increments of 1/16. This factor is applied to the DNR filter output (NTSC) BORDER DATA which lies above the threshold range. The result is added to the original signal. Coring Gain Data (DNR04–DNR07) 8 8 8 8 These four bits are assigned to the gain factor applied to the PIXEL BLOCK PIXEL BLOCK luma data inside the MPEG pixel block. In DNR Mode the range of gain values is 0–1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted Figure 69. MPEG Block Diagram from the original signal. In DNR Sharpness Mode the range of gain values is 0–0.5, in increments of 1/16. This factor is applied to the DNR filter out- put which lies above the threshold range. The result is added to the original signal. Figures 67 and 68 show the various operations under the control of DNR Register 0.
REV. A –41– ADV7192
DNR17 DNR16 DNR15 DNR14 DNR13 DNR12 DNR11 DNR10
BLOCK SIZE DNR THRESHOLD CONTROL BORDER AREA DNR17 DNR16 DNR DNR DNR DNR DNR DNR 15 14 13 12 11 10 0 8 PIXELS 0 2 PIXELS 1 16 PIXELS 1 4 PIXELS 0 0 0 0 0 0 0 0000011 ••••••• ••••••• ••••••• 11111062 11111163
Figure 70. DNR Register 1
DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22) DNR GAIN CONTROL MODE BLOCK SIZE CONTROL Three bits are assigned to select the filter which is applied to the BORDER AREA BLOCK OFFSET incoming Y data. The signal which lies in the passband of the GAIN selected filter is the signal which will be DNR processed. Figure 71 CORING GAIN DATA shows the filter responses selectable with this control. CORING GAIN BORDER SUBTRACT NOISE SIGNAL PATH SIGNAL IN DNR Mode Control (DNR23) FILTER BLOCK THRESHOLD This bit controls the DNR mode selected. A Logic 0 selects RANGE FROM FILTER OUTPUT DNR mode, a Logic 1 selects DNR Sharpness mode. ORIGINAL < THRESHOLD ? Y DATA SIGNAL DNR works on the principle of defining low amplitude, high- INPUT FILTER OUTPUT frequency signals as probable noise and subtracting this noise > THRESHOLD DNR from the original signal. MAIN SIGNAL PATH OUT In DNR mode, it is possible to subtract a fraction of the signal which lies below the set threshold, assumed to be noise, from DNR GAIN CONTROL the original signal. The threshold is set in DNR Register 1. SHARPNESS BLOCK SIZE CONTROL MODE BORDER AREA When DNR Sharpness mode is enabled it is possible to add a BLOCK OFFSET GAIN fraction of the signal which lies above the set threshold to the CORING GAIN DATA original signal, since this data is assumed to be valid data and CORING GAIN BORDER ADD NOISE SIGNAL PATH not noise. The overall effect being that the signal will be boosted SIGNAL (similar to using Extended SSAF Filter). FILTER BLOCK ABOVE THRESHOLD RANGE FILTER OUTPUT TO 1 > THRESHOLD ? Y DATA ORIGINAL INPUT SIGNAL FILTER D FILTER OUTPUT < THRESHOLD 0.8 DNR MAIN SIGNAL PATH OUT
0.6 FILTER C Figure 72. Block Diagram for DNR Mode and DNR Sharp- ness Mode
0.4 FILTER B Block Offset (DNR24–DNR27)
MAGNITUDE – dB Four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. Consider the coring gain posi- 0.2 FILTER A tions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. 0 012345 6 FREQUENCY – MHz APPLY DATA APPLY BORDER CORING GAIN CORING GAIN Figure 71. Filter Response of Filters Selectable O X X X X X X O O X X X X X X O
OFFSET CAUSED BY O X X X X X X O O X X X X X X O VARIATIONS IN DNR27-DNR24 INPUT TIMING = 01HEX O X X X X X X O O X X X X X X O
Figure 73. DNR27–DNR24 Block Offset Control
–42– REV. A ADV7192
DNR27 DNR26 DNR25 DNR24 DNR23 DNR22 DNR21 DNR20
BLOCK OFFSET CONTROL DNR MODE DNR INPUT SELECT CONTROL CONTROL DNR DNR DNR DNR DNR23 DNR DNR DNR 27 26 25 24 22 21 20 0 DNR MODE 0000 0 PIXEL OFFSET 1 DNR 0 0 1 FILTER A 0001 1 PIXEL OFFSET SHARPNESS 0 1 0 FILTER B 0010 2 PIXEL OFFSET MODE 0 1 1 FILTER C •••• • 1 0 0 FILTER D •••• • •••• • 110113 PIXEL OFFSET 111014 PIXEL OFFSET 111115 PIXEL OFFSET
Figure 74. DNR Register 2
0.5 GAMMA CORRECTION REGISTERS 0–13 (GAMMA y96 = [(80/224) × 224] + 16 = 150* 0.5 CORRECTION 0–13) y128 = [(112/224) × 224] + 16 = 174* (Address (SR5–SR0) = 26H–32H) *Rounded to the nearest integer. The Gamma Correction Registers are fourteen 8-bit wide regis- The above will result in a gamma curve shown below, assuming ter. They are used to program the gamma correction Curves A a ramp signal as an input. and B. Generally gamma correction is applied to compensate for the 300 nonlinear relationship between signal input and brightness level GAMMA CORRECTION BLOCK OUTPUT output (as perceived on the CRT). It can also be applied wher- TO A RAMP INPUT ever nonlinear processing is used. 250 300 Gamma correction uses the function: SIGNAL OUTPUT 200 γ 250 SignalOUT = (SignalIN) 0.5 where 200 γ = gamma power factor 150 150 Gamma correction is performed on the luma data only. The 100 user has the choice to use two different curves, Curve A or Curve B. 100 At any one time only one of these curves can be used. SIGNAL INPUT
GAMMA-CORRECTED AMPLITUDE 50 The response of the curve is programmed at seven predefined 50 locations. In changing the values at these locations the gamma 0 0 50 100 150 200 250 curve can be modified. Between these points linear interpolation LOCATION is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: Figure 75. Signal Input (Ramp) and Signal Output for 32, 64, 96, 128, 160, 192, and 224. Gamma 0.5 Location 0, 16, 240 and 255 are fixed and can not be changed. 300 For the length of 16 to 240 the gamma correction curve has to GAMMA CORRECTION BLOCK OUTPUT be calculated as below: TO A RAMP INPUT FOR VARIOUS GAMMA VALUES y = xγ 250 where SIGNAL OUTPUTS 200 y = gamma corrected output 0.3 x = linear input signal 0.5 γ = gamma power factor 150 To program the gamma correction registers, the seven values for 100 y have to be calculated using the following formula: 1.5 γ SIGNAL INPUT 1.8 yn = [x(n–16) /(240–16) ] × (240–16) + 16 GAMMA-CORRECTED AMPLITUDE 50 where
0 x(n-16) = Value for x along x-axis at points n = 32, 64, 96, 128, 0 50 100 150 200 250 160, 192, or 224 LOCATION yn = Value for y along the y-axis, which has to be written Figure 76. Signal Input (Ramp) and Selectable Gamma into the gamma correction register Output Curves Example: The gamma curves shown above are examples only, any user 0.5 defined curve is acceptable in the range of 16–240. y32 = [(16/224) × 224] + 16 = 76* 0.5 y64 = [(48/224) × 224] + 16 = 120*
REV. A –43– ADV7192
BRIGHTNESS DETECT REGISTER OCR BIT DESCRIPTION (Address (SR5–SR0) = 34H) Reserved (OCR00) The Brightness Detect Register is an 8-bit-wide register used only A Logic 0 must be written to this bit. to read back data in order to monitor the brightness/darkness of CLKOUT Pin Control (OCR01) the incoming video data on a field-by-field basis. The brightness 2 This bit enables the CLKOUT pin when set to 1 and, there- information is read from the I C and based on this information, the fore, outputs a 54 MHz clock generated by the internal PLL. color controls or the gamma correction controls may be adjusted. The PLL and 4× Oversampling have to be enabled for this con- The luma data is monitored in the active video area only. The trol to take effect, (MR61 = 0; MR16 = 1). 2 average brightness I C register is updated on the falling edge of Reserved (OCR02–03) every VSYNC signal. A Logic 0 must be written to this bit. OUTPUT CLOCK REGISTER (OCR 9–0) Reserved (OCR04–06) (Address (SR4–SR0) = 35H) A Logic 1 must be written to these bits. The Output Clock Register is an 8-bit-wide register. Figure 76 Reserved (OCR07) shows the various operations under the control of this register. A Logic 0 must be written to this bit.
OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
OCR07 OCR06 – OCR04 OCR03 – OCR02 OCR00 ZERO MUST BE ONE MUST BE ZERO MUST BE ZERO MUST BE WRITTEN TO WRITTEN TO WRITTEN TO WRITTEN TO THIS BIT THESE BITS THESE BITS THIS BIT
CLKOUT PIN CONTROL OCR01 0 ENSABLED 1 DISABLED
Figure 77. Output Clock Register
–44– REV. A ADV7192
APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7192 is a highly integrated circuit containing both pins on the ADV7192 must have at least one 0.1 µF decou- precision analog and high-speed digital circuitry. It has been pling capacitor to AGND. The same applies to groups of VDD and designed to minimize interference effects on the integrity of the DGND. These capacitors should be placed as close as pos- analog circuitry by the high-speed digital circuitry. It is impera- sible to the device. tive that these same design and layout techniques be applied to It is important to note that while the ADV7192 contains circuitry the system level design such that high-speed, accurate performance to reject power supply noise, this rejection decreases with fre- is achieved. The Recommended Analog Circuit Layout shows quency. If a high frequency switching power supply is used, the the analog interface between the device and monitor. designer should pay close attention to reducing power supply The layout should be optimized for lowest noise on the ADV7192 noise and consider using a three-terminal voltage regulator for power and ground lines by shielding the digital inputs and pro- supplying power to the analog power plane. viding good decoupling. The lead length between groups of V AA Digital Signal Interconnect and AGND and V and DGND pins should by minimized so DD The digital inputs to the ADV7192 should be isolated as much as as to minimize inductive ringing. possible from the analog outputs and other analog circuitry. Also, Ground Planes these input signals should not overlay the analog power plane. The ground plane should encompass all ADV7192 ground pins, Due to the high clock rates involved, long clock lines to the voltage reference circuitry, power supply bypass circuitry for ADV7192 should be avoided to reduce noise pickup. the ADV7192, the analog output traces, and all the digital signal traces leading up to the ADV7192. This should be as substantial as Any active termination resistors for the digital inputs should be possible to maximize heat spreading and power dissipation on connected to the regular PCB power plane (VCC), and not the the board. analog power plane. Power Planes Analog Signal Interconnect The ADV7192 and any associated analog circuitry should have its The ADV7192 should be located as close as possible to the output own power plane, referred to as the analog power plane (VAA). This connectors to minimize noise pickup and reflections due to power plane should be connected to the regular PCB power plane impedance mismatch. (VCC) at a single point through a ferrite bead. This bead should The video output signals should overlay the ground plane, and be located within three inches of the ADV7192. not the analog power plane, to maximize the high frequency power The metallization gap separating device power plane and board supply rejection. power plane should be as narrow as possible to minimize the Digital inputs, especially pixel data inputs and clocking signals obstruction to the flow of heat from the device into the gen- should never overlay any of the analog signal circuitry and should eral board. be kept as far away as possible. The PCB power plane should provide power to all digital logic For best performance, the outputs should each have a 300 Ω load on the PC board, and the analog power plane should provide resistor connected to AGND. These resistors should be placed power to all ADV7192 power pins and voltage reference circuitry. as close as possible to the ADV7192 so as to minimize reflections. Plane-to-plane noise coupling can be reduced by ensuring that The ADV7192 should have no inputs left floating. Any inputs portions of the regular PCB power and ground planes do not that are not required should be tied to ground. overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common-mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA
REV. A –45– ADV7192
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP
5V (VAA) 10nF 0.1 F 5V (VAA) 5V (VAA) 5V (VAA) 10nF 0.1 F 0.1 F 0.1 F 53, 79, 68, 48, 38 34, 21
COMP2 COMP1 VAA VDD V REF DAC A 300 Cb0 – Cb9
DAC B Cr0 – Cr9 ADV7192 300 Y0/P8 – Y7/P15 Y8 – Y9 DAC C UNUSED 300 INPUTS P7 – P0 SHOULD BE GROUNDED DAC D CSO_HSO 300 VSO/TTX/CLAMP DAC E PAL_NTSC 300 SCRESET/RTC/TR DAC F HSYNC 5V (VAA) 5V (VAA) 5V (V ) 300 AA VSYNC 5k 5k 100 4.7k BLANK SCL RESET 100 MPU BUS 4.7 F SDATA 6.3V TTXREQ RSET2 CLKIN 1.2k 27MHz CLOCK R (SAME CLOCK AS SET1 ALSB AGND DGND 1.2k USED BY MPEG2 5V (V ) DECODER) AA 52, 49, 80, 69, 43, 4.7k 35 33, 22
Figure 78. Recommended Analog Circuit Layout
–46– REV. A ADV7192
APPENDIX 2 CLOSED CAPTIONING
The ADV7192 supports closed captioning conforming to the FCC Code of Federal Regulations (CFR) 47 Section 15.119 standard television synchronizing waveform for color transmission. and EIA608 describe the closed captioning information for Lines Closed captioning is transmitted during the blanked active line 21 and 284. time of Line 21 of the odd fields and Line 284 of even fields. The ADV7192 uses a single buffering method. This means that Closed captioning consists of a seven-cycle sinusoidal burst that the closed captioning buffer is only one byte deep, therefore, there is frequency and phase locked to the caption data. After the clock will be no frame delay in outputting the closed captioning data run-in signal, the blanking level is held for two data bits and is unlike other two byte deep buffering systems. The data must followed by a Logic Level 1 start bit. Sixteen bits of data follow be loaded one line before (Line 20 or Line 283) it is outputted the start bit. These consist of two eight-bit bytes, seven data on Line 21 and Line 284. A typical implementation of this method bits, and one odd parity bit. The data for these bytes is stored is to use VSYNC to interrupt a microprocessor, which in turn will in Closed Captioning Data Registers 0 and 1. load the new data (two bytes) every field. If no new data is required The ADV7192 also supports the extended closed captioning for transmission, 0s must be inserted in both data registers, this operation which is active during even fields and is encoded on is called NULLING. It is also important to load control codes all Scan Line 284. The data for this operation is stored in Closed of which are double bytes on Line 21 or a TV will not recognize Captioning Extended Data Registers 0 and 1. them. If there is a message like Hello World which has an odd number of characters, it is important to pad it out to even in order to get All clock run-in signals and timing to support Closed Captioning end of caption 2-byte control code to land in the same field. on Lines 21 and 284 are generated automatically by the ADV7192 All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled.
10.5 0.25 s 12.91 s 7 CYCLES TWO 7-BIT + PARITY OF 0.5035 MHz ASCII CHARACTERS (CLOCK RUN-IN) (DATA)
S P P T A A A D0–D6 R D0–D6 R 50 IRE R I I T T T Y Y
BYTE 0 BYTE 1
40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s 33.764 s
Figure 79. Closed Captioning Waveform (NTSC)
REV. A –47– ADV7192
APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7192 supports Copy Generation Management System Function of CGMS Bits (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits Word 0 – 6 Bits C/W05 and C/W06 control whether or not CGMS data is outputed Word 1 – 4 Bits on ODD and EVEN fields. CGMS data can only be transmitted Word 2 – 6 Bits when the ADV7192 is configured in NTSC mode. The CGMS CRC – 6 Bits CRC Polynomial = X6 + X + 1 (Preset to data is 20 bits long, the function of each of these bits is as shown 111111) below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 79. These bits are outputed from the configuration registers in the WORD 0 1 0 following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, B1 Aspect Ratio 16:9 4:3 C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, B2 Display Format Letterbox Normal C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, B3 Undefined C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, WORD 0 C/W27 = C7. If the bit C/W04 is set to a Logic 1, the last six B4, B5, B6 Identification Information About Video and bits C19–C14 which comprise the 6-bit CRC check sequence Other Signals (e.g., Audio) are calculated automatically on the ADV7192 based on the WORD 1 lower 14 bits (C0–C13) of the data in the data registers and B7, B8, B9, Identification Signal Incidental to Word 0 output with the remaining 14-bits to form the complete 20-bits of the CGMS data. The calculation of the CRC sequence is B10 based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic 0 then all 20-bits (C0–C19) WORD 2 are output directly from the CGMS registers (no CRC calcu- B11, B12, Identification Signal and Information lated, must be calculated by the user). B13, B14 Incidental to Word 0
100 IRE REF CRC SEQUENCE 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
49.1 s 0.5 s –40 IRE 11.2 s
2.235 s 20ns
Figure 80. CGMS Waveform Diagram
–48– REV. A ADV7192
APPENDIX 4 WIDE SCREEN SIGNALING
The ADV7192 supports Wide Screen Signaling (WSS) conforming B4 to the standard. WSS data is transmitted on Line 23. WSS data 0 Camera Mode can only be transmitted when the ADV7192 is configured in PAL 1 Film Mode mode. The WSS data is 14-bits long, the function of each of these B5 bits is as shown below. The WSS data is preceded by a run-in 0 Standard Coding sequence and a Start Code, see Figure 80. The bits are output 1 Motion Adaptive Color Plus from the configuration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, B6 C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, 0 No Helper C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, 1 Modulated Helper C/W15 = W13. If the bit C/W07 is set to a Logic 1, it enables B7 RESERVED the WSS data to be transmitted on Line 23. The latter portion of B9 B10 Line 23 (42.5 µs from the falling edge of HSYNC) is available for 0 0 No Open Subtitles the insertion of video. 1 0 Subtitles in Active Image Area Function of CGMS Bits 0 1 Subtitles Out of Active Image Area Bit 0–Bit 2 Aspect Ratio/Format/Position 1 1 RESERVED Bit 3 Is Odd Parity Check of Bit 0–Bit 2 B11 Aspect Format Position 0 No Surround Sound Information B0, B1, B2, B3 Ratio Format Position 1 Surround Sound Mode 0 0 0 1 4:3 Full Format Nonapplicable B12 RESERVED 1 0 0 0 14:9 Letterbox Center 0 1 0 0 14:9 Letterbox Top B13 RESERVED 1 1 0 1 16:9 Letterbox Center 0 0 1 0 16:9 Letterbox Top 1 0 1 1 >16:9 Letterbox Center 0 1 1 1 14:9 Full Format Center 1 1 1 0 16:9 Nonapplicable Nonapplicable
500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN START ACTIVE SEQUENCE CODE VIDEO
11.0 s 38.4 s 42.5 s
Figure 81. WSS Waveform Diagram
REV. A –49– ADV7192
APPENDIX 5 TELETEXT INSERTION
Time, tPD, is the time needed by the ADV7192 to interpolate Teletext Protocol input data on TTX and insert it onto the CVBS or Y outputs, The relationship between the TTX bit clock (6.9375 MHz) and such that it appears tSYNTTXOUT = 10.2 µs after the leading edge the system CLOCK (27 MHz) for 50 Hz is given as follows: of the horizontal signal. Time TTXDEL is the pipeline delay time (27 MHz/4) = 6.75 MHz by the source that is gated by the TTXREQ signal in order to × 6 × 6 deliver TTX data. (6.9375 10 /6.75 10 = 1.027777 With the programmability that is offered with TTXREQ signal Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit on the Rising/Falling edges, the TTX data is always inserted at has a width of almost four clock cycles. The ADV7192 uses an the correct position of 10.2 µs after the leading edge of Horizontal internal sequencer and variable phase interpolation filter to mini- Sync pulse, thus this enables a source interface with variable mize the phase jitter and thus generate a bandlimited signal pipeline delays. which can be output on the CVBS and Y outputs. The width of the TTXREQ signal must always be maintained At the TTX input the bit duration scheme repeats after every such that it allows the insertion of 360 (in order to comply with 37 TTX bits or 144 clock cycles. The protocol requires that the Teletext Standard PAL-WST) teletext bits at a text data rate TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to 0. other bits by four clock cycles. After 37 TTX bits, the next bits The insertion window is not open if the Teletext Enable bit with three clock cycles are Bits 47, 56, 65, and 74. This scheme (MR33) is set to 0. holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.
45 BYTES (360 BITS) – PAL TELETEXT VBI LINE ADDRESS & DATA
RUN-IN CLOCK
Figure 82. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
tPD
HSYNC tPD
10.2 s
TTXDATA
TTXDEL
TTXREQ PROGRAMMABLE PULSE EDGES TTXST tSYNTTXOUT = 10.2 s tPD = PIPELINE DELAY THROUGH ADV7192 TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES]) Figure 83. Teletext Functionality Diagram
–50– REV. A ADV7192
APPENDIX 6 OPTIONAL OUTPUT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and is not required if the outputs of the ADV7192 are connected to RGB outputs of the ADV7192, the following filter in Figure 84 most analog monitors or TVs, however, if the output signals are can be used in 2× Oversampling Mode. In 4× Oversampling applied to a system where sampling is used, (e.g., Digital TVs) Mode the filter in Figure 86 is recommended. The plot of the fil- then a filter is required to prevent aliasing. ter characteristics are shown in Figures 85 and 87. An output filter
22 H 22 H 6.8 H 22 H 10 H FILTER I/P FILTER O/P FILTER I/P FILTER O/P 600 22pF68pF 56pF 600 600 27pF 68pF 600
Figure 84. Output Filter for 2× Oversampling Mode Figure 86. Output Filter for 4× Oversampling Mode
0 0 –7 –10 –14
–20 –21
–28 –30 –35
–40 –42 MAGNITUDE – dB MAGNITUDE – dB –49 –50 –56 –60 –63
–70 –70 100k 1.0M 10M 100M 100k 1.0M 10M 100M FREQUENCY – Hz FREQUENCY – Hz × Figure 85. Output Filter Plot for 2× Oversampling Filter Figure 87. Output Filter Plot for 4 Oversampling Filter
2 FILTER 0 REQUIREMENTS
4 FILTER REQUIREMENTS dB
–30 6.75 13.5 27.0 40.5 54.0 FREQUENCY – MHz
Figure 88. Output Filter Requirements in 4× Oversampling Mode
REV. A –51– ADV7192
APPENDIX 7 DAC BUFFERING
External buffering is needed on the ADV7192 DAC outputs.
The configuration in Figure 89 is recommended. +VCC
When calculating absolute output full-scale current and voltage 4 5 use the following equations: AD8051 1 OUTPUT TO INPUT/ TV MONITOR 3 V = I × R OPTIONAL OUT OUT LOAD 2 FILTER O/P I = (V × K)/R OUT REF SET –VCC
K = 4.2146 constant, VREF = 1.235 V Figure 90. Recommended DAC Output Buffer Using an
VAA Op Amp
ADV7192
VREF DAC A OUTPUT CVBS BUFFER
RSET1 DAC B OUTPUT 1.2k BUFFER LUMA
OUTPUT DAC C BUFFER CHROMA PIXEL DIGITAL PORT CORE OUTPUT DAC D BUFFER G
R OUTPUT SET2 DAC E BUFFER B 1.2k DAC F OUTPUT R BUFFER
Figure 89. Output DAC Buffering Configuration
–52– REV. A ADV7192
APPENDIX 8 RECOMMENDED REGISTER VALUES The ADV7192 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards.
NTSC (FSC = 3.5795454 MHz) PAL B, D, G, H, I (FSC = 4.43361875 MHz) Address Data Address Data 00Hex Mode Register 0 10Hex 00Hex Mode Register 0 11Hex 01Hex Mode Register 1 3FHex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 16Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 7CHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 F0Hex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 21Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 23Hex DNR0 44Hex 24Hex DNR 1 20Hex 24Hex DNR1 20Hex 25Hex DNR 2 00Hex 25Hex DNR2 00Hex 35Hex Output Clock Register 70Hex 35Hex Output Clock Register 70Hex
REV. A –53– ADV7192
PAL N (FSC = 4.43361875 MHz) PAL 60 (FSC = 4.43361875 MHz) Address Data Address Data 00Hex Mode Register 0 13Hex 00Hex Mode Register 0 12Hex 01Hex Mode Register 1 3FHex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 CBHex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 8AHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 09Hex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 2AHex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 13Hex Closed Captioning Register 0 00Hex 4Hex Closed Captioning Register 1 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1CHex Teletext Control Register 00Hex DHex Contrast Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex 35Hex Output Clock Register 70Hex
–54– REV. A ADV7192
PAL M (FSC = 3.57561149 MHz) Address Data Address Data 00Hex Mode Register 0 12Hex 13Hex Closed Captioning Register 0 00Hex 01Hex Mode Register 1 3FHex 14Hex Closed Captioning Register 1 00Hex 02Hex Mode Register 2 62Hex 15Hex Pedestal Control Register 0 00Hex 03Hex Mode Register 3 00Hex 16Hex Pedestal Control Register 1 00Hex 04Hex Mode Register 4 00Hex 17Hex Pedestal Control Register 2 00Hex 05Hex Mode Register 5 00Hex 18Hex Pedestal Control Register 3 00Hex 06Hex Mode Register 6 00Hex 19Hex CGMS_WSS Reg 0 00Hex 07Hex Mode Register 7 00Hex 1AHex CGMS_WSS Reg 1 00Hex 08Hex Mode Register 8 04Hex 1BHex CGMS_WSS Reg 2 00Hex 09Hex Mode Register 9 00Hex 1CHex Teletext Control Register 00Hex 0AHex Timing Register 0 08Hex 1DHex Contrast Control Register 00Hex 0BHex Timing Register 1 00Hex 1EHex Color Control Register 1 00Hex 0CHex Subcarrier Frequency Register 0 A3Hex 1FHex Color Control Register 2 00Hex 0DHex Subcarrier Frequency Register 1 EFHex 20Hex Hue Control Register 00Hex EHex Subcarrier Frequency Register 2 E6Hex 21Hex Brightness Control Register 00Hex 0FHex Subcarrier Frequency Register 3 21Hex 22Hex Sharpness Response Register 00Hex 10Hex Subcarrier Phase Register 00Hex 23Hex DNR 0 44Hex 11Hex Closed Captioning Ext Register 0 00Hex 24Hex DNR 1 20Hex 12Hex Closed Captioning Ext Register 1 00Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex
REV. A –55– ADV7192
POWER-ON RESET REGISTER VALUES
POWER-ON RESET REG VALUES POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) (PAL_NTSC = 1, PAL Selected) Address Data Address Data 00Hex Mode Register 0 00Hex 00Hex Mode Register 0 01Hex 01Hex Mode Register 1 07Hex 01Hex Mode Register 1 07Hex 02Hex Mode Register 2 08Hex 02Hex Mode Register 2 08Hex 03Hex Mode Register 3 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 00Hex 08Hex Mode Register 8 00Hex 09Hex Mode Register 9 00Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 16Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 7CHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 F0Hex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 21Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 00Hex 23Hex DNR 0 00Hex 24Hex DNR 1 00Hex 24Hex DNR 1 00Hex 25Hex DNR 2 00Hex 25Hex DNR 2 00Hex 26Hex Gamma 0 xxHex 26Hex Gamma 0 xxHex 27Hex Gamma 1 xxHex 27Hex Gamma 1 xxHex 28Hex Gamma 2 xxHex 28Hex Gamma 2 xxHex 29Hex Gamma 3 xxHex 29Hex Gamma 3 xxHex 2AHex Gamma 4 xxHex 2AHex Gamma 4 xxHex 2BHex Gamma 5 xxHex 2BHex Gamma 5 xxHex 2CHex Gamma 6 xxHex 2CHex Gamma 6 xxHex 2DHex Gamma 7 xxHex 2DHex Gamma 7 xxHex 2EHex Gamma 8 xxHex 2EHex Gamma 8 xxHex 2FHex Gamma 9 xxHex 2FHex Gamma 9 xxHex 30Hex Gamma 10 xxHex 30Hex Gamma 10 xxHex 31Hex Gamma 11 xxHex 31Hex Gamma 11 xxHex 32Hex Gamma 12 xxHex 32Hex Gamma 12 xxHex 33Hex Gamma 13 xxHex 33Hex Gamma 13 xxHex 34Hex Brightness Detect Register xxHex 34Hex Brightness Detect Register xxHex 35Hex Output Clock Register 72Hex 35Hex Output Clock Register 72Hex
–56– REV. A ADV7192
APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE PEAK COMPOSITE 1268.1mV
100 IRE REF WHITE 1048.4mV
714.2mV 7.5 IRE BLACK LEVEL 387.6mV 0 IRE BLANK LEVEL 334.2mV
–40 IRE SYNC LEVEL 48.3mV Figure 91. NTSC Composite Video Levels
100 IRE REF WHITE 1048.4mV
714.2mV
7.5 IRE BLACK LEVEL 387.6mV 0 IRE BLANK LEVEL 334.2mV
–40 IRE SYNC LEVEL 48.3mV Figure 92. NTSC Luma Video Levels
963.8mV PEAK CHROMA
629.7mV (p-p) 286mV (p-p) 650mV BLANK/BLACK LEVEL
PEAK CHROMA 335.2mV
0mV Figure 93. NTSC Chroma Video Levels
100 IRE REF WHITE 1052.2mV
720.8mV
7.5 IRE BLACK LEVEL 387.5mV 0 IRE BLANK LEVEL 331.4mV
–40 IRE SYNC LEVEL 45.9mV Figure 94. NTSC RGB Video Levels
REV. A –57– ADV7192
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE PEAK COMPOSITE 1289.8mV
100 IRE REF WHITE 1052.2mV
714.2mV
0 IRE BLANK/BLACK LEVEL 338mV
–40 IRE SYNC LEVEL 52.1mV Figure 95. NTSC Composite Video Levels
100 IRE REF WHITE 1052.2mV
714.2mV
0 IRE BLANK/BLACK LEVEL 338mV
–40 IRE SYNC LEVEL 52.1mV Figure 96. NTSC Luma Video Levels
978mV PEAK CHROMA
694.9mV (p-p) 307mV (p-p) 650mV BLANK/BLACK LEVEL
283mV PEAK CHROMA
0mV Figure 97. NTSC Chroma Video Levels
100 IRE REF WHITE 1052.2mV
715.7mV
0 IRE BLANK/BLACK LEVEL 336.5mV
–40 IRE SYNC LEVEL 51mV Figure 98. NTSC RGB Video Levels
–58– REV. A ADV7192
PAL WAVEFORMS
1284.2mV PEAK COMPOSITE
1047.1mV REF WHITE
696.4mV
350.7mV BLANK/BLACK LEVEL
50.8mV SYNC LEVEL Figure 99. PAL Composite Video Levels
1047mV REF WHITE
696.4mV
350.7mV BLANK/BLACK LEVEL
50.8mV SYNC LEVEL Figure 100. PAL Luma Video Levels
990mV PEAK CHROMA
672mV (p-p) 300mV (p-p) 650mV BLANK/BLACK LEVEL
318mV PEAK CHROMA
0mV Figure 101. PAL Chroma Video Levels
1050.2mV REF WHITE
698.4mV
351.8mV BLANK/BLACK LEVEL
51mV SYNC LEVEL Figure 102. PAL RGB Video Levels
REV. A –59– ADV7192
VIDEO MEASUREMENT PLOTS
COLOR BAR (NTSC) WFM FCC COLOR BAR FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE)
99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7
100
50
0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE LEVEL (IRE)
0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0 100
50
0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE PHASE (DEGREE) 167.3 283.8 240.9 60.80 103.6 347.1 400
200
0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
AVERAGE 32 32 Figure 103. NTSC Color Bar Measurement
COLOR BAR (PAL) WFM FCC COLOR BAR FIELD = 1 LINE = 21 LUMINANCE LEVEL (mV)
1000 695.7 464.8 366.6 305.7 217.3 156.4 61.2 –0.4
500
0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE LEVEL (mV)
1000 0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0
500
0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE PHASE (DEGREE) 166.7 283.3 240.4 60.4 103.2 346.7 400 300 200 100 0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
AVERAGE 32 32 Figure 104. PAL Color Bar Measurement –60– REV. A ADV7192
DG DP (NTSC) WFM MOD 5 STEP DG DP (PAL) WFM MOD 5 STEP FIELD = 1, LINE = 21 LINE = 570 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.32, p-p/MAX = 0.32 0.00 0.21 0.02 0.07 0.27 0.08 0.00 0.30 0.15 0.24 0.32 0.26 2.5 2.5
1.5 1.5
0.5 0.5
–0.5 –0.5
–1.5 –1.5
–2.5 –2.5 1st 2nd 3rd 4th 5th 6th 1st 2nd 3rd 4th 5th 6th
DIFFERENTIAL PHASE (DEGREE) MIN = 0.00, MAX = 0.20, p-p = 0.20 DIFFERENTIAL PHASE (DEGREE) MIN = 0.00, MAX = 0.16, p-p = 0.16 0.00 0.10 0.12 0.15 0.13 0.10 0.00 0.09 0.13 0.16 0.12 0.14 2.5 2.5
1.5 1.5
0.5 0.5
–0.5 –0.5
–1.5 –1.5
–2.5 –2.5 1st 2nd 3rd 4th 5th 6th 1st 2nd 3rd 4th 5th 6th AVERAGE 32 32 AVERAGE 32 32 Figure 105. NTSC DG DP Measurement Figure 107. PAL DG DP Measurement
LUMINANCE NONLINEARITY (NTSC) WFM MOD 5 STEP LUMINANCE NONLINEARITY (PAL) WFM MOD 5 STEP FIELD = 2, LINE = 77 LINE = 570 LUMINANCE NONLINEARITY (PERCENT) p-p = 0.4 LUMINANCE NONLINEARITY (PERCENT) p-p = 0.8 99.9 99.9 99.6 100.0 99.9 111 113 99.6 99.9 100.0 99.6 99.9
109 111
107 109
105 107 103 105 101 103 99 101 97 99 95 97 93 95 91 93 89 91 1st 2nd 3rd 4th 5th st nd rd th th AVERAGE 32 32 1 2 3 4 5 AVERAGE 32 32 Figure 106. NTSC Luminance Nonlinearity Figure 108. PAL Luminance Nonlinearity
REV. A –61– ADV7192
CHROMINANCE NONLINEARITY(NTSC) WFM NTSC–7 COMBINATION CHROMINANCE NONLINEARITY(PAL) WFM MOD 3 STEP FIELD = 2, LINE = 217 LINE = 572 CHROMINANCE AMPLITUDE ERROR (PERCENT) REF = 40IRE PACKET CHROMINANCE AMPLITUDE ERROR (PERCENT) REF = 420mV PACKET 0.5 0.0 –0.3 0.6 0.0 –0.4 10 10
0 0
–10 –10
20IRE 40IRE 80IRE 140mV 420mV 700mV
CHROMINANCE PHASE ERROR (DEGREE) REF = 40IRE PACKET CHROMINANCE PHASE ERROR (DEGREE) REF = 420mV PACKET –0.0 0.0 0.0 –0.3 0.0 –0.3 5
0 0
–5 –5
20IRE 40IRE 80IRE 140mV 420mV 700mV
CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714 mV) CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 700mV) 0.0 0.1 0.1 0.0 0.0 0.1 0.2 0.1 0.2
0.0 0.0 –0.1 –0.2 –0.2 20IRE 40IRE 80IRE 140mV 420mV 700mV AVERAGE 32 32 AVERAGE 32 32 Figure 109. NTSC Chrominance Nonlinearity Figure 111. PAL Chrominance Nonlinearity
CHROMINANCE AM/PM (NTSC) WFM RED FIELD CHROMINANCE AM/PM (PAL) WFM APPROPRIATE FIELD = 2, LINE = 217 LINE = 572 BANDWIDTH 10kHz TO 100kHz BANDWIDTH 10kHz TO 100kHz
AM NOISE –86.5dB RMS AM NOISE –84.2dB RMS
–95 –90 –85 –80 –75 –70 –65 –60 –95 –90 –85 –80 –75 –70 –65 –60 dB RMS dB RMS
PM NOISE –82.7dB RMS PM NOISE –82.7dB RMS
–95 –90 –85 –80 –75 –70 –65 –60 –95 –90 –85 –80 –75 –70 –65 –60 dB RMS dB RMS (0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) (0dB = 700mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) Figure 110. NTSC Chrominance AM/PM Figure 112. PAL Chrominance AM/PM
–62– REV. A ADV7192
NOISE SPECTRUM (NTSC) WFM PEDESTAL NOISE SPECTRUM (PAL) WFM PEDESTAL FIELD = 2, LINE = 223 LINE = 511 AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –79.7dB RMS AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –79.1dB RMS BANDWIDTH 10kHz TO FULL BANDWIDTH 10kHz TO FULL
20 0
0 –20
–20 –40
–40
–60 –60
–80 –80
–100 –100 123456 123 4576 MHz MHz Figure 113. NTSC Noise Spectrum: Pedestal Figure 115. PAL Noise Spectrum: Pedestal
NOISE SPECTRUM (NTSC) WFM RAMP NOISE SPECTRUM (PAL) WFM RAMP FIELD = 2, LINE = 217 LINE = 572 AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –63.1dB RMS AMPLITUDE (0dB = 700mV p–p) NOISE LEVEL = –62.3dB RMS BANDWIDTH 100kHz TO FULL (TILT NULL) BANDWIDTH 100kHz TO FULL (TILT NULL)
0 0
–10 –10
–20 –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100 123456 123 45 6 7 MHz MHz Figure 114. NTSC Noise Spectrum: Ramp Figure 116. PAL Noise Spectrum: Ramp
REV. A –63– ADV7192
UV WAVEFORMS WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 505mV 505mV 423mV 334mV
171mV BETACAM LEVEL BETACAM LEVEL 82mV
0mV 0mV 0mV 0mV
–82mV 171mV
334mV
–423mV 505mV –505mV
Figure 117. NTSC 100% Color Bars No Pedestal U Levels Figure 120. NTSC 100% Color Bars No Pedestal V Levels WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 467mV 467mV 391mV 309mV
158mV BETACAM LEVEL BETACAM LEVEL 76mV
0mV 0mV 0mV 0mV
–76mV –158mV
–309mV
–391mV –467mV –467mV
Figure 118. NTSC 100% Color Bars with Pedestal U Levels Figure 121. NTSC 100% Color Bars with Pedestal V WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 350mV 350mV 293mV 232mV
SMPTE LEVEL 118mV SMPTE LEVEL 57mV
0mV 0mV 0mV 0mV
–57mV –118mV
–232mV –293mV –350mV –350mV
Figure 119. PAL 100% Color Bars U Levels Figure 122. PAL 100% Color Bars V Levels
–64– REV. A ADV7192
OUTPUT WAVEFORMS
0.6
0.4
VOLTS 0.2
0.0
0.2 L608
0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 0.00 dB APL = 39.1% PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2 3 4
Figure 123. 100/0/75/0 PAL Color Bars
0.5 VOLTS
0.0
L575
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 MICROSECONDS NO BRUCH SIGNAL APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1
Figure 124. 100/0/75/0 PAL Color Bars Luminance
REV. A –65– ADV7192
0.5
VOLTS 0.0
–0.5 L575
10.020.0 30.0 40.0 50.0 60.0 MICROSECONDS NO BRUCH SIGNAL APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1
Figure 125. 100/0/75/0 PAL Color Bars Chrominance
100.0
0.5
50.0 VOLTS IRE:FLT
0.0 0.0
F1 –50.0 L76
0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS APL = 44.6% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2
Figure 126. 100/7.5/75/7.5 NTSC Color Bars
–66– REV. A ADV7192
100.0
0.6
0.4 50.0
VOLTS 0.2 IRE:FLT
0.0 0.0
–0.2 F2 L238
10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2
Figure 127. 100/7.5/75/7.5 NTSC Color Bars Luminance
0.4 50.0
0.2
VOLTS 0.0 IRE:FLT
–0.2
–50.0 –0.4
F1 L76
0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2
Figure 128. 100/7.5/75/7.5 NTSC Color Bars Chrominance
REV. A –67– ADV7192
APPENDIX 10 VECTOR PLOTS
V APL = 39.6% SYSTEM LINE L608 ANGLE (DEG) 0.0 cy GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND –V R g M g
75%
100% YI b
U
yl B
G Cy m g
r
SOUND IN SYNC OFF Figure 129. PAL Vector Plot
R-Y APL = 45.1% SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB cy I 525 LINE NTSC BURST FROM SOURCE
R M g Q
YI b 100% B-Y
75% B
G Cy –Q
–I
SETUP 7.5% Figure 130. NTSC Vector Plot –68– REV. A ADV7192
OUTLINE DIMENSIONS Dimensions shown in inches and (mm).
80-Lead LQFP (ST-80)
0.640 (16.25) SQ 0.620 (15.75) 0.063 (1.60) 0.553 (14.05) MAX SQ 0.549 (13.95) 0.030 (0.75) 80 61 0.020 (0.50) 1 60 SEATING PLANE
0.486 TOP VIEW (12.35) C00229–0–12/00 (rev. A) (PINS DOWN) TYP SQ
0.004 (0.10) MAX 20 41 40 0.006 (0.15) 21 0.002 (0.05) 0.029 (0.73) 0.014 (0.35) 0.057 (1.45) 0.022 (0.57) 0.010 (0.25) 0.053 (1.35)
PRINTED IN U.S.A.
REV. A –69–