14.52 Rev 1.0 At Sonnet, we've been developing 3D planar high frequency EM software since 1983, and our software has earned a solid reputa- tion as the world's most accurate commercial planar EM analysis package for single and multi-layer planar circuits, packages and antennas. Sonnet Software Inc., founded by Dr. James C. Rautio, is a pri- vate company, entirely dedicated to the development of com- mercial EM software. We take great pride in providing quality technical support for our products with timely response--which we believe to be very important for high-end technical software products. Sonnet is based in Syracuse, NY, USA with representatives across the globe. DXF TRANSLATOR
Published: May 2018
Release 16
Sonnet Software, Inc. 126 N. Salina Street Syracuse, NY 13202 Phone: (315) 453-3096 Fax: (315) 451-1694
www.sonnetsoftware.com
Copyright 1989,1991,1993, 1995-2018 Sonnet Software, Inc. All Rights Reserved Registration numbers: TX 2-723-907, TX 2-760-739
Rev 16.56 Copyright Notice
Reproduction of this document in whole or in part, without the prior express written authorization of Sonnet Software, Inc. is prohibited. Documentation and all authorized copies of documentation must remain solely in the possession of the customer at all times, and must remain at the software designated site. The customer shall not, under any circumstances, provide the documentation to any third party without prior written approval from Sonnet Software, Inc. This publication is subject to change at any time and without notice. Any suggestions for improvements in this publication or in the software it describes are welcome.
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The program names, xgeom, emstatus, emvu, patvu, dxfgeo, ebridge, emgraph, gds, cvbridge, emserver, emclient, sonntcds, and sonntawr, sonntawr64, Blink, Co-calibrated, Lite, LitePlus, Level2 Basic, Level2 Silver, and Level3 Gold are trademarks of Sonnet Software, Inc. Sonnet®, em®, and emCluster® are registered trademarks of Sonnet Software, Inc. Windows XP, Windows Vista, Windows 7, Windows 8, Windows 10 and Internet Explorer® are U.S. registered trademarks of Microsoft Corporation. AutoCAD and Drawing Interchange file (DXF) are trademarks of Auto Desk, Inc. Cadence® and Virtuoso® are registered trademarks of Cadence Design Systems, Inc. GLOBALFOUNDRIES® is a registered trademark of GlobalFoundries, Inc. Agilent, ADS, and Touchstone are trademarks of Keysight Technologies. NI AWR and Microwave Office are registered trademarks and EM Socket is a trademark of National Instruments, Inc. HSPICE is a registered trademark of Synopsys, Inc. GDSII is a trademark of Calma Company. Flexera Software, Flexlm, FlexNet, InstallShield, are trademarks of Flexera Software, Inc. and/or InstallShield Co.Inc. in the United States of America and/or other countries. OSF/Motif is a trademark of the Open Software Foundation. X Window System is a trademark of The Open Group Linux® is a registered trademark of Linus Torvalds. Red Hat® is a registered trademark of Red Hat, Inc. SUSE®, openSUSE® and SLES® are registered trademarks of SUSE LLC. OpenGL® is a registered trademark owned by Silicon Graphics, Inc. MATLAB is a registered trademark of The MathWorks, Inc. in the United States and/or other countries. Acrobat® is a registered trademark of Adobe Systems Incorporated. Xpeedic® and IRIS® are registered trademarks of Xpeedic Technology. ODB++® is a registered trademark of Mentor Graphics Corporation. Modelithics® is a registered trademark of Modelithics, Inc. Table of Contents
TABLE OF CONTENTS
TABLE OF CONTENTS ...... 5
1THE SONNET BOX ...... 7 Coupling to the Box ...... 8
2DXF TRANSLATOR ...... 13 Importing DXF Files ...... 14 Layer Mapping ...... 15 Post Conversion Editing ...... 17 Errors and Warnings in Processing the DXF File ...... 18 Capabilities and Limitations of DXF Translation ...... 19 Exporting DXF Files ...... 21
3DXF TRANSLATOR TUTORIAL ...... 23 Obtaining the Translator Example Files ...... 24 Importing the File ...... 24 Alignment ...... 32 Box and Cell Size ...... 32 Snapping to Grid ...... 36 Merging Polygons ...... 39 Defining Metal Types ...... 40 Configuring the Vias ...... 45 Creating a Via Technology Layer ...... 45 Assigning Polygons to a Technology Layer ...... 47 Deleting Unnecessary Metalization ...... 51 Dielectric Layers ...... 54 Using a Dielectric from the Dielectric Library . . . . . 57 Feedlines and Ports ...... 60 Changing the Bottom Metal ...... 62 3D View...... 63 Analysis Setup ...... 64 Template File...... 66 Importing with a Template ...... 67 Layer Mapping ...... 68
5 DXF Translator
Import Options ...... 71
APPENDIX IVIA SIMPLIFICATION ...... 75
Introduction ...... 75 Via Array Simplification ...... 75 Via Array Criteria ...... 76 Additional Simplify Via Array Options ...... 76 Simplify Via Array Options ...... 76 Number of New Via Metals Created ...... 82 Simplified Via Array Loss ...... 82 Bar Via Group Simplification ...... 83 New Via Metals and Bar Via Loss ...... 84 ...... 84
INDEX ...... 85
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Chapter 1 The Sonnet Box
Metal Box Top
The Sonnet six-sided shielding box. The metal walls of the box are transparent to allow you to see the interior of the circuit.
Metal Side Walls
The Sonnet EM analysis is performed inside a six-sided metal box as shown above. This box contains any number of dielectric layers which are parallel to the bottom of the box. Metal polygons may be placed on levels between any or all of the dielectric layers, and vias may be used to connect the metal polygons on one level to another.
The four sidewalls of the box are lossless metal, which provide several benefits for accurate and efficient high frequency EM analysis: • The box walls provide a perfect ground reference for the ports. Good ground reference is very important when you need S-
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parameter data with dynamic ranges that might exceed 50 or 60 dB, and Sonnet’s sidewall ground references make it possible for us to provide S-parameter dynamic range that routinely exceeds 100 dB. • Because of the underlying EM analysis technique, the box walls and the uniform grid allow us to use fast-Fourier transforms (FFTs) to compute all circuit cross-coupling. FFTs are fast, numerically robust, and map very efficiently to computer processing. • There are many circuits that are placed inside of housings, and the box walls give us a natural way to consider enclosure effects on circuit behavior.
As an example, a microstrip circuit can be modeled in Sonnet by creating two dielectric layers: one which represents your substrate, and one for the air above the substrate. The metal polygons for the microstrip would be placed on the metal level between these two dielectric layers. The bottom of the box is used as the ground plane for the microstrip circuit. The top and bottom of the box may have any loss, allowing you to model ground plane loss.
Coupling to the Box
Since the four sidewalls of the box are lossless metal, any circuit metal which is close to these walls can couple to the walls - just like what would happen if you fabricated and measured a real circuit with the same box. If you do not want to model this coupling (for example, your real circuit does not have sidewalls), then you must keep the circuit metal far away from the box sidewalls. A good rule to use is at least three to five substrate thicknesses as shown below.
This circuit has a substrate of 25 mils. The spiral should be kept at least 75-125 mils from the box walls.
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All Sonnet geometry projects are composed of two or more dielectric layers. There is no limit to the number of dielectric layers in a Sonnet geometry project, but each layer must be composed of a single dielectric material. Metal polygons are placed at the interface between any two dielectric layers and are usually modeled as zero-thickness, but can also be modeled using Sonnet’s thick metal model. Vias may also be used to connect metal polygons on one level to metal on another level.
You will use the Dielectrics dialog box (Circuit Dielectric Layers), as shown below, to add dielectrics to your circuit. Each time a new dielectric layer is added, a corresponding metal level is also added to the bottom of the new dielectric layer. You may also add dielectric layers in the Stackup Manager.
This example shows a 3-D drawing of a circuit (with the z-axis exaggerated). Please note that the pictured circuit is not realistic and is used only for purposes of illustrating the box setup.
Note that the number of the metal level appears in between the dielectric layers.
Dielectric Layer
0
Metal Level 1
2
Metal Bottom (Ground Plane). This is not shown in the Dielectric Layer dialog box
Below is a glossary of some commonly used terms in Sonnet which relate to the box model.
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Dielectric Layer: This refers only to dielectrics, NOT metals. In the example above, there are four dielectric layers. There is an entry for each dielectric layer in the Dielectric Layers dialog box (Circuit Dielectric Layers).
Metal Level: Metal levels are modeled as zero thickness and are attached to the dielectric layer ABOVE them. In the example above, there are three metal levels in addition to the box top and bottom. Since no metal may be placed on the top of the box, it may not be accessed by the user or viewed in the project editor. The bottom of the box is referred to as the GND level and may be accessed in the project editor. It is not labeled in the dielectric window. The top and bottom of the box are lossless metal by default, but can be changed in the Box Settings dialog box (Circuit Box Settings). You can use as many different metal types as you wish on a single metal level; for instance, you may use a silver polygon and copper polygon on the same metal level.
NOTE: A “layer” refers to a dielectric layer while “level” refers to the metal level which is sandwiched between the two dielectric layers. So, technically, there is no such thing as a “metal layer” in Sonnet.
GND Level: You can place polygons on the GND level, but they have no effect because this level is already completely metalized. However, cases do exist in which you may want to place a polygon on the GND level in order to place a via or a dielectric brick there.
Viewing Levels: When you view your circuit in the normal 2D view in the project editor, you are always “on” a particular level, as shown by the level drop list in the Project Editor tool bar as shown below. The top level is always “0” and increases as you move downward through the box. You can switch levels by using
10 Rev 16.56 Chapter 1 The Sonnet Box your arrow keys, or using the level drop list. By default, all polygons on your present level are shown in Fill, and all polygons on all other levels are shown as dashed outlines.
Level 0 is displayed in the level drop list in the project editor.
The dotted outline indicates metal on the level below this one.
Level 0
You may also change the view to other metal levels by using the Up One Level and Down One Level button on the project editor tool bar.
The dotted polygon seen above is shown on Level 1 which is below Level 0. Level 1
As mentioned above, the metal level is associated with the dielectric layer above, such that when you delete a dielectric layer, the metal level directly below the layer is deleted.
The total height of the box is determined by the sum of the thicknesses of the dielectric layers since metal is either modeled as zero-thickness or protrudes into the dielectric layer above. If you wish to model microstrip circuits, you will need to place a thick layer of air above your circuit; i.e., the topmost dielectric layer should be at least three to five times the substrate thickness.
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Chapter 2 DXF Translator
The DXF translator allows you to convert a DXF file to a Sonnet project by importing the DXF file into Sonnet’s project editor. The DXF translator can also be used to convert a Sonnet project to a DXF file in order to bring the design back into your layout tool or use for other processing. This chapter provides you with an overview of the import and export process. For a tutorial detailing how to perform the import of a DXF file, including creating a template file, see Chapter 3 "DXF Translator Tutorial" on page 23.
NOTE: The DXF translator is only available if you have purchased a DXF translator license from Sonnet. A DXF license is provided as part of the Sonnet LitePlus, Level2 Basic and Level2 Silver products and may be purchased as an add-on for other products. Please see your system administrator if you are unsure of the availability of this program. For details on Sonnet products, please see the Sonnet Products document available as part of your Sonnet manuals.
DXF stands for Drawing eXchange Format. Autodesk developed this format for AutoCAD many years ago. Since that time it has been adopted by many design and layout software packages for file sharing. Many high frequency circuit simulator framework tools as well as focused PCB layout tools can read/write DXF files. Users who create their circuit layouts in traditional CAD tools can export their designs directly to a DXF file.
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Importing DXF Files
The DXF translator takes a DXF input file from a circuit layout program and converts it to a Sonnet project. The translator is accessed through the project editor. Once the import is started, you are taken through a sequence of dialog boxes to control the import process. The diagram below shows the import process. DXF Import Flow Diagram
Select File Import DXF from project editor main menu.
Browse Window Select the input .dxf file.
Import Control dialog box Specify destination project, optional template file, and set technology layers checkbox.
Layer Mapping dialog box Determines mapping of DXF Layers to Sonnet levels, objects and materials and Technology Layers.
Import Options dialog box Controls project length units, box and cell size, conversion standards and via properties.
Import window Allows you to execute the Import and display the conversion status.
Sonnet Project
Post Conversion Editing
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The DXF tutorial in the next chapter walks you through the process of performing an import. For more information on the dialog boxes used during the import, please refer to Help by searching on “DXF Translator” in the index or by clicking on the Help button of any of the dialog boxes.
To import a DXF file, you select the command File Import DXF from the project editor main menu. A browse window is opened which allows you to choose the DXF file you wish to import. Each dialog box is opened in succession when you click on the Next button to walk you through the import process. If you wish to return to a previous dialog box, click on the Back button in each dialog box until you open the desired dialog box.
Layer Mapping
One of the most important aspects of importing a DXF file is in mapping the DXF layers to your Sonnet project. The DXF file does not contain the information listed below, which Sonnet requires to translate the DXF file into a Sonnet project. This information is conveyed to Sonnet through the Layer Mapping settings. 1 Which DXF layers are important to translate (for example, text layers and alignment markers are usually not translated) 2 The physical location and order of the layers (i.e., levels) in the Sonnet project (i.e., the stackup) 3 The object type that the layer represents (planar metal, via, or dielectric brick) 4 The material properties of the polygons
Sonnet’s Technology Layers can be used to store items 2, 3 and 4 making translations much more efficient.
Sometimes you do not know some of this information before translating, especially the physical location and order of the layers, and the object type of the layer. If this is the case, you may need to do a “blind” import, which allows you to look at the resulting polygons to determine the purpose of the DXF layer. Then, do a second import using the knowledge you learned from the first import. However, caution should be used when using this approach since you would not be able to detect if a given layer contains objects that do not translate due to a limitation of the translation (see “Capabilities and Limitations of DXF Translation,” page 19 for more information.)
The layer mapping can be accomplished three different ways:
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1 Manually entering the information at the time of import: This is accomplished with the Layer Mapping dialog box as shown below.
Often times, you only need to enter this information on your first import, then one of the other two methods below can be used for subse- quent imports. 2 Loading an external layer file: The layer file contains the mapping from the DXF layers to the Sonnet levels, as well as all the other settings in the Layer Mapping dialog box. You use the Save button to create a layer file and the Load button to use a previously saved layer file to enter the settings. This method is generally not as useful as the template method below because the layer file does not contain other useful infor- mation, such as material properties. 3 Using a project file as a template: This is the recommended method. Typically, after your first import, and after setting up all your settings, you would save the file as a template project to be used for subsequent imports. When using a template file, the Layer Mapping dialog box is automatically filled in for you using information included in the tem- plate. Mapping information in your template file is stored in the Technology Layer definitions. Technology Layers allow you to define a group of objects with common properties including the metal level on which they are placed in your Sonnet project; they may also store the import/export
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settings for DXF for the project. For more information on Technology Layers, please see “Technology Layers” in the index of Help.
Sonnet Stackup
In order to properly map the layers in the DXF file to the Sonnet project, you need to have an understanding of the metal levels convention in Sonnet. Below is a 3D view of a Sonnet project with two metal levels; the stackup manager for the project is also shown. Note that level 0 is the highest metal level and is attached to the bottom of the top dielectric layer. Level numbers increase as you move down through the dielectric layers. It is also important to note that Sonnet’s convention is that thick metals extend upwards into the dielectric above.
NOTE: The top level of your circuit is on Level 0 in the project editor. Next level below is Level 1. (See the figure below)
Level 0
Level 1
GND
The Project Editor Level Numbering in a 3 layer circuit.
Post Conversion Editing
Once the conversion is done, you need to complete the setup of your project in order to analyze the circuit. This is also an opportunity to check that your cell size is small enough to prevent open circuits or short circuits. Below is a list of the most common tasks that may need to be done before the analysis is run. If you use a template project, or import to present project, during the import, some of these tasks would become unnecessary if those settings are already correctly defined in the template or present project. • Defining material and dielectric layer parameters. • Decide on a proper size substrate and cell size.
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• Remove any parts of the circuit that you do not wish to include in the analysis. • Change polygons to have the proper fill (Staircase or Conformal Mesh) • Align the circuit to grid points. • Add ports and reference planes. • Specify frequency sweeps.
Chapter 3 "DXF Translator Tutorial" on page 23 uses an example to describe each of these steps in detail, some of which are performed while creating a template project.
Errors and Warnings in Processing the DXF File
You may receive an error or warning message from the DXF translator during a translation. Most commonly, these warnings are about elements in the DXF file that are not supported by the translator (see the Capabilities and Limitations of DXF Translation section below). Shown below is an example of the DXF Warnings dialog box with some more common warnings shown.
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Most error messages stop the conversion; however, there are two error messages that do not stop the conversion. Both error messages indicate that there are no polygons in the resulting project, either because all the layers in the DXF file were marked as unmapped in the Layer Mapping dialog box or because there were no polygons in the layers that were marked as mapped. In either case, it is most likely you can edit the layer Mapping using the Layer Mapping dialog box and mapping the appropriate layer(s).
Another cause of DXF errors is file incompatibility. If you are having trouble importing a DXF file into Sonnet, try saving your DXF file from your layout tool in an earlier DXF file format. As noted in the next section, the Sonnet DXF translator is based on AutoCAD R12 DXF format, so this is the preferred format, if available.
Capabilities and Limitations of DXF Translation
The DXF translator was created using the Autocad R12 DXF Specification, and later upgraded to read the Autocad R14 DXF Specification. The default output is the R12 specification which was tested in the current version of Autocad at the time of this release and encountered no problems.
The DXF translator can handle most methods of describing a circuit that is supported by the DXF file format. The DXF translator does not handle any parts of the DXF format that are not meaningful to the description of a planar circuit, such as text, dimension lines, and 3D structures. The DXF translator handles two basic methods of circuit description. All of these methods can be used within a single DXF file: • Zero width lines - The circuit is constructed using lines, polylines, circles, arcs, polygons, etc in the DXF file, all with a linewidth set- ting of zero. The metallized area is assumed to be inside the perim- eter of these objects. The objects may or may not be joined to form closed polygons. The preferred condition for translation to Sonnet is closed polygons in the DXF file. If they are not, the translator uses an algorithm to attempt to join the objects into closed polygons in the resulting Sonnet project. The Combining Tolerance, entered in the Import Options dialog box, defines how close object end- points must be in order to be joined. If the end points are automati- cally joined, often it will result in misshapen geometry, which may or may not trigger a warning message. • Finite width lines - The circuit is constructed using lines, polylines, circles, arcs, polygons, etc in the DXF file, all with a finite line- width. The metallized area is assumed to be within the area created
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by the linewidth. The objects in this scenario typically are not joined to form closed polygons. The translator takes the object and its linewidth and converts this to a polygon in the resulting Sonnet project. DXF files which use this method often require manual cleanup of overlapping polygons inside the Sonnet project editor.
The following is a partial list of DXF file features and whether or not they are supported by the Sonnet translator: • Circles and Arcs are supported but are converted to n-sided polygons in the Sonnet project. The Arc Conversion Angle in the DXF Options dialog box sets the number of sides in the resulting polygons. The default value is 10 degrees which would convert a circle into a 36-sided polygon. Please note that on DXF export, circles and arcs will not be created, just the n-sided polygons described above. • Blocks are supported by the DXF translator, including scaling, rotation and row/column replication and may be useful in any of the above methods. • Groups are supported by the DXF translator. • Regions are not supported by the DXF translator. • Polyline curve-fit and spline-fit are not supported. • Entities not supported include: POINT, Fill, TEXT, SHAPE, ATTRIBUTES, 3DFACE, VIEWPORT and DIMENSION. • Tables not supported include: APPID, DIMSTYLE, LTYPE, STYLE, UCS, VIEW and VPORT. • The only header variables read are: $EXTMIN, $EXTMAX, $LIM- MIN and $LIMMAX. All others are ignored. • In the layer table, color, line type and frozen and locked flags are ignored. The name, and on/off flags are read. • The Z coordinate of all objects is ignored. Only the layer is used to determine the Z position of the metal. • The color and line styles are always ignored. • Only the starting width of the first point in polylines are used, the ending width and both widths of other points are ignored. • No 3D structures are supported, including polygon mesh, polyface mesh and smooth surface.
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Exporting DXF Files
The DXF translator can export a Sonnet project to a DXF format file. The translator is accessed through the project editor. To export a DXF file you select the command File Export DXF from the project editor main menu. Once the export is started, you are taken through a sequence of dialog boxes to control the export. The diagram below shows the export process
Select File Export DXF from project editor main menu.
Export Options dialog box Set the options which control how to translate your project into a DXF file.
Layer Mappng dialog box Determines mapping of Sonnet Technology Layers, objects, levels and materials to DXF layers.
Browse Window Enter the output .dxf filename.
DXF file
The functions of the dialog boxes used in the export are detailed in Help. Please refer to Help by searching on “DXF Translator” in the index or by clicking on the Help button of any of the dialog boxes.
For a detailed explanation of all the control fields in the Export Options dialog box, please click on the Help button in the dialog box.
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Chapter 3 DXF Translator Tutorial
This tutorial teaches you the basics of performing a translation of a DXF file into a Sonnet project, and creating a template project for future translations. The DXF translator is accessed through the project editor. For a more detailed discussion of the DXF translator, please see Chapter 1 "The Sonnet Box" on page 7. This tutorial assumes a working knowledge of Sonnet’s project editor. You may also find it helpful to first review Chapter 1 before performing this tutorial.
NOTE: The DXF translator is only available if you have purchased a DXF translator license from Sonnet. A DXF license is provided as part of Sonnet LitePlus; however, this tutorial requires a Professional License to perform.
The circuit used for this tutorial is a microstrip interdigital bandpass filter printed circuit board design (PCB) using Rogers RO3010 material. Each resonator element is connected to ground using vias. This example contains three files: dxf_import_filter.dxf, dxf_tutorial_template.son, and dxf_import_filter_final.son. The only file actually used during the tutorial is dxf_filter_import.dxf, but the template and final project are provided as references.
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This tutorial covers the following: • Performing an initial import using only default settings • Setting box and cell size • Aligning the circuit • Defining and assigning Technology Layers • Defining materials • Defining the dielectric stackup • Setting up an analysis • Creating a template file • Performing an import using the created template file
Obtaining the Translator Example Files
You need to copy the example, DXF_trans, to your working directory using the Sonnet Example Browser. You may access the Sonnet Example Browser by selecting Help Browse Examples from the menu of any Sonnet application. For instructions on using the Example Browser, please click on the Help button in the Example Browser window.
Importing the File
In this tutorial, we will demonstrate manually inputting the mapping and project parameters, then using your initial input to create a template file for subsequent translations.
If you are using the same environment for a number of different designs, or will need to import your DXF design multiple times, the recommended method is to create a template project. A template project captures the layer mapping configuration and can optionally include the stackup information and other Sonnet project settings. It provides a convenient means to save project settings and recall them later, to streamline the DXF translation and model setup procedure.
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1 Open the project editor by clicking on the Edit Project button on the Sonnet task bar, then selecting “New Geometry” from the popup menu. A new blank project is opened in the project editor.
1 Select File Import DXF from the project editor main menu. A browse window appears on your display.
2 Navigate to the directory to which you copied the example files and select “dxf_import_filter.dxf” then click on the Open button. The Import Control dialog box appears on your display.
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3 If it is not already selected, click on the Import to New Project radio button. The New Project Name text entry box is enabled with the default project name dxf_import_filter.son. When the import is executed, a new project, dxf_import_filter.son, will be created. If you wished to use another name, you may directly edit the text entry box.
4 If it is not already selected, click on the Make Technology Layers checkbox.
Selecting this option creates a Technology Layer for each DXF layer that you map. A Technology Layer allows you to define a group of objects with common properties including the metal level on which they are placed. This will be useful later in creating a template file for subsequent translations.
If you did not wish to use Technical Layers in your project, you would clear this checkbox. The use of Technology Layers is optional. Previous Sonnet users may continue to edit as they have previously done.
5 Click on the Next button in the Import Control dialog box to continue the import. The Layer Mapping dialog box appears on your display. The settings are the default settings where the Technology layer name is set to the same name as the DXF layer, and any layers which contain objects are mapped as metal. The DXF
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layers “Text” and “0” do not contain any polygons, so these layers are not mapped. We will not make any changes on the first import since our plan is to create a template file to be used on a subsequent import.
Mapped DXF Layer checkbox Sonnet Tech Layer
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6 Click on the Next button in the Layer Mapping dialog box to continue the import. The Import Options dialog box appears on your display. This dialog box allows you to control the translation of your DXF files.
The box size will be based on the size of the imported circuit. Because there are alignment marks which denote the four corners of the printed circuit board (PCB) rectangular perimeter in the circuit, we will not add any margin to move the box walls out (See the illustration of the circuit on page 32). 7 If it is not already selected, click on the Imported Circuit Size radio button. The controls underneath the radio button are enabled. The % circuit size radio button is selected by default.
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8 Clear all the checkboxes for the box walls.
We do not wish to add any margin to the circuit size and clearing these checkboxes ensures that the box size is set only to the bounding box of the imported circuit. Note that the text entry boxes are disabled and now display a value of “0.” The resulting box size, 0.56 by 0.41 inches, is displayed below the Cell Size section. Auto is selected for Cell Size; the software inspects your circuit and attempts to choose an appropriate cell size. We will use the cell size of 0.001 X 0.001 inches estimated by the software for this project, so no action needs to be taken. For a detailed discussion on setting the cell size, please see “Tips for Selecting A Good Cell Size,” page 30 in the Sonnet User’s Guide.
The rest of the default settings are suitable for the translation, so no other changes need to be made.
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9 Click on the Next button in the Import Options dialog box.
The Import Status dialog box appears on your display. The message “Ready to Import” is displayed.
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10 Click on the Import button in the Import Status dialog box.
The file is imported and the window in the dialog box is updated. The status should end with “Conversion Complete” as shown below. Note that a warning sign is displayed and the Warnings button has been enabled.
Warning button
11 Click on the Warnings button in the Import Status dialog box. The DXF Warnings window appears on your display with the following warning:
dxfgeo WARNING - Non-Supported entities ignored:
MTEXT
"MTEXT" is a multiline text object supported in the DXF file standard. It is not supported in Sonnet as text objects are not needed for an EM analysis. This warning indicates there is MTEXT in the DXF file on some drawing layer and that it was not translated. For a complete description of what is supported in the DXF file for translation, please see “Capabilities and Limitations of DXF Translation,” page 19.
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12 Click on the Close button in the DXF Warnings dialog box. 13 Click on the Close button in the Import Status dialog box. The project editor is automatically opened and displays the translated project. Three Metal Technology Layers have been created in the stackup manager for the three DXF layers that were imported.
Box Size Indicated by Alignment Markers
Technology Layer “Symbols”
Alignment Marks
Alig nme nt Based on the default mapping, all of the populated DXF layers were mapped to Metal Technology Layers, shown in red in the stackup manager.
The metal polygons on level 0 are alignment marks which denote the four corners of the printed circuit board (PCB) rectangular perimeter. Since the box size is based on the size of the imported circuit with no margins added, the alignment marks are against the box walls. In this tutorial, we used them to set the Sonnet analysis box size and then remove them before performing the EM analysis.
Box and Cell Size
The box size created during the import process is still larger than the box size indicated by the inner corners of the alignment marks, so you will change the box size to fit the alignment marks.
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14 Select Circuit Box from the project editor main menu. The Box Settings dialog box appears on your display.
Set Box Size with Mouse
15 Click on the “Set Box Size with Mouse” button in the Box Settings dialog box. Clicking on this button allows you to adjust the box size using your mouse. The dialog box disappears and “Drag mouse to specify area” is displayed in the project editor window and the cursor is a “+” as pictured below.
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16 Click and drag your mouse so that the blue box which appears line ups with the alignment marks. Note that when you move the cursor over a vertex a blue circle appears. Select one of the inner corners of an alignment mark, and click your mouse. Then, drag your mouse until the vertex of the alignment mark in the opposite corner is highlighted. This ensures that your box size lines up with all four alignment marks.
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17 Once the edges are aligned, press the enter key to set the box size. The project editor window is updated to show the new box size and the Box Setting dialog box appears again on your display. The box size is now 0.45 by 0.3 inches, as pictured below.
New box size
18 Click on the OK button to close the Box Settings dialog box and apply the changes. Note that any metal outside of the box is ignored and not included in the analysis.
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Snapping to Grid
19 Click on Layer1 in the stackup manager. The view is switched to level 2 and shows the filter metalization.
Layer1 Metal Tech Layer
20 Click anywhere in the main window, then press Ctrl-a to select all of the polygons in your project.
All of the metal is highlighted. Note that this selects all of the polygons on all metal levels.
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21 Zoom in on the end of the feedline on the right until the grid is displayed. Notice that the selected polygon (black line) does not exactly match the metal fill (green striped). Sonnet analyzes “on-grid” metal, so if your polygon is not on the grid, then the actual metal being analyzed can differ from your input.
It is not necessary to have all of your metal polygons on “grid” as em snaps the input circuit to grid regardless and analyzes on grid metal. However, it can be more pleasing to the eye to have it snapped to grid and presents a more accurate representation of the circuit that will be analyzed by the analysis engine. 22 Select Modify Snap To from the main menu in the project editor. The Snap Objects dialog box appears on your display.
23 Click on the “Preserve shape and spacing relative to the reference point” radio button in the Snap Mode section of the dialog box. This setting will move all of the selected vertices so that their relationship to your reference point is maintained.
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Using this setting is important to ensure that your geometry is not changed when performing the snap to. This option will preserve the shape, size and spatial relationship between all of your polygons.
Preserve Shape radio button
Select Reference Point
24 Click on the Select Reference Point button in the Snap Objects dialog box. The dialog box disappears and the cursor changes to a “+” to indicate that you need to select a reference point for the snap.
25 Click on the top right hand corner of the feed line. A blue circle appears when you are above the vertex, click there.
Reference Point
The Snap Objects dialog box appears on your display again.
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26 Click on the OK button to close the dialog box and apply the changes.
The polygons are all snapped. Notice that the black outline of the polygon and the metal fill are now the same. In the case of this file, the whole circuit is now on grid. However, oftentimes the snap command will move only some of the metal on grid. In that case you may need to adjust your cell size to a finer resolution. In some cases, the slight difference between the drawn polygon and the metal fill is negligible in terms of its effect on the analysis. After performing a snap command, it is a good idea to inspect your circuit for any problems created by the snap. 27 Click anywhere to de-select all of the metalization. The black highlighting disappears.
Merging Polygons
28 Click on the Full View button on the project editor tool bar. The full circuit is visible in the window. Notice that all of the resonators in the circuit are composed of two connected polygons. Combining the pieces into one polygon often makes the analysis more efficient. Below is a close-up of the top of one of the resonators.
Two polygons
Before Merge
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29 Click and drag to select all of the resonators in the filter. All of the polygons are highlighted.
30 Select Edit Merge Polygons from the main menu in the project editor. All of the adjacent polygons in the resonators are merged. The picture shown below shows the top of one of the resonators after the merge.
Single polygon
After Merge
Defining Metal Types
Now we will define the metal types for your circuit. 31 Select Circuit Metal Types from the project editor main menu. The Metal Types dialog box is opened. Metalization in your circuit can be comprised of either planar metal types or via metal types. Each metal type can be used to define the loss in the metal in your circuit. Planar metal types are used for traces and via types for vias. When the translation was done, an unknown_metal planar metal type was created for the metal in your circuit. You need to input the
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parameters of this metal type. For a full discussion of metal types and metal loss, please see Chapter 4 "Metalization and Dielectric Layer Loss" on page 48 of the Sonnet User’s Guide.
Unknown_metal metal type
Edit button
32 Click on the Unknown_metal in the list to select it, then click on the Edit button. The Planar Metal Editor dialog box is opened.
Name text entry box
Conductivity text entry box
Thickness text entry box
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33 Enter “0.5oz_Copper” in the Name text entry box in the Planar Metal Editor dialog box.
This metal is a half ounce copper. This is the name which appears in the Metal Types dialog box and any drop lists when you are selecting the metal type for planar metals.
This metal is modeled using the Normal metal type model so there is no need to change the Model type. We are also going to use conductivity to define the loss, so you do not need to change the Specify Using drop list. 34 Enter “5.8e7” in the Conductivity text entry box. This is the conductivity of half ounce copper in S/m.
35 Enter “7.0e-4” in the Thickness text entry box. This is the thickness of the metal in inches. It is important to note that the Normal model is modeled as a zero-thickness sheet of metal so the thickness entry is only used in calculating the loss of the metal. The Thick Metal Model is used to model actual physical thickness.
The current ratio setting of 0.0 is correct so no action need be taken. The dialog box should look as shown below:
Name text entry box
Model drop list
Conductivity text entry box
Thickness text entry box
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36 Click on the OK button to close the dialog box and apply the changes. The Metal Types dialog box is updated and the unknown_metal entry has been changed to 0.5oz_copper. Note that since all of the Technology Layers in the circuit use this metal type, they have all been updated as well.
0.5oz_Copper metal type
Add Via button
Copy button
We also need to create a via metal type for the vias in the circuit. 37 If it is not already selected, click on the 0.5oz_copper metal type in the list. 38 Click on the Copy button in the Metal Types dialog box. Copying the metal will save having to enter some parameters. The Copy Metal dialog box appears on the display. This dialog box allows you to select if you are creating a planar or via metal type.
You also could have added this via metal by clicking on the Add Via button in the Metal Types dialog box. 39 Click on the “Create a via metal copy” radio button. This will create a via metal type.
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40 Click on the OK button to close the dialog box. The Via Metal Editor dialog box is opened. Notice that the Name, Conductivity and Wall Thickness have been copied from the planar metal and the pattern is the related to that of the planar metal pattern using the same color but reversing the filled and blank spaces. If the two coppers were exactly alike then there would be no need for changes. However, since the metal thickness of the vias is different from the planar metal, you need to edit some fields before creating the via metal type.
41 Enter “Copper_Vias” in the Name text entry box. 42 Click the Up arrow key in the Pattern field. The displayed pattern changes. Since the metal types are using different parameters rather than just being complementary via and planar metal types using a different pattern provides clarity when looking at the circuit. Even if the metals are complementary, some users prefer using a different color pattern for vias to help them stand out when looking at their design.
43 Enter “0.001” in the Wall Thickness text entry box.
This is the metal thickness used to model the vias that will use this metal type. The dialog box should appear as follows:
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44 Click on the OK button to close the Via Metal Editor dialog box and create the metal type. The Metal Types dialog box is updated and now shows Copper_Vias in the list of metal types. Notice that it is identified as a via metal type. The word “unused” appears across the metal type as there are not yet any via polygons using this metal type in the circuit.
Copper_vias metal type
45 Click on the OK button in the Metal Types dialog box to close it.
Configuring the Vias
The vias in the DXF file were translated as planar metal polygons since we performed a blind import. The vias in the filter extend from the metal of the filter to ground, so we will create a Via Technology Layer which extends from Level 2 to ground, then change the planar polygons representing vias to via polygons, then assign them to the Technology Layer so they are correctly placed in your circuit.
Creating a Via Technology Layer
46 Right-click on the Layer1 Technology Layer in the stackup manager and select “Add Via Tech Layer - To GND” from the popup menu which appears. The Via Technology Layer dialog box appears on your display with the default layer name Via-1 and the From Level and To Level already set correctly.
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47 Select “Copper_Vias” from the Via Metal drop list. Any vias associated with this Technology Layer will use this metal type.
48 Click on the Edit button in the Import/Export section of the dialog box. The Import/Export Mapping dialog box appears on your display. Since you are going to use this project as the basis for a template project for future imports, it is important to set the mapping for the Technology Layer.
49 Enter “Vias” in the DXF Layer text entry box in the Import/Export Mapping dialog box. When an import is executed the DXF Layer “Vias” will be mapped to Via Technology Layer “Vias-1.” This also would mean that if you export your project to a DXF file, then a DXF layer “Vias” would be created with all of the polygons associated with the Technology Layer written to it.
50 Click on the OK button in the Import/Export Mapping dialog box to close it and apply the changes. The Import/Export Mapping section of the Technology Layer dialog box is updated.
Via metal type
Mapping
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51 Click on the OK button to close the dialog box and create the Technology Layer.
The stackup manager is updated and now displays the Via-1 Technology Layer. Note that the Technology Layer only appears as an outline since there are not yet any polygons associated with it. Once the vias are added, it will appear as a solid yellow in the stackup manager.
“Via-1” Via Technology Layer
Now that you have created a via metal type and Via Technology Layer, you are ready to use the DXF Layer “Vias” to create vias in your project and associate them with the new “Via-1” Via Technology Layer.
Assigning Polygons to a Technology Layer
52 Click on the “Vias” Metal Technology Layer in the stackup manager. The project editor window is updated to show level 1.
53 Right-click on the “Vias” Metal Technology layer in the stackup manager and select “Select Polygons” from the popup menu which appears.
All of the polygons associated with the “Vias” Metal Technology Layer are highlighted.
Selected polygons
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54 Select Modify Convert to Via Polygon from the project editor main menu. The planar metal polygons are converted to via polygons. A new via metal type “0.5oz_Copper” is created during the conversion, based on the planar metal of the same name and assigned to the via polygons. A close up of two of the new via polygons is shown below.
New via polygons
55 Select all of the new via polygons on this level. You can select all of the polygons by clicking in the circuit, then dragging your cursor to “lasso” all of the polygons. Now that the metal polygons have been converted to vias, we need to assign them to the Via Technology Layer.
56 Select Modify Via Properties from the project editor main menu. The Via Properties dialog box appears on your display. Any changes you make in this dialog box will apply to all the selected polygons. Note that the message “11 objects selected” appears in the dialog box to indicate this.
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57 Select “Via-1” from the Tech Layer drop list. The Properties control drop list defaults to “Inherit.” The Inherit setting means that all of the polygons inherit their properties from the settings in the Technology Layer to which they are assigned, so all of the other controls in the dialog box are disabled. Tech Layer drop list
Properties Control drop list
58 Click on the OK button to close the Via Properties dialog box and apply the changes. The via polygons are all moved to metal level 2 since they are now associated with the Via-1 Technology Layer and that layer is assigned to metal level 2. The “Via- 1” Technology Layer on the stackup manager is now displayed as a solid color, instead of an outline, to indicate that there are now polygons assigned to it. The “Vias” Metal Technology Layer is now an outline since there are no longer any polygons associated with it.
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59 Click on the Via-1 Technology Layer in the stackup manager to view Level 2.
A view of level 2 is shown below.
Empty Technology Layer
Via-1 Technology Layer
Moved via polygons
A close up of one of the via polygons is shown below. Note that the metal pattern is that of the via metal “Copper_Vias” which you created earlier in the tutorial and are using for the Via-1 Via Technology Layer.
60 Click anywhere in your circuit to de-select the via polygons.
The metal translated from the DXF Layer Symbols is still present on Level 0. You do not wish to analyze this metal as part of your circuit, but may wish to retain the layer as a reference for the box size, especially if the box size changes, when you perform a translation using a template file. Moving the Technology Layer to the ground level allows you to keep the polygons as reference points, but does not affect the analysis, since later in the tutorial you will be changing the box bottom to the same metal type. Once the Technology Layer has been edited, all of the
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polygons may be deleted. By doing this, the DXF Layer Symbols will be translated on import and can be used as a reference to see if the box size has changed without affecting the analysis.
Deleting Unnecessary Metalization
Since the alignment marks in the Symbols Technology Layer are used only to define the box size and are not part of your circuit, they should be removed before performing the analysis. In this case, you will move the polygons to the metal GND level since planar metal polygons on the GND level have no effect. Moving the alignment marks to the GND level retains them for reference but prevents them from affecting the analysis. 61 Right-click on the Symbols Technology Layer in the stackup manager and select “Tech Layer Properties” from the popup menu which appears.
Symbols Technology Layer
Popup menu
Stackup Manager
The Technology Layer dialog box appears on your display. All of the polygons on this metal level are associated with this Technology Layer, so any changes made to the properties in this dialog box affects all of the metal polygons on this level. Note that the Import/Export Mapping at the bottom of the dialog box indicates that this Technology Layer is mapped to DXF layer Symbols.
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62 Select “GND” from the Level drop list. This will move the Technology Layer and hence, all the polygons to the ground level where they will not affect the analysis.
Level drop list
Planar Metal drop list
DXF Mapping
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63 Click on the OK button in the Technology Layer dialog box to close the dialog box and apply the changes. The project editor window is updated and the Symbols Metal Technology Layer now appears in the bottom dielectric. The polygons now appears as green dotted outlines. The dotted outlines indicate they are on another level than the one presently being viewed.
Symbol Tech Layer moved
Moved Polygons 64 Right-click on the Symbols Technology Layer in the stackup manager and select “Select Polygons” from the pop-up menu. All of the metal is selected.
65 Press Ctrl-x to delete all of the polygons on the GND level. The polygons are deleted.
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66 Right-click on the Vias Technology Layer in the stackup manager and select “Delete Tech Layer” from the pop-up menu which appears. The Vias Technology Layer is deleted. This Metal Technology Layer is no longer being used since we converted and moved the polygons, so we no longer need it. The stackup manager should now appear as shown below. Note that the Symbols Metal Technology Layer is only an outline since we have deleted all the objects associated with the Technology Layer.
Dielectric Layers
Next, we will define the dielectric layers in the stackup.
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67 Select Circuit Dielectric Layers from the project editor main menu. The Dielectric Layers dialog box is opened on your display. All of the presently defined dielectric layers in your project are displayed in the window. Since all of the metalization for the filter is on the level above GND, we do not need the top two dielectric layers.
68 Click on the top entry to select, then click on the Delete button. The top dielectric layer is deleted. Note that the top metal level is now 0.
TIP You may also delete a dielectric layer by right-clicking on the dielectric layer in the stackup manager and selecting “Delete Dielectric” from the popup menu which appears.
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69 Delete the next dielectric layer in the same manner. This leaves two dielectric layers in your project with metal level 0. There are the two dielectric layers we will keep, so now we need to define their parameters.
70 Click on the top dielectric to select it, then click on the Edit button. The Dielectric Editor appears on your display. The top dielectric layer is Air and is 0.1 inches thick.
71 Enter “Air” in the Mat. Name text entry box. 72 Enter “0.1” in the Thickness text entry box. The rest of the parameters are correct for air, so no further changes need to be made.
73 Click on the OK button to close the dialog box and apply the changes. The dialog box is closed and the appearance of the Dielectric Layers dialog box is updated.
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Using a Dielectric from the Dielectric Library
74 Click on the bottom dielectric layer to select it, then click on the Edit button. The Dielectric Editor is once again opened. This dielectric layer is 0.01 inches thick of Rogers RO3010 dielectric. This dielectric is provided in the Sonnet dielectric library delivered with your software, so you will choose the dielectric from the library, rather than entering the parameters manually.
Mat. Name text entry box Select dielectric from library button
Thickness text entry box
75 Click on the Select dielectric from library button. The Dielectric Library dialog box appears on your display. By default, the Global Library is selected and all of the dielectrics delivered with your software appear in the list. This library is meant to be used by everyone using this installation of the software. If you wish to create a library of dielectrics for your personal use, then you can define your own library, using the “My Library” radio button. You are able to add dielectrics to either library. For more details, please click on the Help button in the dialog box.
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76 Using the scroll bar on the right, move down through the list and select the “Rogers RO3010” entry. The entry is highlighted. Note that the parameters for the dielectric are included in the entry.
Global Library
Rogers dielectric
Scroll bar
77 Click on the OK button to close the dialog box and enter the parameters for the dielectric. The Dielectric Editor is updated with the parameters for the dielectric.
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78 Enter “0.01” in the Thickness text entry box. As mentioned above, this is the thickness of the dielectric layer. The dialog box should appear as shown below.
79 Click on the OK button in the Dielectric Editor dialog box to close the dialog box and apply the changes. The Dielectric Layers dialog box is updated with the Rogers dielectric.
Rogers RO3010 dielectric
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80 Click on the OK button to close the Dielectric Layers dialog box. The stackup manager is updated and now displays the names of the dielectrics.
Feedlines and Ports
Next, we need to add feedlines and ports to the circuit. 81 Click on the top dielectric in the stackup manager. The filter is displayed in the project editor window.
82 Zoom in on the left end of the left feedline. 83 Click on the Add Port button in the tool box. The cursor changes appearance.
84 Click on the end of the polygon to add the port. The edge of the polygon is highlighted in blue when your cursor is moved over it. Port 1 is added to the end of the feedline.
Port 1
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85 Right-click on the port, then select “Add Feedline” from the pop-up menu which appears on your display. A polygon is added to your circuit that is the same height as the feedline and extends from the end of the feedline to the box wall. A reference plane is also added and is linked to the corner of the added polygon.
The reference plane is indicated by an open arrow which is used for linked reference planes. When analyzed by em, the circuit is automatically de-embedded to the reference planes when the De-embed option is selected. De-embedding is the process by which the port discontinuity and any reference plane lengths are negated in the analysis results.
Reference Plane
Linked point
It is not necessary to add a port before using the Add Feedline command. You will use this method to add the second port and feedline. 86 Zoom in on the right end of the right feedline. 87 Select Tools Add Feedline from the main menu. The appearance of the cursor changes.
88 Move your mouse until the right edge of the feedline is outlined in blue. It should appear similar to the picture below.
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89 Click to add the feedline, port and reference plane. This command adds a feedline from the selected edge to the boxwall of the same height as the polygon edge. A standard port is added at the boxwall and a linked reference plane is set to the corner of the new polygon created for the feedline.
When you are done, your circuit should appear as shown below.
Changing the Bottom Metal
The Sonnet box is modeled by default with lossless metal. It is possible to change the top and bottom metal. You need to change the bottom metal (substrate) to the 0.5oz_Copper metal type. 90 Select Circuit Box from the project editor main menu. The Box Settings dialog box appears on your display.
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91 Select “0.5oz_Copper” from the Bottom Metal drop list. This sets the bottom metal to 0.5oz_Copper instead of Lossless metal.
Bottom Metal drop list
92 Click on the OK button to close the dialog box and apply the changes. The dialog box disappears. Note that there is no change of appearance in the project editor window when you change the Top or Bottom Metal.
This completes the editing of your circuit. The last task before analyzing the circuit is to set up the analysis frequency and options.
3D View
It is usually a good idea to open the 3D view of your circuit in order to look at your circuit and see if things are properly placed.
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93 Select View View 3D from the project editor main menu. The 3D view of your circuit appears on your display. The 3D view of the circuit is shown below; please note that the Z axis scaling factor is set to 2 to improve the via visibility. This allows you to see the filter on metal level 0 and that the vias are extending to ground.
94 When you are done inspecting your circuit, close the 3D view window.
Analysis Setup
You will specify an ABS sweep from 3.0 to 7.0 GHz. The Adaptive Band Synthesis (ABS) technique provides a fine resolution response for a frequency band requiring only a small number of analysis points. Em performs a full analysis at a few points and uses the resulting internal, or cache, data to synthesize a fine resolution band. This technique, in most cases, provides a considerable reduction in processing time. For a full discussion of Adaptive Band Synthesis, please see Chapter 8 "Adaptive Band Synthesis (ABS)" on page 156 of the Sonnet User’s Guide. 95 Select Analysis Setup from the main menu of the project editor. The Analysis Setup dialog box appears on your display.
96 If it is not already selected, select “Adaptive Sweep (ABS)” from the Analysis Control drop list. The dialog box is updated to show a Start and Stop text entry box for the adaptive sweep.
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97 Enter “3.0” in the Start text entry box and 7.0 in the Stop text entry box. This defines the band over which the circuit is analyzed.
Advanced button
Analysis Control drop list
Start text entry box
Stop text entry box
98 Click on the Advanced button in the Analysis Setup dialog box. The Advanced Options dialog box is opened on your display. For this analysis, we wish to ensure the proper resolution of the response data produced by the sweep, so we will manually set the ABS Frequency Resolution. The resolution provides the minimum value of the gap between data points in an adaptive band synthesis (ABS). Fine resolution does not slow down the analysis unless the number of frequency points in the band is above approximately 1000-3000 data points. A step size resulting in at least 50 points and less than 2000 points is recommended.
In our case, the resolution will be set to 0.01 GHz which yields 400 data points. 99 Click on the Manual button in the ABS Frequency Resolution Per Sweep section of the Advanced Options dialog box. The Frequency text entry box is enabled.
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100 Enter “0.01” in the Frequency text box. The dialog box should appear as shown below.
Frequency text entry box
Manual radio button
101 Click on the OK button to close the Advanced Options dialog box and apply the changes. 102 Click on the OK button in the Analysis Setup dialog box to close the dialog box and apply the changes. This completes the setting up your project for analysis. Before analyzing, you need to save your circuit.
103 Select File Save from the main menu of the project editor. The project is saved and ready to analyze.
Template File
Now that the setup is complete, you may use your finished project to create a template file for subsequent translations. In this next section, you will create a template file, then use that template to perform the import again.
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104 Select File Save As from the project editor main menu. Before editing your project, we will save it under the template name. A Browse window appears on your display.You may save the file in the same working directory or in another location.
105 Save the project as “dxf_import_template.son” in the desired directory. We are using a generic template name for this tutorial. For real imports, it is helpful to name the template so it is easy to identify, for example, by using a design or job name.
106 Press Ctrl-a to select all of the metalization in the project. Because this is a template file, you should remove all of the metalization for a clean import.
107 Press Ctrl-x to delete all of the metalization. All of the polygons on all levels are deleted and your substrate is blank. The stackup manager does not change. Everything else in the project: the stackup, the materials, the box and cell size and the analysis setup will all be the same so no further editing is required.
108 Select File Save from the project editor main menu. The template file is saved.
109 Select File Close to close the template file. Now we will perform the import again using a template file.
Importing with a Template
110 Select File Import DXF from the project editor main menu. A browse window appears on your display.
111 Navigate to the directory to which you copied the example files and select “DXF_import_filter.dxf” then click on the Open button. The Import Control dialog box appears on your display.
112 If it is not already selected, click on the Import to New Project radio button. The New Project Name text entry box is enabled with the default project name dxf_import_filter.son.
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113 Enter “dxf_import_filter_wtemplate.son” in the New Project Name text entry box. This will save this translation under a different file name so you do not overwrite the other project.
114 If it is not already selected, click on the Make Technology Layers checkbox.
Selecting this option creates a Technology Layer for each DXF layer that you map. Since you are using a template file, the Technology Layer definitions in the template file are used to populate the Layer Mapping dialog box. 115 Click on the Use a project as a template checkbox. The Template Name text entry box is enabled.
116 Enter “dxf_import_template.son” in the Template Name text entry box.
If you saved the template file in a different location than your example files, click on the browse button and navigate to its location and then select it. The Import Control dialog box should now appear similar to the picture below.
Layer Mapping
117 Click on the Next button in the Import Control dialog box to continue the import.
The Layer Mapping dialog box appears on your display. Since the template file was used to populate the Layer Mapping dialog box, the settings only need to be verified.
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As was shown in Step 49 on page 46, when you define a Technology Layer, you may optionally map a DXF Layer to the Technology Layer. This information is stored in the template file as part of the Technology Layer. So when you use a template layer to import a circuit, the existing Technology Layer is read and if a DXF Layer is identified, then that DXF layer in the imported DXF file is translated into the Technology Layer. This is the information that is used for the settings in the Layer Mapping dialog box.
DXF layer “text” not mapped
Mapped Layers Technology Layers
For an import (indicated by the arrow pointing to the right), the Layer Mapping dialog box maps your incoming DXF layers to the Sonnet object, metal level and material. If you assign a DXF layer to a Technology Layer, then the objects, metal level(s) and materials used by the Technology Layer are used. Because of this, when a Technology Layer is used, the rest of the Sonnet controls are disabled.
As you can see, the DXF Layers are being mapped to the Technology Layers to which you assigned them after your first import in the project you used for the basis of your template. For example, note that the DXF Layer Vias is assigned to Technology Layer Via-1 so that the polygons on that layer are identified as vias and are being placed between the correct metal levels.
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Because of the setup in your template file, there is no need to make any changes to this dialog box. In some cases, you may wish to make changes for such things as there being another DXF layer which is not in your template file but you wish to map it. In that case, you would select the Map checkbox and then define the rest of the Sonnet fields. For information on all of the control fields in this dialog box, please click on the Help button. 118 Click on the Next button to close the Layer Mappings dialog box. The Layer Mappings dialog box is closed.
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Import Options
The Import Options dialog box appears on your display when the Layer Mapping dialog box is closed. The Import Options dialog box allows you set options which affect how your DXF file is translated.
Template Box Size radio button
119 Click on the Template Box Size radio button. Since we set up the correct box size as part of our template, you want to use the template box size. Note that when you click on this radio button, the radio buttons below it are enabled. In addition, in the Cell Size section of the dialog box, the Auto radio button is changed to the Template radio button and the cell size from the template is displayed.
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120 Click on the Center Circuit radio button under Template Box Size. Since the circuit was already placed in the center of the alignment marks which were used to define the box size, you want to have the circuit translated to the center of the box.
The length unit was properly set by reading the length unit from the template file.
For information about the rest of the controls, please click on the Help button in the dialog box. You do not need to make any further changes in this dialog box. 121 Click on the Next button to close the Import Options dialog box. The Import Status dialog box appears on your display with “Ready to Import” shown in the status window.
122 Click on the Import button in the Import Status dialog box.
The file is imported and the window in the dialog box is updated. The status should end with “Conversion Complete” as shown below. You may ignore the Warning symbol as it is again about the TEXT layer not being supported.
123 Click on the Close button in the Import Status dialog box. The dialog box is closed and the imported project is displayed. Note the stackup is correct, and the box size is correct. The analysis controls are also already set up. The template saves you from repeating the bulk of the editing but there are a few steps you need to repeat. These are the steps you would need to do in order to be ready to analyze the project.
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• Snap the circuit to grid (Step 21 on page 37). • Merge the polygons (Step 29 on page 40). • If so desired, delete the polygons from the Symbols layer. Since they are the same metal type as the box bottom, they will not affect the analysis (Step 61 on page 51). • Add feedlines, ports and reference planes (Step 81 on page 60). • Save the file.
As you can see, using a template file can make multiple imports of a design much more efficient. This completes the DXF tutorial.
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Appendix I Via Simplification
Introduction
Several manufacturing processes used to produce RF circuits utilize via arrays or bar via groups to provide the trace metal layer to layer connections. Both of these types of vias present an analysis challenge which drives the Sonnet model memory and analysis time requirements beyond what is practical to analyze. Via simplification provides an approach to via arrays and bar vias that reduce the time and memory requirements without sacrificing accuracy. These two processes are discussed in this appendix.
Via Array Simplification
For via arrays, the small size of the individual vias and the large number in the array usually drive Sonnet model memory and analysis time requirements beyond what is practical to analyze. This often requires that you simplify the via geometry detail before performing your EM simulation. In the past, via array simplification would need to be done manually by deleting vias and replacing with a single, larger via polygon.
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The Simplify Via Array feature automatically performs this simplification during the translation process. It can be invoked inside the Keysight ADS Interface, the Cadence Virtuoso Interface, NI AWR Microwave Office Interface - 32 Bit and NI AWR Microwave Office Interface - 64 Bit. It may also be invoked in Sonnet’s project editor when performing an import using the Gerber/ODB++ Translator, GDSII Translator or DXF Translator.
Via Array Criteria
There are six criteria, all of which must be met, before a group of vias in the original geometry is considered an array and therefore simplified by the software.
Number of Vias: There must be a minimum number of vias in order for them to be considered an array.
Via Size: The vias must be the same size or nearly the same size.
Via Spacing: The vias must be within a certain distance of one another.
Layer Pass Through: The vias must pass through the same layer(s).
Metal Polygons Pads: The vias must be contained within the same metal polygon at either the top or the bottom of the vias.
Material: The vias must be set to the same material, whose conductivity is the same.
Additional Simplify Via Array Options
This text entry box should only be used at the direction of a Sonnet representative.
Simplify Via Array Options
There are six control options for the simplify via array feature which are discussed in detail in the following sections. We will use a simple example circuit to illustrate how the options affect the via simplification.
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TIP The default values were determined based on extensive testing, and in the majority of cases will provide reasonable via simplification behavior. However, Sonnet handles a wide range of layouts and processes, so these controls were provided so that a user can customize the translation if it proves necessary.
The example structure consists of three metal layers and two interconnecting via arrays, as shown below. Since the vias pass through different dielectric layers and use different metal types, the 1 X 2 array and the 5 X 5 array would never be grouped together. Either reason would be sufficient on its own to prevent these two arrays being grouped together.
The 1 X 2 via array extends from The 5 X 5 via array extends metal level 0 to metal level 1 from metal level 1 to metal through the upper dielectric layer. level 2 through the lower dielectric layer.
3D View of circuit 5 X 5 via array. Each via is 4 μm square and the assigned metal type is 1 X 2 via array. Via2. Each via is 1 μm square and the assigned metal type is Via1.
2D View of Metal Level 1
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Minimum Vias in Array
This control defines the minimum number of vias which can be considered part of the same array. The default value for this setting is 5, so that only arrays with 5 or more vias will be considered for simplification. Therefore, in our example the 1 x 2 via array would not be simplified, but the 5 X 5 would be analyzed to see if this array meets the rest of the simplification criteria. You may enter any integer value to set the minimum number required.
1 X 2 Via array 5 X 5 Via Array Will not be simplified Will be simplified
Max Distance to Size Ratio
This control defines the maximum spacing between vias which can be considered part of the same array. While the distance between vias is measured from the center lines of the individual vias, the control is a ratio of distance to via size. This distance cannot exceed the value of this ratio multiplied by the via size. The default setting is 4.0 and the larger the value, the more widespread the vias can be and still be grouped in the same array. Since individual via cross-sections can be of any shape, the square root of the via area is used as the via size.
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For our example the size of the vias is 2.0 μm and the center to center spacing is 4.0 μm, as pictured below. This results in a Distance to Size ratio of 4.0/2.0 = 2.0 so that this array meets the via spacing criteria.
The center to center The size of an spacing is 4 μm. individual via is 2μm.
Maximum Size to Size Ratio
This control defines the maximum allowable difference in via size to be considered part of the same array. The default value of this ratio is 1.5 and the larger the value, the greater the difference of via size is allowed within an array. Since individual via cross-sections can be of any shape, the square root of the via area is used as the via size. For this example, the via cross-section is a 2.0 X 2.0 μm square. The area is 4 μm2 and taking the square root, yields a via size value of 2 μm.
Since all of the vias are the same size in this array (2.0 μm) the Size to Size ratio is 1.0, so that this array meets the via size criteria.
TIP If you wish to limit your arrays to vias of the same size, set this control to 1.0.
Max Expansion Coefficient
This control helps define the size of the resulting simplified via by allowing it to be larger than the original via array perimeter (also referred to as the bounding box). The default value is 7.0, which allows the simplified via to expand outward by a factor of 7 times the largest via size in the array. The advantage in expanding
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the simplified via is that it can often be sized to match the polygons to which the via attaches. Having the via polygon edge and pad polygon edge in alignment can significantly reduce the subsection density in the region and thereby reduce the memory requirement of the model.
An example is shown below. The algorithm looks outward from an imaginary rectangle (bounding box) drawn around the perimeter of the array (green rectangle). The distance checked out from the perimeter is the Max Expansion Distance (shown in red arrows). It is equal to the Max Expansion Coefficient times the largest sized existing via in the array. If a vertex from a pad polygon is encountered within this window (red rectangle), the expansion stops and this sets the simplified polygon edge. If no vertices are found in a particular direction, the edge of the simplified via rolls back to the existing via array perimeter. Please note that all metal levels are examined when looking for vertices within the maximum expansion distance.
The Max Expansion Distance is denoted by the red dashed box and is 7.0 times (default value) the largest via size (2.0 μm) = 14.0 μm. The blue stars are vertices within the max expansion distance on this metal level. The yellow star indicates a vertex found on another metal level.
The via array perimeter is indicated by the dashed green box. If no vertices are found in that direction, then the perimeter defines the edge of the simplified via in that direction.
The dashed blue box above shows the final size of the simplified via. On the top, bottom and right hand side the via extends to the vertices and on the left side it conforms to the array bounding box (dashed green box) since no vertices were found within the maximum expansion distance in that direction.
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TIP The default setting for Max Expansion Coefficient is 7.0. If you wish the simpli- fied via to be the bounding box around the array, set the Max Expansion Coeffi- cient to 0, which allows no expansion.
Merge Planar Polygons During Simplification
In order to be considered an array, a group of vias must connect to a single polygon on the top and bottom of the group. This control allows the user to merge the polygon pads or traces prior to simplifying the vias. This results in larger arrays being recognized leading to the least number of simplified vias, thereby producing the most efficient model. This option is enabled by default. The option is illustrated below using the example circuit.
The trace is divided into two parts (black outlines show the two polygons).
If the Merge Planar Polygon option is not selected, then the array is treated as two via arrays (indicated by the dashed red boxes) and two simplified vias are created. If the option is on, however, the two parts of the trace are merged into one polygon and the whole array is simplified into one via.
NOTE: The polygons are only temporarily merged for via simplification and will not be merged in the resulting Sonnet project.
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Number of New Via Metals Created
Via metal types using the Array loss model are created to model your simplified vias in Sonnet. This setting controls how many via metal types are created in your translated project in order to model your simplified array. The fill factor is used to determine how many metal types are created. For more information on the fill factor and the Array loss model, please see “Array Loss Model” in the Sonnet User’s Guide.
There are three choices:
Minimum: Creates the least number of via metal types but may be less accurate as a wider range of fill factors will be grouped together.
Automatic: Creates the via metal types based on an algorithm that balances the trade off between accuracy and the number of via metal types produced. This is the default setting.
Maximum: Creates the highest number of via metal types providing the most accurate answer since a via metal type is created for each unique fill factor.
Simplified Via Array Loss
When an array is converted to a simplified via, a via metal type using the Array Loss model is created, if it does not yet exist. For example, you are translating an array which uses “ViaMetal1” for an array. During the translation a via metal type “ViaMetal1” is created that uses the Array Loss model. During translation, one source metal may be translated into two metal types if there is a significant difference in individual via size in different arrays using the same metal. For more information about via metal types and defining their loss, please see “Array Loss Model,” in the Sonnet User’s Guide.
The simplified via is modeled using the same meshing fill as the vias in the original via array. For a detailed discussion of meshing fill for via polygons, please see “Meshing Fill for Vias” in the Sonnet User’s Guide.
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Bar Via Group Simplification
Bar vias are vias whose length is significantly longer than their width. They are typically used in stacked multi-level conductors where vias carry horizontal currents. An example is shown below, with one of the bar vias highlighted in black. For vias whose aspect ratio is smaller, such as 1:1, the Sonnet model assumes that there is little to no horizontal current in the via. The assumption is that current flows in the vertical or z-direction. For bar vias, whose aspect ratio is larger, the current flow in the horizontal direction is more significant. Bar via groups placed on metal traces also drive a very fine resolution in the meshing that can require an inordinate amount of processing resources.
The Identify Bar Vias feature identifies bar vias in the translated circuit based on length to width ratio entered by the user. These vias are assigned the Bar via meshing fill, then during the analysis multiple adjacent bar vias are identified as a bar via group and merged into one wider via during the subsectioning by the analysis engine, em.
Since via arrays are simplified during translation, their appearance in the project editor is that of the simplified via polygon into which the via array was converted. However, in the case of bar vias, the actual via polygon input by the user is displayed in the project editor, because no simplification has yet been done. If you wish to see the actual metal for the simplified bar vias that are used in the simulation, you should view the subsections for the circuit. For a detailed
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explanation of how bar vias are simplified and modeled by the analysis engine, please see “Simplifying Bar Vias in the Analysis Engine,” page 293 in the Sonnet User’s Guide.
NOTE: The Simplify Via Arrays feature must be on in order to use the Identify Bar Vias feature.
This feature can be invoked inside the Keysight ADS Interface, the Cadence Virtuoso Interface, and the NI AWR Microwave Office Interface. It may also be invoked in Sonnet’s project editor when performing an import using the Gerber/ ODB++ Translator, GDSII Translator or DXF Translator.
New Via Metals and Bar Via Loss
Metal used for bar vias should always use the Volume loss model since this model supports horizontal current. Any vias that use the Array loss model or the Surface loss model will not be identfied as bar vias during the simplification process.
Changes in meshing fill do not change the loss associated with a via polygon, only the way in which the via is subsectioned. Loss is based on the loss model used for the metal type. For more information about via metal types and the Volume loss model, please see “Volume Loss Model” in the Sonnet User’s Guide. Note that this description details the loss in the vertical direction. For the horizontal loss, bar vias are modeled in the same way as Thick metal. For more information on Thick metal modeling, see the “Thick Metal” chapter in the Sonnet User’s Guide. For a detailed discussion of meshing fill for via polygons, please see “Meshing Fill for Vias,” in the Sonnet User’s Guide.
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Index
A F air 8, 11 flags 20 APPID 20 arcs 20 G array criteria 76 GDSII file array see via array simplification exporting 21 ATTRIBUTES 20 importing 14–18 GDSII_trans 24 B blocks 20 H box header variables 20 coupling 8 definition 7 I C importing GDSII file 14–18 circles 20 circuit description 19 L commands 13 $LIMMAX 20 D $LIMMIN 20 level number 17 DIMENSION 20 LIMMAX 20 DIMSTYLE 20 LIMMIN 20 DXF file loss 7 error message 18 loss of simplified via array 82 LTYPE 20 E $EXTMAX 20 M $EXTMIN 20 max distance to size ratio 78 enclosure 7 max expansion coefficient 79 error message 18 maximum size to size ratio 79 example files merge planar polygons during GDSII_trans 24 simplification 81 exceptions microstrip 8, 11 entities not handled 20 minimum vias in array 78 exporting GDSII file 21 N EXTMAX 20 number of new via metals created 82, 84 EXTMIN 20
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P VIEW 20 VIEWPORT 20 POINT 20 VPORT 20 polyface mesh 20 polygon mesh 20 X polyline 20 xgeom level number 17 R rotation 20 row/column replication 20 S scaling 20 SHAPE 20 shielding box 7 simplify via arrays 75, 83 array criteria 76 loss 82 options 76–82 smooth surface 20 SOLID 20 STYLE 20 T 3D structures 20 3DFACE 20 tables not handled 20 TEXT 20 TRACE 20 troubleshooting DXF file error message 18 U UCS 20 V variables $EXTMAX 20 $EXTMIN 20 $LIMMAX 20 $LIMMIN 20 header 20 via array simplification 75, 83 array criteria 76 loss 82 options 76–82
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