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Current Source Biasing

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Current Source Biasing Current Source Biasing • Integrated circuits have transistors which are manufactured simultaneously with the same device parameters (parameters from chip to chip will vary) • As a result, different bias techniques are employed than in discrete designs • One common technique is current source biasing, which allows the designer to take advantage of matched devices • We will begin by looking at some simple current source circuits • A current source is not a “naturally” occurring device. It can be simulated by a network of transistors and circuit elements. The voltage across RE is approximately constant. \ IE is held at a constant value -VEE -VBE I E = RE Problem: For the previous circuits find the bias values IC and VCE for each transistor Solution Assume D1 and D2 forward biases (I1 > IB2) VB = VEE + 2VF = -10V + 2(0.7V) = - 8.6V Using KVL around loop A 2VF = VBE2 + IE2 R2 Since VBE2 @ VF VF 0.7V IE2 = = @ 3.7 mA R2 180W Since IC @ IE IC1 = IC2 = 3.9 mA Check that D1 and D2 are forward biased for a worst case minimum bF = 20 IC2 IB2 = @ 0.19 mA b F VCC -VB 10V - (-8.6V) I1 = = = 0.37 mA R1 50 kW VC1 = VCC - IC1RC = 10V - (3.9 mA)(1kW) = 6.1V VE2 = VB -VBE2 = - 8.6V - 0.7V = - 9.3V VE1 = VC2 = 0V -VBE1 = - 0.7V VCE1 = VC1 -VE1 = 6.1V - (-0.7V) = 6.8V VCE2 = VC2 -VE2 = - 0.7V - (-9.3V) = 8.6V Current Mirrors • Current mirrors also take advantage of matched transistors but require a minimal number of resistors. They are also well suited for circuits with more than one stage. Basic BJT Current Mirror VCC - (VCE1 +VEE ) VCC -VBE1 -VEE I A = = RA RA I A = IREF + IB1 + IB2 IF b F is large IB1 << IREF IB2 << IREF IREF @ I A Problem For the following circuit IC3 = 3 mA and VCE = 5.4 V. Find the quiescent (DC bias) power dissipated in each transistor. IC3 @ Io = IREF @ I A 0V - (VF +VEE ) I A = RA -VF -VEE -0.7V - (-10V) RA = = = 3.1kW IREF 3mA VE = - 0.7V; To achieve VCE = 5.4V, VC = 4.7V VCC -VC = 10V - 4.7V = 5.3V 5.3V R = = 1.8 kW C 3mA The DC power in each transistor is given by: PQ = ICVCE + IBVBE @ ICVCE PQ1 = (3mA)(0.7V) = 0.2 mW PQ2 = (3mA)[-0.7V - (-10V)] @ 28 mW PQ3 = (3mA)(5.4V) = 16 mW MOSFET Current Mirror Advantage: IREF = IA Gate current is negligible Widlar Current Source • The basic current mirror requires that the bias current and reference current be equal • The wildar current source sets the mirrored current to a value smaller than IREF by using an extra resistor • The widlar current source allows you to establish small bias currents (mA) without using large resistor values VCC -VEE -VBE1 IREF @ RA VBE1 = VBE2 + IE2 R2 V V æ BE ö BE hV hV I = I çe T -1÷ @ I e T E EO ç ÷ EO è ø IE VBE = hVT ln IEO Assuming matched BJTs IE1 IE1 hVT ln = hVT ln + IE2 R2 IEO IEO IE1 IE2 R2 = hVT ln IE2 IE1 @ IREF IE2 @ Io hVT IREF Io = ln R2 Io · Equation difficult to solve in closed form. Use successive iteration or trial and error · When you know the desired Io then IREF can be found directly æ Io R2 ö I REF = Io expç ÷ è hVT ø Problem: Using a widlar current source find the values of RA and RB that will produce Io = 100 mA. Given VCC = 10 V, VEE = -10 V, VF = 0.7 V and h = 1. Solution: Select a value of R2 such that Io R2 @ hVT To keep exponent from becoming too large hVT = 25mV Choose Io R2 = 100 mV \ R2 = 1kW é(100 mA)(1kW)ù IREF = (100 mA)expê ú =5.46 mA ë 0.025V û VCC -VEE -VF IREF = RA 10V - (-10V)- 0.7V R = = 3.54 kW A 5.46 mA Wilson Current Source • Refined Widlar source that can produce IO > IREF · The balance between VBE1 and VBE2 is set by the ratio of R1 to R2 Assuming IC @ IE VBE1 + IREF R1 = VBE2 + Io R2 IREF Io hVT ln + IREF R1 = hVT ln + Io R2 IEO1 IEO2 Assuming matched devices hVT IREF R1 Io = ln + IREF R2 Io R2 Small Signal Modeling of Three Terminal Devices • Incremental signals • Piecewise linear models • Incremental circuit models – BJT – FET • Refinements to incremental model – Output resistance – Input resistance – Alternative BJT representation • Two - port representations Small Signal Modeling of Three Terminal Devices • Related to PWL concept in which the V-I characteristics are modeled by a straight line tangent to the curve at a particular operating point • With three terminal devices the relationship between the output port and input port must be taken into account. This generally leads to a PWL model with a linearly dependent source. • Circuits containing small signal models can be analyzed using linear circuit theory under proper conditions • The terms small-signal and incremental will be used interchangeably Incremental Signals • Any transient, periodic or AC fluctuation in a voltage or current • An incremental signal is small in magnitude compared to the bias voltages or currents in the circuit • Incremental signal carries the signal information processed by the circuit PWL Models of Three Terminal Devices • Formation of small signal model begins with PWL model • PWL model can be applied to three terminal device if the dependency of the output port is considered ¶ vbe hVT rBE = = ¶ ib V ,I I B BE B · Model valid only in constant current region · If the circuit in which the BJT is connected produces a signal as well as a bias component to iB then: ic (t) = bo ib (t) · where ic and ib are inc · remental signals and bo is the incremental current gain • Since bF is fairly constant it is possible to assume bo = bF in many cases • The symbols hFE and hfe are sometimes used instead of bF and bo when using h-parameter analysis Incremental Circuit Model In analyzing the small signal performance of a circuit it is customary to ignore the DC components of the model once the bias conditions have been established. This can be accomplished by the following procedure: 1. Find the DC bias point and determine an appropriate PWL model 2. Set all bias values to zero by setting all DC sources to zero (including those in the PWL model) 3. Solve the desired variables using linear circuit theory 4. Superimpose the signal variables onto the corresponding DC bias voltages and currents to obtain the total voltage and current values VBB -VF 1V - 0.7V IB = = = 30 mA RB 10 kW IC = b F IB = (100)(30 mA) = 3mA VOUT = VCE = VCC - IC RC = 10V - (3mA)(1kW) = 7V · Transistor operates in constant current therefore we can use PWL model developed earlier hVT 1(0.025) rbe = = @ 833W IB 30mA vs ib = vo = - boib RC RB + rbe -bo RC -100(1kW) vo = vs = vs @ - 9.2 vs RB + rbe 10 kW + 0.833kW -b R o C is the incremental or small - signal voltage gain RB + rbe VOUT = VCE + vo (t) = 7V - 9.2 vs (t) Total = Bias + Incremental Voltage Voltage Signal Problem: For the following circuit find the incremental components of vc and ve. Note: vs connection does not represent typical amplifier design. KVL around the input loop for incremental signal R1 vs = ib (R1 R2 ) + ib rp + (bo +1)ib RE R1 + R2 éR1 ù vs ëê (R1 + R2 )ûú ib = (R1 R2 ) + rp + (bo +1) RE éR1 ù (bo +1) RE vs ëê (R1 + R2 )ûú ve = (bo +1)ib RE = (R1 R2 ) + rp + (bo +1) RE éR1 ù bo RC vs ëê (R1 + R2 )ûú vc = - (bo ib ) RC = - (R1 R2 ) + rp + (bo +1) RE In the limit R1 R2 << (bo +1) RE bo +1 @ bo rp << (bo +1) RE R1 ve @ vs R1 + R2 RC R1 vc @ - vs RE R1 + R2 Incremental Model of MOSFET ¶ i ¶ g = D = k(V -V )2 = 2k (V -V ) m [ GS TR ] V , I GS TR ¶ vGS V , I ¶ vGS GS D GS D Assume constant current operation 1/2 æ I ö V -V = ç D ÷ GS TR è k ø gm = 2 k ID Similar expression can be derived for JFET • An incremental description for a FET can also be defined for triode (resistive) region • It can be shown that the incremental model is as follows 1 rds = gm = 2k VDS 2k (VGS -VTR ) Problem: (A) Find the small signal componont of VOUT for the 2 following circuitd vs = 0.1 Sin wt, k = 0.2 mA/V , VTR = -2 V. (B) Find the Thevenin circuit between VOUT and ground .. The bias values can be found to be ID @ 0.47mA VGS = -ID RE = - 0.47V Applying KVL to output loop VDS = VDD - ID (RD + RE ) = 10V - (0.47mA)(3k) = 8.6V · Since VDS > (VGS -VTR) = 1.53 V the device operates in the constant current region The incremental transconductance gm is given by gm = 2k (VGS -VTR ) = 2(0.2 mA / V2 )[-0.47 V - (-2 V)] @ 0.61mA / V • The signal component of vOUT can be found by substituting the PWL model and setting all DC sources to zero Applying KVL to the output loop vgs = vs - id RE = vs - (gmvgs )RE vs vgs = 1+ gm RE \ Note feedback limits the fraction of vs that appears as vgs vOUT = - id RD = - gm vgs RD -gm RD vOUT = vs 1+ gm RE vOUT -gm RD -(0.61mA / V)(2 kW) aV = = = = - 0.76 vs 1+ gm RE 1+ (0.61mA / V)(1kW) vOUT = aV vs = (-0.76)(0.1sinwt) = - 0.076sinwt • Since vOUT is computed with no load it represents the incremental open circuit Thevenin voltage • The incremental rth can be found by setting vs to zero and applying vTEST vgs = gm vgs RE can only be satisfied if vgs = 0 vtest itest = RD vtest rth = = RD itest.
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