A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE
CURRENT GENERATOR
A Thesis Presented to The Graduate Faculty of The University of Akron
In Partial Fulfillment of the Requirements for the Degree Master of Science
Shivasai Bethi December, 2014
A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE
CURRENT GENERATOR
Shivasai Bethi
Thesis
Approved: Accepted:
______Advisor Department Chair Dr. Kye-shin Lee Dr. Abbas Omar
______Committee Member Dean of the College Dr. Joan E. Carletta Dr. George K. Haritos
______Committee Member Interim Dean of the Graduate School Dr. Robert Veillette Dr. Rex D. Ramsier
______Date
ii
ABSTRACT
This thesis presents the design of a temperature and process insensitive CMOS only
reference current generator. The proposed reference current generator consists of a
conventional CMOS Widlar current source, in which the passive resistor is replaced with
a transistor resistor. The gate voltage of the transistor resistor is provided by a gate bias
generator that makes the output current insensitive to temperature variation. Furthermore,
to achieve a process insensitive reference current, three separate gate bias generator
circuits for nominal, strong and weak corners were designed. These gate bias generators are manually selected by the control switches to minimize the current variation under
different process corners. As an extension of the manual mode selector, the design of an
automatic mode selector that automatically selects the optimum gate bias generators to
minimize the current variation under different process corners is realized. The proposed
reference current generator can be used for high temperature sensor interface applications
that include amplifiers, oscillators, filters and data converters. The proposed reference
current generator is designed using 0.5 µm CMOS SOI technology, and the operation has
been verified through circuit level simulations. The results show for a reference current of
20 µA, a temperature coefficient of 39 ppm/°C is achieved in the temperature range
between 25°C and 125°C for the nominal process corner. Using the mode control circuits
for different process corners, worst-case temperature coefficients of 520 ppm/°C and 300
ppm/°C are obtained for the weak and the strong corners, respectively.
iii
DEDICATION
Dedicated to my Parents and Friends.
iv
ACKNOWLEDGEMENTS
First and foremost, I would like to express my sincerest gratitude to my advisor Dr.
Kye-Shin Lee for his continues advice, guidance and support throughout my study. He had been guiding me academically and emotionally through the rough road to finish my thesis. During the toughest process of my thesis writing, he also gave me his endearing support, guidance and advice that I needed to complete.
I would also specially like to thank my committee members Dr. Joan Carletta and Dr.
Robert Veillette for their valuable advice and their continuous support on my thesis.
A special person whom I am deeply thankful to is Dr. Alex De Abreu-Garcia, who played a deserving part for my study at The University of Akron.
Last but not the least, I would like to express my thankfulness to my family, friends, research assistants and seniors who have supported me and given me an immense amount of motivational support.
v
TABLE OF CONTENTS
Page
LIST OF FIGURES ...... viii
LIST OF TABLES ...... x
CHAPTER
I. INTRODUCTION ...... 1
1.1 Motivation ...... 1
1.2 Goal of thesis ...... 3
1.3 Organization of this thesis ...... 4
II. LITERATURE REVIEW ...... 5
2.1 Bandgap reference ...... 5
2.2 MOSFET ZTC point ...... 7
2.3 CMOS reference current generator ...... 10
2.4 Summary of the previous work ...... 13
2.5 Summary of contribution ...... 14
III. PROPOSED CMOS ONLY REFERENCE CURRENT GENERATOR ...... 16
3.1 Temperature insensitive operation ...... 16
3.2 Process insensitive operation ...... 20
vi 3.3 Simulation results ...... 23
IV. AUTOMATIC MODE SELECTION DESIGN ...... 25
4.1 The automatic mode selection operation ...... 25
4.2 Current to voltage (I-V) converter ...... 27
4.3 Mode selector ...... 28
4.3.1 The controller ...... 32
4.3.2 Bit serial adder ...... 34
4.3.3 Bit serial magnitude comparator...... 36
4.3.4 Signal generator ...... 39
4.3.5 Comparison decoder ...... 40
4.4 Simulation results ...... 41
V. CONCLUSION ...... 45
5.1 Summary ...... 45
5.2 Future work ...... 46
BIBLIOGRAPHY ...... 47
vii LIST OF FIGURES
Figures Page
2.1: Block diagram of reference current generator based on bandgap reference technique 6
2.2: Typical low voltage bandgap reference current using an opamp ...... 7
2.3: Trans-conductance characteristics of a transistor showing the ZTC point [11] ...... 8
2.4: Proposed 10 bit gate-controlled DAC ...... 9
2.5: Conventional CMOS reference current generator ...... 11
2.6: Reference current for conventional circuit at different process corners over temperature ...... 11
2.7: Temperature compensated CMOS current reference ...... 12
3.1: The proposed current generator circuit ...... 17
3.2: Gate bias circuit for different process corners ...... 21
3.3: Reference current with temperature for nominal corner ...... 24
4.1: Block diagram of the overall automatic mode selector ...... 26
4.2: The reference voltage generator for Mode 1 ...... 27
4.3: The block diagram of the mode selector ...... 29
4.4: The detail block diagram of the automatic mode selector ...... 30
4.5: The controller ...... 33
4.6: The state diagram of the controller ...... 33
viii 4.7: Waveforms of the control signals ...... 34
4.8: Bit serial adder ...... 35
4.9: Waveforms for the inputs and outputs of the bit serial adder ...... 36
4.10: Proposed bit serial signed magnitude comparator ...... 37
4.11: Comparison decoder logic ...... 41
4.12: Simulation results of the automatic mode control at nominal temperature ...... 44
ix LIST OF TABLES
Table Page
2.1: Summary of current reference circuits present in the literature……………...... 14
3. 1: The transistor sizes for the proposed reference current generator for Mode 1, Mode 2, and Mode 3 ...... 22
3.2: The bias current at nominal and process corners over temperature for three different modes ...... 24
4.1: The transistor sizes for an I-V converter ...... 27
4.2: Truth table of logic in bit serial adder ...... 35
4.3: Truth table for the bit logic conventional unsigned magnitude bit serial comparator ...... 37
4.4: Truth table for the comparison decoder ...... 40
4.5: The reference voltage and current under different process corners over temperature for three different modes ...... 43
4.6: The output values of each block for nominal corner at room temperature ...... 43
x CHAPTER I
INTRODUCTION
1.1 Motivation
Reference current generators are one of the most widely used building blocks for
analog integrated circuits including amplifiers, filters, and data converters [1]-[3]. For application in harsh environment electronics such as the high temperature sensor interfaces, the reference current source should be insensitive to both temperature and process variations. So far, there have been a number of research efforts that generate temperature insensitive reference currents. These include bandgap voltage reference [4],
MOS transistor zero temperature coefficient (ZTC) point [5], [6], and MOS transistor based current generators [7], [8]. Although the above works can obtain temperature insensitive reference currents, the performance is degraded by process variations.
The conventional CMOS reference current generator proposed in [9] is designed using a CMOS Widlar current source, current mirrors and a passive resistor. For this approach, the accuracy of the reference current depends on the absolute value of the resistor. A slight change in the resistor value can degrade the performance over
1 temperature and process corners. The output current of this conventional CMOS
reference current generator varies (worst case up to 50%) over the temperature range
from 25°C to 125°C even under nominal corner, which will critically limit the
performance of analog circuits for high-temperature applications. As a result, a
temperature and process insensitive reference current generator is highly demanding.
In this work, first a temperature and process insensitive CMOS transistor only
reference current generator is designed to produce a constant reference current of 20 A
over the temperature range from 25°C to 125°C. This is realized by replacing the passiveµ
resistor used in the conventional CMOS reference current generator circuit with a
transistor resistor. In addition, the gate voltage of the transistor resistor is controlled so
that the current is insensitive to temperature variation. By doing this, the temperature
coefficient of the gate bias voltage is balanced with the temperature coefficient of the
output current, thus leading to a temperature insensitive reference current.
Furthermore, in order to maintain the temperature insensitivity over different process corners, the gate bias generator for the transistor resistor is designed for nominal (Mode
1), strong (Mode 2) and weak (Mode 3) corners, where an optimum gate voltage will be
selected. This will make the output current closest to 20 A even under process
variations. Once the reference current generator has been fabricatedµ into an integrated
circuit, the default mode will be Mode 1, where the current can be measured through an
external pin. If the measured current is less than the nominal value, which indicates a
weak corner, bias voltage generator Mode 3 will be selected. On the other hand, if the
measured current is larger than the nominal value which indicates a strong corner, bias
voltage generator Mode 2 will be selected. By choosing an appropriate mode for specific
2
process corners, a process insensitive reference current can be obtained. The gate bias
generators for Mode 1, Mode 2 and Mode 3 will be manually selected by controlling the
switches.
An automatic mode selector design is presented to automatically select the optimum
gate bias generator depending on the process corner. The design consists of three
reference current generators. The three reference current generators that create the three
different reference currents. Digital representations of the three currents are compared to
determine which of the three is closest to the desired value. A digital code is produced to
control the switches that would otherwise have been controlled manually; these switches
provide the best of the three gate bias voltages to the final reference current generator that
produces the temperature and process insensitive reference current.
1.2 Goal of thesis
The goal of the thesis is to design a CMOS only reference current generator which will enable low power consumption and less silicon area compared to circuits using BJTs,
diodes and resistors.
The proposed reference current generator with manual mode and automatic mode
selector built on-chip is designed using 0.5 µm CMOS SOI process. The operation of the
circuits is verified through circuit simulations under nine different process corners. For
the proposed reference current generator circuit, a temperature coefficient of 39 ppm/°C
is achieved in the range between 25°C and 125°C for the nominal process corner with a
constant reference current of 20 µA. The worst-case variations for Mode 2 and Mode 3
are 300 ppm/°C and 520 ppm/°C, respectively. To the best of our knowledge, the best
3 temperature coefficient previously achieved with a MOSFET only circuit is 108 ppm/°C
[3] at nominal process corner over temperature range from -20 to 100 °C.
1.3 Organization of this thesis
The remaining part of this thesis is divided into four chapters. Chapter II presents the previous work related to reference current generators available in the literature. Chapter
III shows the design of the temperature and process insensitive reference current generator with the manual mode control. Chapter IV describes the automatic mode selector design. In Chapter V, the conclusion and possible further work are presented.
4 CHAPTER II
LITERATURE REVIEW
This chapter describes the basic techniques of the conventional reference current
generators including the bandgap reference, the MOSFET ZTC point and the CMOS
reference current generator. In addition, the design tradeoffs for the existing reference current generator topologies are analyzed.
2.1 Bandgap reference
The bandgap reference is the most general technique used for the generation of temperature insensitive reference voltage. This reference voltage is then converted into the reference current using a voltage to current converter. The temperature insensitive
reference voltage can be obtained by combining the negative temperature coefficient
(TC) terms and the positive TC terms with proper weights in order to achieve a zero TC
[10].
Figure 2.1 shows the block diagram of a temperature insensitive reference current
generator based on the bandgap reference technique. The negative TC term is generated from the forward biased base-emitter voltage VBE of a bipolar junction transistor (BJT),
5
Figure 2.1: Block diagram of reference current generator based on bandgap reference technique and the positive TC is obtained from ΔVBE the difference between the base-emitter
voltages of two BJTs operating under unequal collector currents. Therefore, a
temperature insensitive voltage can be obtained by the weighted sum of VBE and ΔVBE.
These voltages are then converted into respective currents, and these currents are added
together to obtain a temperature insensitive reference current.
Figure 2.2 is an example of a reference current generator based on the bandgap reference technique [4]. The voltages at node x and node y will be identical due to the negative feedback operation, and is equal to VEB1 which has the negative TC. Because of
the feedback loop formed by the Opamp, R2, R3, Q1, Q2, M3 and M4, the voltage across R1
is equal to the difference between the VEB1 and VEB2 that is ∆VEB which has a positive TC.
In this case, the base-emitter junction area of Q1 and Q2 will have a ratio of 1:N. As a
result, the current flowing through R1 is given as ∆VEB/R1, which will have positive TC.
Furthermore, the current through R2 and R3 is given as VEB1/(R2+R3). The current I is the
sum of the current flowing in R1 and the current flowing in R2 and R3. When these two currents are added with the proper resistor ratio (R2+R3)/ R1, the negative TC of VEB1 can
be cancelled out with the positive TC of ∆VEB, and the circuit generates a temperature insensitive reference current that is expressed as
6
Figure 2.2: Typical low voltage bandgap reference current using an opamp
1 R + R = + 2 3 ∆ ⋅ I REF V EB1 V EB (2.1) R2 + R3 R1
Finally, the current I is mirrored through M3 and M4 to generate the reference current
IREF. The sizes of M3, M4 and M5 are identical to keep the same current mirroring ratio.
The bandgap reference circuit used to generate a reference current includes BJTs and resistors in addition to MOSFETs. BJTs require a more complicated fabrication process and resistors require larger area in layout. This is the drawback of generating a reference current based on the bandgap reference technique.
2.2 MOSFET ZTC point
In this case, the temperature insensitive reference current generator is obtained by operating the MOSFET at the Zero Temperature Coefficient (ZTC) point. The concept of the ZTC point can be understood by considering the drain current of an NMOS transistor operating in the saturation region
7
Figure 2.3: Trans-conductance characteristics of a transistor showing the ZTC point [11]
1 2 W I = µ C (V −V ) . (2.2) D 2 n OX GS t L
where µn is the electron mobility, COX is the gate capacitance per unit area, VGS is the
gate-to-source voltage, Vt is the threshold voltage and (W/L) is the aspect ratio of the
channel. The drain current shown in eqn 2.2, depends mainly on the threshold voltage
and the mobility which are temperature dependent parameters. Both the threshold voltage
and the mobility show negative TC. The ZTC point is the bias point where there is a mutual compensation between the temperature effects on the mobility and the threshold voltage [11].
The ZTC point of a transistor can be obtained by plotting its trans-conductance characteristics (ID vs. VGS) at different temperatures. Figure 2.3 shows the trans-
conductance characteristics for an NMOS transistor at different temperatures. All the
curves that intersect at a particular point called the ZTC point of the MOS transistor. It
can be observed that at lower VGS values, the current has a positive TC. However, for
8
Figure 2.4: Proposed 10 bit gate-controlled DAC
higher VGS values, the current has a negative TC. As a result, a temperature insensitive current can be obtained by operating the MOSFET at the ZTC point.
Figure 2.4 is an example of a circuit using the MOSFET ZTC point technique to generate temperature insensitive binary weighted gate controlled reference current. This is used as a part the temperature-insensitive gate-controlled weighted current digital-to-
analog converter (DAC) proposed in [6]. The design consists of CMOS inverters to
switch the gate voltage of a set of binary-weighted PMOS current sources (M1, M2…Mn).
Temperature-insensitive reference current is obtained by biasing the gate voltage of
the PMOS current sources at the ZTC point. The PMOS current sources generate the
current that varies with the gate to source voltage. Therefore, by fixing the VBIAS to the
ZTC voltage of the PMOS current sources, the bit currents in the gate-controlled DAC
will be insensitive to temperature variation.
A drawback of this design approach is that the ZTC point of the MOSFET is not easy
to find and it also changes with the process corners. It is very difficult to handle the ZTC
9 point at different process corners for a circuit to generate a temperature and process insensitive reference current.
2.3 CMOS reference current generator
The conventional CMOS reference current generator circuit is shown in Figure 2.5 [8].
The reference current is generated by the CMOS Widlar current source M1, M2 and R5, and copied to the other branch by current mirror M3 and M4, where the current is given by
I = (VGS1 −VGS 2 ) R5 . (2.3)
In addition, assuming the threshold voltages are identical Vt1 =Vt2 (owing to the SOI technology), (W/L)2 =2(W/L)1, and the W/L ratio of M3 and M4 are identical, the reference current can be re-written as
2 2 1 1 1 I = 21− (2.4) µ 2 R5 pCOX (W L)1
where µp is the mobility and COX is the gate capacitance per unit area. Since µp is a temperature-dependent parameter that decreases with temperature, the reference current I will increase with temperature. Also, the mobility will change with different process corners, which makes the reference current sensitive to process variations.
Figure 2.6 shows the current I of the conventional circuit for different process corners over the temperature range of 25°C ~ 125°C, where the reference current increases with temperature. This is due to the mobility reduction with increasing temperature. Mobility
10
Figure 2.5: Conventional CMOS reference current generator
Figure 2.6: Reference current for conventional circuit at different process corners over temperature
11
has a negative TC [2]. Moreover, the reference current varies (worst case up to 50%) over
temperature for all process corners. This is the drawback of the conventional reference
current generator, which will critically limit the performance of analog circuits for high-
temperature applications.
The CMOS reference current generators use only MOSFETs. As a result, CMOS
reference current generators occupy less area, are simple and easy to design, and can generate process and temperature insensitive reference current.
Figure 2.7 is an example of a CMOS reference current generator proposed in [8] that can
generate temperature insensitive reference current. The circuit includes a current mirror
M3-M4 and the CMOS Widlar current source M1, M5, M2, and R1, where the difference
compared to conventional CMOS Widlar current source is the additional transistor M5.
The reference current I is generated in the left branch and copied to the right branch by
the current mirror M3 and M4, (with aspect ratio of 1: m), where the voltage drop across
R1 is given by
Figure 2.7: Temperature compensated CMOS current reference
12
mR1I = VGS1 +VGS5 −VGS 2 . (2.5)
Furthermore, assuming the threshold voltage of M1 and M2 are identical, the above eqn
2.5 can be rewritten as
I 1 1 m mR I = + − +V (2.6) 1 β α Tn5 n0 α1 α 5 2
where βn0 = µnCOX/2, αi is the aspect ratio of the transistors and VTn5 is the threshold
voltage of M5. Therefore, the voltage across the resistor R1 is given by the sum of the
overdrive voltages of transistors M1, M2 and M5 that has a positive TC and the threshold
voltage of M5 that has a negative TC. Neglecting the TC of R1, if the positive TCs from
the overdrive voltages and the negative TC from the threshold voltage are properly
weighted, a reference current with zero TC can be obtained.
This design still has a disadvantage of including a resistor, and may not operate as
designed at process corners.
2.4 Summary of the previous work
The summary of the current reference circuits for the above techniques explained in
this chapter are shown in Table 2.1. All the designs in the literature [1]-[8] consist of
MOSFETs along with either BJTs or resistors and are simulated in a wide temperature
range. The designs proposed in [1] and [2] use BJTs and resistors, and those in [4], [5],
[7], and [8] use resistors, along with the MOSFETs, which can lead to fabrication and layout disadvantages. Furthermore, the performance of the reference current generator
13
Table 2.1: Summary of current reference circuits present in the literature
Operating Temperature
Design Basic technology Temperature Range Coefficient
(°C) (ppm/°C)
[1] CMOS current generator 0 to 80 375
[2] CMOS current generator -20 to 80 600
[3] CMOS current generator -20 to 100 108
[4] Bandgap current reference -20 to 100 45
[5] MOSFET ZTC point -20 to 80 46
[6] MOSFET ZTC point 27 to 125 45
[7] CMOS current generator 0 to 75 226
[8] CMOS current generator -30 to 100 130
depends on the accuracy of the resistor values, which vary over process corners. The reference current generators in [3] and [6] are realized using only MOSFETs, and has temperature coefficient of 108 ppm/°C and 45 ppm/°C, respectively, but the designs are sensitive to process variations as these are only good for nominal process conditions.
2.5 Summary of contribution
A detailed procedure for the design of a temperature and process insensitive CMOS only reference current generator is proposed to produce a reference current of 20μA. The temperature coefficient obtained at nominal process is 39 ppm/oC over the operating temperature range of 25oC to 125oC.
14
This thesis presents a detailed step-by-step procedure for a temperature insensitive reference current generator at nominal process. The main idea of the design is to replace
the passive resistor used in the conventional CMOS reference current generator circuit
with a transistor resistor. By design, the temperature variations of the gate bias voltage of
this transistor are balanced with the temperature variations of the output current resulting
from fluctuations in mobility and threshold voltage. The same procedure is followed to
obtain a temperature insensitive reference current generator for strong corners and weak
corners. This leads to a temperature insensitive reference current for three separate modes
of operation. The operating mode is manually selected by the control switches to
minimize the current variation under different process corners. As an extension of the
manual mode selector, the design of an automatic mode selector that automatically
selects the optimum gate bias generators to minimize the current variation under different
process corners is realized. The proposed reference current generator is simulated under
different process corners in the temperature range from 25°C and 125°C. Using the mode
control circuits for different process corners, a worst-case temperature coefficient of 520
ppm/°C and 300 ppm/°C are obtained for the weak and the strong corner, respectively.
15
CHAPTER III
PROPOSED CMOS ONLY REFERENCE CURRENT GENERATOR
In the previous chapter, various designs of reference current generators from the
literature were presented. This chapter presents the design of the proposed temperature
and process variation insensitive CMOS only reference current generator that can operate
in the temperate range from 25°C to 125°C.
3.1 Temperature insensitive operation
Figure 3.1 shows the proposed reference current generator where the passive resistor
is replaced with a PMOS transistor and its gate bias generator [14]. The gate bias generator includes one PMOS transistor M8, and two NMOS transistors M6 and M7,
where M8 copies the reference current I (M1 and M8 are matched), and the diode-
connected transistors M6 and M7 generate the gate voltage VX. All the transistors operate
in the saturation region except M5, which operates in the linear region as a resistor. The resistance of M5 is given by
1 R = . (3.1) 5 µ () ( −VVLWC ) p OX 5 GS t55
16 Figure 3.1: The proposed current generator circuit
In order to obtain a temperature insensitive reference current, the resistance of M5 should increase with temperature, which will compensate the negative TC of the mobility reduction (eqn 2.3 and Figure 2.4). As a result, to make R5 increase with temperature,
|VGS5| should decrease with temperature and again VX should increase with temperature, since VGS5 = VX –VDD. The gate bias VX is generated by the sum of VGS6 and VGS7, which can be written as
2I 2I VX = Vt6 ++ +Vt7 . (3.2) µ µ n OX ()LWC 6 n OX ()LWC 7
Assuming the threshold voltages of M1 and M2 are identical and (W/L)2 =2(W/L)1, the reference current of the proposed circuit is given by
17 2 2 1 2 (W L) = − µ ( − ) 5 I 21 pCOX V GS5 V t5 . (3.3) 2 (W L)1
In order to obtain a temperature insensitive current, the TC of I should equal zero,
which is given by the relationship
∂I ∂I ∂µ p ∂I ∂V ∂I ∂V = + GS5 + t5 = 0 , (3.4) ∂ ∂µ ∂ ∂ ∂ ∂ ∂ T p T VGS5 T Vt5 T
where ∂µp/∂T is the TC of the mobility, and ∂VGS5/∂T and ∂Vt5/∂T are the TC of the gate
to source voltage and the threshold voltage of M5. By obtaining the partial derivatives of
the reference current with respect to mobility µp, VGS5 and Vt5, eqn 3.4 can be re-written
as
∂µ ∂I p ∂VGS5 ∂Vt5 = K (VGS5 −V t5 ) + 2µ p − 2µ p = 0 (3.5) ∂T ∂T ∂T ∂T
2 2 1 C (W L) (V −V ) = − OX 5 GS5 t5 where K 21 . (3.6) 2 (W L)1
Since K is a common term, eqn 3.5 can be simplified as
∂µ p ∂VGS5 ∂Vt5 (VGS5 −V t5 ) + 2µ p − 2µ p = 0 . (3.7) ∂T ∂T ∂T
Solving eqn 3.7 for ∂VGS5/∂T gives
∂V ∂V (V −V ) ∂µ p GS5 = t5 − GS5 t5 . (3.8) ∂T ∂T 2× µ p ∂T
18
Furthermore, by setting |VGS5| = 1.2V (this value is set in the design to make M5
-6 2 operate in the linear region) and replacing ∂µp/∂T = 27×10 cm /Vs°C, ∂Vt5/∂T =
-3 -3 2 1.04×10 V/°C, Vt5 = 0.63V and µp = 6.1×10 cm /Vs in eqn 3.8, leads to
-3 ∂VGS5/∂T = 0.22×10 V/°C (3.9)
where the values of µp, Vt5, ∂µp/∂T and ∂Vt5/∂T are obtained from the nominal process
corner circuit simulations with temperature range between 25°C to 125°C. This TC of
VGS5 is a design requirement that will enable zero TC for I. However, since the gate to
source voltage of M5 is given by
VGS5 = VX −VDD (3.10)
and differentiating VGS5 with respect to the temperature leads to
∂VGS5 ∂T = ∂VX ∂T (3.11)
where the power supply voltage VDD is assumed as a constant. As a result, to obtain a temperature insensitive reference current, the TC of VX should be chosen according to the
required TC of VGS5. Using eqn 3.2, the TC of VX can be written as
∂V ∂V ∂µ ∂V ∂V ∂V ∂V X = X n + X t6 + X t7 . (3.12) ∂T ∂µ ∂T ∂V ∂T ∂V ∂T n t6 t7
Also from eqn 3.2, the partial derivative of VX with respect to Vt6 and Vt7 are unity.
That is
∂VX ∂Vt6 = 1 (3.13)
∂VX ∂Vt7 = 1. (3.14)
19
In addition, the partial derivative of VX with respect µn is given by
∂V −1 1 2I 2I X = + . (3.15) 3 ∂µn 2 COX (W L) COX (W L) µn 6 7
By replacing the TC terms in eqn 3.12 with eqn 3.13, 3.14 and 3.15, the TC of VX can
be rewritten as
∂µ ∂ ∂ ∂V −1 1 2I 2I n Vt6 Vt7 X = + × + + , (3.16) 3 ∂ ∂ ∂ ∂T 2 COX (W L) COX (W L) T T T µn 6 7 where the reference current I is set to 20 µA, and the following parameters are set based
-3 2 2 on the nominal process corner simulation results: µn = 27×10 cm /Vs, COX = 3.6 fF/µm ,
-3 2 -3 ∂µn/∂T = 0.147×10 cm /Vs°C, ∂Vt6/∂T = ∂Vt7/∂T = 1.33×10 V/°C. In addition, based
-3 on eqn 3.11 and eqn 3.13, the TC of VX should be set to 0.22×10 V/°C to enable a
temperature insensitive reference current I. Therefore, by replacing each term in eqn 3.16
with the above values, and assuming that M6 and M7 are identical, we can compute the
aspect ratios (W/L)6 and (W/L)7 that will enable zero TC for I as
(W/L)6 = (W/L)7 = 1.45. (3.17)
3.2 Process insensitive operation
The proposed temperature insensitive reference current generator is optimized for
nominal current of 20 µA. However, under different process corners, the temperature
insensitivity will degrade, as the current deviates from the nominal value. Therefore, we
need different sets of gate bias generators optimized for different process corners.
Although it is impossible to cover all the process corners, process corners can be divided
20
Figure 3.2: Gate bias circuit for different process corners into three categories; nominal, strong and weak. Strong corners will lead to larger current whereas weak corners will lead to smaller current than nominal. As a result, adding two additional gate bias generators for strong and weak corners will make the referencecurrent close to the nominal value that can reduce the performance degradation caused by process variations. Figure 3.2 shows the gate bias circuit for nominal (Mode
1), strong (Mode 2) and weak (Mode 3) corners which can be selected by the control switches S1, S2 and S3. The tuned value of M6 and M7 is (W/L)6 = (W/L)7 = 2, which simulation shows to give less current variation over temperature than the ratio of 1.45 calculated from eqn 3.17. The inaccuracy in the eqn 3.17 results from the use of simplified MOSFET models in the derivation, and from the use of approximations for the values of µn, COX, ∂µn/∂T, ∂Vt6/∂T and ∂Vt7/∂T in the calculation. For Mode 2 and Mode 3, the sizes of the diode connected transistors are set to (W/L)9 = (W/L)10 = 1 and (W/L)12 =
(W/L)13 = 4, respectively. The Mode 3 bias circuit will lower the VX level for weak
21 corners, whereas the Mode 2 bias circuit will raise VX for strong corners, making the reference current closer to the nominal value under different process corners. The tuned sizes lead to VX of 1.3V for Mode 1 and 1.5V for Mode 2 and 1.1V for Mode 3.
Once the reference current generator has been fabricated into an integrated circuit, the default mode will be Mode 1, where the current can be measured through an external pin.
If the measured current is larger than nominal, which indicates a strong corner, bias voltage generator Mode 2 can be selected. On the other hand, if the measured current is less than nominal, which indicates a weak corner, bias voltage generator Mode 3 can be selected. By choosing an appropriate mode for specific process corners, a process insensitive reference current can be obtained. An appropriate threshold between the nominal and weak may be about 18.7 µA, approximately half way between the nominal current and the largest weak current. Similarly an appropriate threshold between nominal and strong may be about 21.9 µA. Table 3.1 shows the transistor sizes for the proposed reference current generator for Mode 1, Mode 2, and Mode 3.
Table 3. 1: The transistor sizes for the proposed reference current generator for Mode 1, Mode 2, and Mode 3
Transistor Size(W/L) M1 3.2/1 M2 6.4/1 M3 and M4 1.2/0.8 M5 3.1/1 M6 1.6/0.8 M7 1.6/0.8 M8 3.2/1 M9 2/2 M10 2/2 M11 3.2/1 M12 8/2 M13 8/2 M14 3.2/1
22
3.3 Simulation results
The proposed reference current generator circuit is designed using CMOS 0.5 µm
SOI technology with supply voltage of 3.3V, and the operation is verified through circuit level simulations. Figure 3.3 shows the reference current with temperature between 25°C and 125°C for the nominal process corner. The reference current varies between 20.37
µA and 20.449 µA within the temperature range. This leads to a TC of 39 ppm/°C.
Table 3.2 shows the minimum and maximum reference current within the temperature range of 25°C to 125°C for nine different process corners. Process corners for which both
PMOS and NMOS devices are fast are strong corners, with currents above 20 µA; those for which both PMOS and NMOS devices are slow are weak corners. The “skewed” process corners (with combinations of fast and slow together) may be weak or strong, depending on whether the fast or slow devices are depart more from the nominal characteristics. For example, the fast N slow P process corner is strong because the N devices are further from the nominal than the P devices are, whereas the slow P fast N corner is weak because the opposite is true.
The variation (ppm/°C) is obtained from the difference between the maximum and the minimum current within the temperature range of 100°C. It is clearly shown that Mode 2 and Mode 3 gives less current variation close to nominal current (20 µA) for strong and weak corners with respect to Mode 1. The worst-case variation for Mode 2 and Mode 3 are 300 ppm/°C and 520 ppm/°C respectively. However, without the mode control the maximum current variation is 900 ppm/°C. For slow (P) fast (N) corner, although the current is less than the nominal value for Mode 1, the current variation is less than the
23 Mode 3 (300 ppm/°C for Mode 1 and 520 ppm/°C for Mode 3). However, the absolute current is close to the nominal value, which justifies using Mode 3. The temperature coefficient of the reference current is calculated as
ppm/°C = 6 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚−𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 10 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 ∆𝑇𝑇 Table 3.2: The bias current at nominal and process corners over temperature for three different modes
Mode 1 Mode 2 Mode 3
No. Process corners Min Max ppm/°C Min Max ppm/°C Min Max ppm/°C (µA) (µA) (µA) (µA) (µA) (µA)
1 Nominal 20.37 20.449 39 11.98 12.38 318 22.8 24.78 800
2 Slow(N)slow(P) 12.66 13.8 900 7.17 8.17 1220 15.49 15.58 58
3 Fast(N)fast(P) 30.82 29.2 520 18.64 18.07 300 32.6 37.34 1270
4 Slow(N)fast(P) 16.3 17.3 600 8.895 9.83 950 19.91 20.38 230
5 Fast(N)slow(P) 24.76 23.9 340 15.51 15.33 120 26.1 29.416 1130
6 Slow(P)slow(N) 12.03 13.06 790 7.06 7.945 1100 14.65 14.74 61
7 Fast(P)fast(N) 31.63 29.93 540 17.81 17.44 210 33.95 38.91 1270
8 Slow(P)fast(N) 14.76 15.2 300 8.75 9.3 550 17.15 18.1 520
9 Fast(P)slow(N) 28 27.48 186 16.3 16.55 150 30.5 33.86 990
Figure 3.3: Reference current with temperature for nominal corner
24
CHAPTER IV
AUTOMATIC MODE SELECTION DESIGN
In the previous chapter, a temperature and process insensitive CMOS only reference current generator that can operate in the temperature range from 25°C to 125°C was discussed. To achieve a process insensitive reference current generator, a gate bias generator circuit for nominal (Mode 1), strong (Mode 2) and weak (Mode 3) corners were designed. These gate bias generators were manually selected by the control switches S1,
S2 and S3 to obtain a constant current over temperature from 25°C to 125°C. As an extension to the manual mode selection, a design for a block that performs automatic mode selection is presented in this chapter.
4.1 The automatic mode selection operation
In the previous chapter, the gate bias generators for Mode 1, Mode 2 and Mode 3 were manually selected by controlling the switches S1, S2 and S3. In this chapter, the switches are controlled by the automatic mode selector to connect the gate bias generator for each mode with the reference current generator. The overall block diagram of the automatic mode selector is shown in Figure 4.1, and includes a set of I-V converters, a
25 Figure 4.1: Block diagram of the overall automatic mode selector mode selector, and the reference current generator with gate bias generators for Mode 1,
Mode 2 and Mode 3.
The additional blocks needed to replace the manual mode selection with automatic mode selection are three reference current generators, three I-V converters and mode selector block. The three reference current generators use the three bias voltages to create three different reference currents, which are then converted to voltages by three I-V converters. The mode selector block then converts those three voltages to digital form, and performs computations to determine which of the three reference currents is closest to the desired value. Finally, the mode selector block produces a code used to control the switches that would otherwise have been controlled manually; these switches provide the best of the three gate bias voltages to reference current generator 4, which produces the final reference current.
26 The reference current generators in the automatic mode selector design are identical
to the design already presented in Section 3.2. The other blocks of the automatic mode
selector design are described in the following sections.
4.2 Current to voltage (I-V) converter
Figure 4.2 shows the I-V converter along with the already presented reference current
generator and gate bias generator, using Mode 1 as an example. The transistor M15 copies
the reference current IREF and the cascode current mirror M16, M17, M18 and M19 mirrors the reference current IREF to the left branch. In this branch, the reference current is
converted to a reference voltage with a resistor R1 of 79kΩ.This is to make the reference
voltage equal to 1.58 V for reference current of 20 µA. If the reference current IREF is less
Figure 4.2: The reference voltage generator for Mode 1
Table 4.1: The transistor sizes for an I-V converter
Transistor Size(W/L) M15 1.2/0.8 M16, M17, M18 and M19 3.2/1.0
27
than 20 µA then the reference voltage will be less than 1.58 V, and if the reference
current IREF is greater than 20 µA then the reference voltage will be greater than 1.58 V.
Similar to reference generator for Mode 1, there are two more reference voltage generators for Mode 2 and Mode 3. Table 4.1 shows the sizes for the I-V converter circuit
transistors; the sizes are same for the different circuits.
In this design, the resistor R1 is an off chip resistor and in the circuit simulation, an ideal resistor was used. This resistor must maintain its nominal value only during the
automatic mode selection, which only happens at power up.
4.3 Mode selector
Figure 4.3 shows the block diagram of the mode selector. The mode selector block consists of a three-to-one analog mux, an eight-bit SAR ADC, shift registers, a controller,
three bit serial adders [12], three bit serial magnitude comparators [13] and a comparison
decoder. In this design, serial data processing has been chosen because it requires far
fewer resources (logic gates) than conventional word-level processing; computations
require more time when done one bit at a time, but the extra time does not impact this
application negatively. The controller starts by controlling the analog mux to pass the
first reference voltage through to the SAR ADC, and sending a start signal to start the
analog-to digital conversion. The reference voltages (V1REF, V2REF and V3REF) are
converted one after another from analog to an eight-bit digital format and stored in shift registers. The corresponding digital codes are denoted A, B, and C on the diagram. The error of each digital reference voltage with respect to 1.58 V is then computed; this is done by subtracting the digital code D that represents 1.58 V, 10000000, from the digital
28
Figure 4.3: The block diagram of the mode selector code for each reference voltage using the bit serial adders, to produce the difference A1,
A2, and A3. The three bit serial magnitude comparators then compare pairs of differences, to determine which one of each pair is the smallest error. The results of the three comparators are used by the comparison decoder to create a one-hot code S1 S2 S3
that indicates the reference voltage that is closest to the ideal reference voltage of 1.58
volts; this code can be used directly to control the mode switches. The controller is a
finite state machine that produces the sequence of control signals needed for the SAR
ADC, 3 to 1 Mux and shift registers, and the signal generator produces the control signals for the bit serial adders and bit serial magnitude comparators.
The SAR ADC converts the reference voltages V1REF, V2REF and V3REF into the eight-
bit digital data format (S). The shift register block stores the eight-bit data from the SAR
ADC, and converts the parallel loaded data into serial data A, B, C and D (LSB first),
where A, B, C and D correspond to V1REF, V2REF, V3REF and VREF, respectively. The
control block controls the selection signals of the analog mux, the start_ADC signal for
the eight-bit SAR ADC and the shift signal for the shift register. The analog mux selects
one of the reference voltages one by one based upon the activation of the select lines
Mux_Sel1, Mux_Sel2 and Mux_Sel3. Each output from the shift register A, B and C is
29
bit by bit added with the output D using of the bit serial adder. In two’s complement
format the value of D 10000000 may be interpreted either as (-128) or as (128). So, subtracting 10000000 (128) from the input is equivalent to adding 10000000 (-128) to it.
Figure 4.4: The detail block diagram of the automatic mode selector 30
The bit serial adder generates outputs A1 (A+D), A2 (B+D) and A3 (C+D). These outputs are compared among each other by the bit serial magnitude comparator. The
comparison decoder activates one of the control switches S1, S2 or S3 based on the outputs of the bit serial magnitude comparator.
Figure 4.4 shows the detailed block diagram of the mode selector. The input range of
the 8 bit SAR ADC is from 0.35 V to 2.8 V with mid-range of 1.58 V, where 1.58 V
corresponds to the reference current of 20 µA. When the conversion is complete, the
controller sends a parallel load signal to shift register SR1, so that the converted eight-bit
code A for the converter V1REF is stored. The controller then similarly guides the system
through conversions of V2REF and V3REF, storing the corresponding codes B and C in SR2 and SR3, respectively. The digital code D = 10000000 corresponding to the ideal reference voltage 1.58 volts is loaded in SR4. With digital codes for all three voltages
ready in the shift registers, the signal generator then guides the bit-serial logic through the process that computes the errors with respect to the ideal voltage, and finds the error of smallest magnitude. The bit serial computations are done least significant bit first. As the bits of the codes A, B, C, and D are shifted out of the shift registers and into the bit serial adders, the three bit serial adders from the differences A1=A-D, A2=B-D, and A3=C-D.
The bits of the differences proceed directly as they are produced into the bit-serial
magnitude comparators; these three comparators compare A1 and A2, A1 and A3, and
A2 and A3, respectively, producing three one-bit signals, |A1|>|A2|, |A1|>|A3| and
|A2|>|A3|. The comparison decoder activates one of the control switches S1 or S2 or S3
based on the outputs of the bit serial magnitude comparators.
31
4.3.1 The controller
Figure 4.5 shows the controller with four D flip-flops that controls the eight-bit SAR
ADC, three-to-one analog mux, and shift registers SR1, SR2, SR3 and SR4. The state diagram of the controller is shown in Figure 4.6. The controller is implemented as a shift register with the four D flip-flops with a one-hot state encoding; the state progresses through the sequence 1000, 0100, 0010 and 0001. On power on reset, the first flip-flop
will be set to 1 and other flip-flops will be set to 0, and the controller is put in the state
1000. In state 1000, the select signal of the analog mux is chosen to pass V1REF to the
SAR ADC input, and a conversion starts. Once the conversion is complete, the SAR
ADC sets the SR_load signal to 1. This signal causes the converted result to be parallel- loaded into the shift register SR1 and enables the controller to move to the next state,
0100. The next two states operate in the same way, except that the analog mux is controlled to pass V2REF and the V3REF to the SAR ADC input, and the converted results
are stored in SR2 and SR3, respectively. The input to SR4 is hard coded with the binary
code 10000000, which represents the voltage that corresponds to the current 20 A. This
code is parallel-loaded into SR4 when the SR3_load goes high in state 0010. Whenµ the
controller enters the start compare state 0001, the Shift signal goes high; as a result, the
values stored in SR1, SR2, SR3, and SR4 start simultaneously shifting out, one bit per
clock, least significant bit first, on the serial lines marked A, B, C and D, respectively.
The control signal waveforms for the SAR ADC, three-to-one analog mux and shift
registers are shown in Figure 4.7.
32
Figure 4.5: The controller
Figure 4.6: The state diagram of the controller
33
Figure 4.7: Waveforms of the control signals
4.3.2 Bit serial adder
The circuitry inside the bit serial adder is shown in Figure 4.9; it includes two flip- flops and a full adder circuit. The Add (reset_bar) signal is a control signal and the clock is the free running bit clock. When the Add signal is low, flip-flops are held in reset, ensuring that the addition stay with a carry-in of 0. When the Add signal is high, the circuitry does a one-bit addition, adding the two incoming data bits and the previous carry in flip-flop 1 to produce one bit of sum, stored in flip-flop 2, and a new carry, which replaces the previous carry in flip-flop 1. The truth table for the bit serial adder is shown in Table 4.2. On the rising edge of each clock cycle, flip-flop 1 generates the carry out (Ci) signal and gives its value as the carry in (Ci+1) signal on the next clock cycle. The
Add (reset_bar) signal is kept high for nine clock cycles by the signal generator block in order to perform an eight-bit addition.
The digital codes that are input to the bit serial adders are eight-bit unsigned codes, with values ranging from 0 to 255. Each code is added to code 10000000, which corresponds to the voltage for the ideal reference current. The code 10000000 can be interpreted as either the ideal voltage in an unsigned format, or as the complement of that
34 ideal voltage in a two’s complement format; thus, adding this code produces a signed two’s complement code that is the difference between a voltage and the ideal voltage.
Table 4.2: Truth table of logic in bit serial adder
Inputs Outputs
Ci A D Sum Ci+1
0 1 1 0 1
1 0 0 1 0
0 1 0 1 0
0 0 1 1 0
Figure 4.8: Bit serial adder
35
Figure 4.9: Waveforms for the inputs and outputs of the bit serial adder
The inputs A and D, outputs Sum (i.e A1, A2 or A3) and Cout, clock and control
signal are shown as waveforms in Figure 4.10. As can be seen on the waveform, the
output bits appear on the sum line, one bit at a time, least significant bit first. The three
errors computed by the three bit serial adders come out serially and simultaneously, and
proceed to the bit serial magnitude comparator.
4.3.3 Bit serial magnitude comparator
A conventional unsigned magnitude comparator takes two unsigned serial binary
numbers as inputs (X1 and X2) and compares the two inputs to determine whether the first input X1 is greater or smaller than the second input X2. The output is Y=’1’ if
X1>X2 and Y=‘0’ if X1≤X2. The truth table for the one bit logic inside a conventional unsigned magnitude bit serial comparator is shown in Table 4.3.
The conventional unsigned magnitude comparator cannot be directly used here, because the inputs to the comparator are not unsigned; they are in a signed, two’s complement format, and any error might be positive or negative.
36
Table 4.3: Truth table for the bit logic conventional unsigned magnitude bit serial comparator
Inputs Outputs
X1 X2 Y (X1>X2)
0 0 0
1 0 1
0 1 0
1 1 0
Figure 4.10: Proposed bit serial signed magnitude comparator
37
A magnitude comparator that can compare the magnitude of signed numbers is built, using the conventional magnitude comparator as a building block. It includes two bit serial unsigned magnitude comparators, logic gates, multiplexers and flip-flops as shown in Figure 4.10.
The design works by doing two different unsigned comparisons; comparator 1 compares A1 and A2 as if they were unsigned values, and comparator 2 compares A1 and
A2_bar, which is A2 with all of its bits complemented. The correct result when A1 and
A2 are signed two’s complement values can be derived from one of these two comparisons; the rest of the circuitry determines which one to use, modifies it as needed, and routes it to the output. Which of the four cases applies can be determined by looking at the most significant bits of the two inputs; those bits are ‘1’ if the number is negative, and ‘0’ if the number is positive. Once the eight bits of the inputs have been processed, the MSBs of the inputs A1 and A2 are in flip-flops D-FF1 and D-FF2, respectively. If these two flip-flops control two multiplexers, Mux 1, which selects the correct output from either comparator 1 or comparator 2, and Mux 2, which selects either a direct or complemented version of the comparator output. Mux 3 and DFF3 are used to transfer and hold the correct result at the output of the comparator. The transfer signal is generated from the signal generator block.
How to derive the correct result from the unsigned comparisons depends on the signs of the two inputs A1 and A2. There are four possible combinations of signs; each is considered in turn to show the required logic.
38 Case 1: A1 positive and A2 positive
If A1 and A2 are both positive, comparator 1 produces the correct result, because
positive values have the same binary code whether they are expressed in a signed two’s
complement code or an unsigned code.
Case 2: A1 negative and A2 negative
Two negative numbers can be successfully compared using an unsigned comparator
by realizing that the one of larger magnitude has smaller magnitude if interpreted as an
unsigned number. As a result, the correct output can be found by simply complementing
the output of comparator 1.
Case 3: A1 negative and A2 positive
In this case, comparator 2 is used. All the bits of A2 are complemented before
entering comparator 2; this serves to (approximately) invert A2, so that it has the same
magnitude, but is negative. This makes case 3 just like case 2, with two negative inputs to
an unsigned comparator. Accordingly, the output of comparator 2 should be
complemented to find the correct output.
Case 4: A1positive and A2 negative
For this case, comparator 2 is used. Here, A2 is complemented, so that both inputs to
comparator 2 are positive, and can be treated as unsigned numbers; accordingly, the
output of comparator 3 can be directly used as the correct output.
4.3.4 Signal generator
The signal generator block consists of flip-flops and logic gates that generate Add,
Compare and Transfer signals using the clock signal. The Add signal controls the bit
39
serial adder and the Compare and Transfer signals control the bit serial signed/unsigned magnitude comparator.
4.3.5 Comparison decoder
The comparison decoder takes the three outputs |A1|>|A2|, |A1|>|A3| and |A2|>|A3|
from the signed magnitude comparators, and uses them to determine which of the three
errors is smallest; it produces a one-hot code V1 V2 V3. The logic for the comparison
decoder is shown in Figure 4.11, and the truth table is shown in Table 4.4. If A1 is
smaller than A2 and A3 then the decoder gives an output ‘1’ for V1. Similarly, if A2 is
smaller than A1 and A3 then the decoder gives an output ‘1’ for V2, and if A3 is smaller
than A1 and A2 then the decoder gives an output ‘1’ for V3. Two input combinations
‘010’ and ‘101’ for the comparison decoder cannot happen; accordingly, they were used
as “don’t cares” when designing the logic. For instance, the input ‘010’ states that A1 is
less than A2, A1 is greater than A3 and A2 is less than A3: this is not possible.
Table 4.4: Truth table for the comparison decoder
|A1|>|A2| |A1|>|A3| |A2|>|A3| V1 V2 V3
0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 X X X
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 X X X
1 1 0 0 1 0
1 1 1 0 0 1
40
Figure 4.11: Comparison decoder logic
4.4 Simulation results
The proposed I-V converter and automatic mode selector circuits are designed using
CMOS 0.5 µm SOI technology with a supply voltage of 3.3V. The operation of the circuit is verified through circuit level simulations for temperature range between 25°C and 125°C under different process corners. From the circuit level simulation, the automatic mode selector design generates the reference voltage and current under process corners for different modes at temperature 25°C and 125°C and the simulation results tells how much the reference current and voltage varies over temperature range 25°C to
125°C. Table 4.5 shows the reference voltage and current under different process corners over temperature for three different modes. The highlighted grey parts in the Table 4.5 are the currents closest to 20 µA between the Mode 1, Mode 2 and Mode 3 for a particular process corner and temperature which has been selected by the comparison decoder.
For the nominal corner at room temperature, the reference voltages 1.61 V, 1.96 V and 0.95 V are obtained by the I-V converter for Mode 1, Mode 2 and Mode 3,
41
respectively. These voltages are then converted in to 8 bit digital outputs 10000010,
01000010 and 10011101 through the 8 bit SAR ADC. The outputs are loaded in the shift
register in the original format, and shifted out LSB first. The output from the shift register
SR1, SR2 and SR3 are A (01000001), B (01000010) and C (10111001), respectively.
These outputs from the shift registers are subtracted by hard coded input D (00000001)
using the bit serial adder. The outputs of the bit serial adders are A1 (01000000), A2
(010000011) and A3 (10111000). The output A1 (01000000) is obtained when A is
subtracted with D (i.e., 01000001 – 00000001= 01000000). Similarly, the outputs A2 and
A3 are obtained. The difference values A1 (2), A2 (194) and A3 (29) are unsigned binary
numbers from the bit serial adders. These values are compared using the proposed bit
serial magnitude comparator to find the smallest difference (i.e., the value is closer to the
hard coded input in the shift register SR4). The inputs of the proposed bit serial
magnitude comparator A1 and A2, A1 and A3 and A2 and A3 follows the cases 4, 1 and
3, respectively.
A comparison decoder picks the smallest difference output value from the bit serial
magnitude comparator. The smallest difference value is obtained when the reference
voltage 1.61 V is subtracted with the hard coded input 1.58 V. Table 4.6 shows the output
value of each block for the nominal corner at room temperature and Figure 4.12 shows
the simulated result of the automatic mode selector at nominal corner. Figure 4.12 shows
the simulation result at nominal corner and room temperature when the switch S1 is selected that activates the reference current generator (RCG) for Mode 1 and generates an
output reference current of 20.37 µA. Accordingly, the automatic mode selector is
42
simulated at 25°C and 125°C for different process corners where the current closest to the
20 µA is activated by the switch S1, S2 or S3.
Table 4.5: The reference voltage and current under different process corners over temperature for three different modes
At 25°C At 125°C
Process corners Mode 1 Mode 2 Mode 3 Mode 1 Mode 2 Mode 3 VREF µAmp VREF µAmp VREF µAmp VREF µAmp VREF µAmp VREF µAmp Nominal 1.61 20.37 0.95 11.98 1.96 24.78 1.61 20.449 0.98 12.38 1.80 22.8
Slow(N)slow(P) 1.00 12.66 0.57 7.17 1.23 15.58 1.09 13.8 0.65 8.17 1.22 15.49
Fast(N)fast(P) 2.43 30.82 1.47 18.64 2.95 37.34 2.31 29.2 1.43 18.07 2.58 32.6
Slow(N)fast(P) 1.29 16.3 0.70 8.895 1.61 20.38 1.37 17.3 0.78 9.83 1.57 19.91
Fast(N)slow(P) 1.96 24.76 1.23 15.51 2.32 29.416 1.89 23.9 1.21 15.33 2.06 26.1
Slow(P)slow(N) 0.95 12.03 0.56 7.06 1.16 14.74 1.03 13.06 0.63 7.945 1.16 14.65
Fast(P)fast(N) 2.50 31.63 1.41 17.81 3.07 38.91 2.36 29.93 1.38 17.44 2.68 33.95
Slow(P)fast(N) 1.17 14.76 0.69 8.75 1.43 18.1 1.20 15.2 0.73 9.3 1.35 17.15
Fast(P)slow(N) 2.21 28 1.29 16.3 2.67 33.86 2.17 27.48 1.31 16.55 2.41 30.5
Table 4.6: The output values of each block for nominal corner at room temperature
Signal Result VREF 1.58 V V1REF 1.61 V V2REF 0.95 V V3REF 1.96 V A 10000010 B 01000010 C 10011101 D 10000000 A1 00000010 A2 11000010 A3 00011101 |A1|>|A2| 0 |A1|>|A3| 0 |A2|>|A3| 1 V1 1 V2 0 V3 0
43
Figure 4.12: Simulation results of the automatic mode control at nominal temperature
44
CHAPTER V
CONCLUSION
5.1 Summary
This thesis presents the design of a temperature and process insensitive CMOS only
reference current generator. The proposed reference current generator consists of a
conventional CMOS Widlar current source, in which the passive resistor is replaced with a transistor resistor. The gate voltage of the transistor resistor is provided by a gate bias generator that makes the output current insensitive to temperature variation. Furthermore, to achieve a process insensitive reference current, three separate gate bias generator circuits for nominal, strong and weak corners were designed. These gate bias generators are manually selected by the control switches to minimize the current variation under different process corners. As an extension of the manual mode selector, the design of an
automatic mode selector that automatically selects the optimum gate bias generators to
minimize the current variation under different process corners is realized. The proposed
reference current generator can be used for high temperature sensor interface applications
that include amplifiers, oscillators, filters and data converters. The proposed reference
current generator is designed using 0.5 µm CMOS SOI technology, and the operation has
45 been verified through circuit level simulations. The result show for a reference current of
20 µA, a temperature coefficient of 39 ppm/°C is achieved in the temperature range
between 25°C and 125°C for the nominal process corner. Using the mode control circuits
for different process corners, a worst-case temperature coefficient of 520 ppm/°C and 300 ppm/°C are obtained for the weak and the strong corner, respectively.
5.2 Future work
The performance of the reference current generator could be improved by replacing
the gate bias generators with a more sophisticated circuit. The automatic mode selector
circuitry can also be designed in a simpler manner by using only one reference current
generator instead of redundant reference current generators. This will lead to simple
digital logic circuits.
The layout of the manual mode selection design was sent to foundry for IC
fabrication and it needs to be tested.
Furthermore, the automatic mode selection design should be laid out and sent to the
foundry for IC fabrication and can be tested for performance evaluation. This will help to
evaluate the performance of the proposed design under an actual process condition.
Finally, to be updated with the technology, the proposed design can be implemented
with a more advanced CMOS process.
46 BIBLIOGRAPHY
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