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A Temperature and Process Insensitive Cmos Only Reference A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE CURRENT GENERATOR A Thesis Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Master of Science Shivasai Bethi December, 2014 A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE CURRENT GENERATOR Shivasai Bethi Thesis Approved: Accepted: ________________________ ________________________ Advisor Department Chair Dr. Kye-shin Lee Dr. Abbas Omar ________________________ ________________________ Committee Member Dean of the College Dr. Joan E. Carletta Dr. George K. Haritos ________________________ ________________________ Committee Member Interim Dean of the Graduate School Dr. Robert Veillette Dr. Rex D. Ramsier ________________________ Date ii ABSTRACT This thesis presents the design of a temperature and process insensitive CMOS only reference current generator. The proposed reference current generator consists of a conventional CMOS Widlar current source, in which the passive resistor is replaced with a transistor resistor. The gate voltage of the transistor resistor is provided by a gate bias generator that makes the output current insensitive to temperature variation. Furthermore, to achieve a process insensitive reference current, three separate gate bias generator circuits for nominal, strong and weak corners were designed. These gate bias generators are manually selected by the control switches to minimize the current variation under different process corners. As an extension of the manual mode selector, the design of an automatic mode selector that automatically selects the optimum gate bias generators to minimize the current variation under different process corners is realized. The proposed reference current generator can be used for high temperature sensor interface applications that include amplifiers, oscillators, filters and data converters. The proposed reference current generator is designed using 0.5 µm CMOS SOI technology, and the operation has been verified through circuit level simulations. The results show for a reference current of 20 µA, a temperature coefficient of 39 ppm/°C is achieved in the temperature range between 25°C and 125°C for the nominal process corner. Using the mode control circuits for different process corners, worst-case temperature coefficients of 520 ppm/°C and 300 ppm/°C are obtained for the weak and the strong corners, respectively. iii DEDICATION Dedicated to my Parents and Friends. iv ACKNOWLEDGEMENTS First and foremost, I would like to express my sincerest gratitude to my advisor Dr. Kye-Shin Lee for his continues advice, guidance and support throughout my study. He had been guiding me academically and emotionally through the rough road to finish my thesis. During the toughest process of my thesis writing, he also gave me his endearing support, guidance and advice that I needed to complete. I would also specially like to thank my committee members Dr. Joan Carletta and Dr. Robert Veillette for their valuable advice and their continuous support on my thesis. A special person whom I am deeply thankful to is Dr. Alex De Abreu-Garcia, who played a deserving part for my study at The University of Akron. Last but not the least, I would like to express my thankfulness to my family, friends, research assistants and seniors who have supported me and given me an immense amount of motivational support. v TABLE OF CONTENTS Page LIST OF FIGURES ......................................................................................................... viii LIST OF TABLES ...............................................................................................................x CHAPTER I. INTRODUCTION ............................................................................................................1 1.1 Motivation ................................................................................................................. 1 1.2 Goal of thesis ............................................................................................................. 3 1.3 Organization of this thesis ......................................................................................... 4 II. LITERATURE REVIEW ................................................................................................5 2.1 Bandgap reference ..................................................................................................... 5 2.2 MOSFET ZTC point ................................................................................................. 7 2.3 CMOS reference current generator ......................................................................... 10 2.4 Summary of the previous work ............................................................................... 13 2.5 Summary of contribution ........................................................................................ 14 III. PROPOSED CMOS ONLY REFERENCE CURRENT GENERATOR ....................16 3.1 Temperature insensitive operation .......................................................................... 16 3.2 Process insensitive operation .................................................................................. 20 vi 3.3 Simulation results .................................................................................................... 23 IV. AUTOMATIC MODE SELECTION DESIGN ..........................................................25 4.1 The automatic mode selection operation ................................................................. 25 4.2 Current to voltage (I-V) converter .......................................................................... 27 4.3 Mode selector .......................................................................................................... 28 4.3.1 The controller ................................................................................................... 32 4.3.2 Bit serial adder .................................................................................................. 34 4.3.3 Bit serial magnitude comparator....................................................................... 36 4.3.4 Signal generator ................................................................................................ 39 4.3.5 Comparison decoder ......................................................................................... 40 4.4 Simulation results .................................................................................................... 41 V. CONCLUSION .............................................................................................................45 5.1 Summary ................................................................................................................. 45 5.2 Future work ............................................................................................................. 46 BIBLIOGRAPHY ..............................................................................................................47 vii LIST OF FIGURES Figures Page 2.1: Block diagram of reference current generator based on bandgap reference technique 6 2.2: Typical low voltage bandgap reference current using an opamp ................................ 7 2.3: Trans-conductance characteristics of a transistor showing the ZTC point [11] .......... 8 2.4: Proposed 10 bit gate-controlled DAC .......................................................................... 9 2.5: Conventional CMOS reference current generator ..................................................... 11 2.6: Reference current for conventional circuit at different process corners over temperature ....................................................................................................................... 11 2.7: Temperature compensated CMOS current reference ................................................. 12 3.1: The proposed current generator circuit ...................................................................... 17 3.2: Gate bias circuit for different process corners ........................................................... 21 3.3: Reference current with temperature for nominal corner ............................................ 24 4.1: Block diagram of the overall automatic mode selector ............................................. 26 4.2: The reference voltage generator for Mode 1 ............................................................. 27 4.3: The block diagram of the mode selector ................................................................... 29 4.4: The detail block diagram of the automatic mode selector ......................................... 30 4.5: The controller ............................................................................................................. 33 4.6: The state diagram of the controller ............................................................................ 33 viii 4.7: Waveforms of the control signals .............................................................................. 34 4.8: Bit serial adder ........................................................................................................... 35 4.9: Waveforms for the inputs and outputs of the bit serial adder .................................... 36 4.10: Proposed bit serial signed magnitude comparator ................................................... 37 4.11: Comparison decoder logic ....................................................................................... 41 4.12: Simulation results
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