DOCSLIB.ORG

Current Mirrors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

Current mirrors Current mirrors are important blocks in electronics. They are widely used in several applications and chips, the operational amplifier being one of them. Current mirrors consist of two branches that are parallel to each other and create two approximately equal currents. This is why these circuits are called current mirrors. These currents are used to load other stages in circuits and they are designed in such a way so that current is constant and independent of loading. Current mirrors come in different varieties: Simple current mirror (BJT and MOSFET) Base current corrected simple current mirror Widlar current source Wilson current mirror (BJT and MOSFET) Cascoded current mirror (BJT and MOSFET) For best performance, transistors should be matched, temperature should be the same for all devices and collector-base/drain-gate voltages should also be matched. This will provide equal currents on both sides of the current mirror. All of the circuits have a compliance voltage which is the minimum output voltage required to maintain correct circuit operation: the BJT should be in the active/linear region and the MOSFET should be in the active/saturation region. 1 www.ice77.net Simple current mirror Two implementations exist for the simple current mirror: BJT and MOSFET. BJT The BJT implementation of the simple current mirror is used as a block in the operational amplifier. VCC Vo 3.600V 1.472mA R1 VCC Vo IREF Io I 2k 3.600V 650.0mV V1 V2 Q1 3.6Vdc 0.65Vdc 1.425mA Q2 1.425mA 1.425mA 1.472mA 0V 23.47uA 0V I 23.47uA 655.3mV Q2N3642 Q2N3642 0 0 -1.449mA -1.449mA 0V 0 Simple current mirror (BJT) 1.5mA 1.0mA 0.5mA 0A -0.5mA 0V 50mV 100mV 150mV 200mV 250mV 300mV 350mV 400mV 450mV 500mV IC(Q2) -I(R1) V_V2 Simple current mirror currents (BJT) The compliance voltage is roughly given by Vo(min) VCE 2(sat) 0.2V 2 www.ice77.net The collector resistor is given by V V R CC BE1 I REF The collector current is given by V BE V I I e VT 11 CE C S V A From KCL analysis at the collector of Q1, the reference current is defined as I 2 C I REF I C 2I B I C 2 I C 1 o o where βo is the value of β for VCB=0V (Q1 is diode-connected). The output current is given by V BE V I I I e VT 11 CE o C S V A When VCB=0V the Early effect is eliminated and it does not affect the equation. As the value of VCB increases, β values for both transistors no longer match and the output current is no longer flat but it’s tilted with a slope of 1/ro. The output resistance is VA VCE R0 r0 I o 3 www.ice77.net MOSFET The MOSFET implementation of the simple current mirror is as follows: VDD Vo 3.600V 537.8uA R1 VDD Vo IREF Io I 2k 3.600V 2.500V V1 V2 3.6Vdc 2.5Vdc 2.524V 537.8uA 537.8uAM1 M2 537.8uA 537.8uA 0V 0V I 0A 0A M2N6760 M2N6760 0 0 0V 0 Simple current mirror (MOSFET) 600uA 400uA 200uA 0A 0V 0.4V 0.8V 1.2V 1.6V 2.0V 2.4V 2.8V 3.2V 3.6V -I(R1) ID(M2) V_V2 Simple current mirror currents (MOSFET) The parameters for the transistors are W=900n, L=90n and VTN=0.25V. The compliance voltage is roughly given by Vo(min) VDS 2(sat) VGS 2 VTN 2.5V 0.25V 2.25V Note: the subscript N is added to VT to avoid confusion with the thermal voltage (VT=25mV). 4 www.ice77.net The drain resistor is given by V V R DD GS1 I REF Both transistors work in the active/saturation region and their drain current is given by 2 I D K n VGS VTN 1 VDS VGS VTN Since no current enters the gates, reference and output currents match. When VDS-VGS+VTN=0V the channel-length modulation is eliminated and it does not have affect the equation. If the value of VDS-VGS+VTN≠0V, the output current is no longer flat but it’s tilted with a slope of 1/ro. Currents are related by the following expression: I o W2 / L2 1 VDS 2 I REF W1 / L1 1 VDS1 The above relationship says that current in the two branches of the current mirror depends on the aspect ratio of the two transistors. The output resistance is 1 R0 r0 I o 5 www.ice77.net Base current corrected simple current mirror The currents of the BJT implementation of the simple current mirror are somewhat dependent on the value of β for both transistors. In order to minimize this dependency and decrease the error in current matching, a transistor is added to the original simple current mirror circuit. VCC Vo 3.600V 1.194mA VCC R1 3.600V VCC Vo IREF Io I 2k 3.600V 1.200V Q3 38.73uA 1.211V V1 V2 913.6nA Q2N3642 Q1 -39.64uA 3.6Vdc 1.2Vdc 650.5mV 1.193mA Q2 1.193mA 1.193mA 1.233mA 0V 0V I 19.82uA 19.82uA Q2N3642 Q2N3642 0 0 -1.213mA -1.213mA 0V 0 Base current corrected simple current mirror 1.2mA 0.8mA 0.4mA 0A -0.4mA 0V 50mV 100mV 150mV 200mV 250mV 300mV 350mV 400mV 450mV 500mV -I(R1) IC(Q2) V_V2 Base current corrected simple current mirror currents The compliance voltage is roughly given by Vo(min) VCE 2(sat) 0.2V 6 www.ice77.net The collector resistor is given by V V V R CC BE3 BE1 I REF The collector current is given by V BE V I I e VT 11 CE C S V A From KCL analysis at the collector of Q1, the reference current is defined as 2I V V V I I I I C CC BE3 BE1 REF C1 B3 C 1 R The output current is given by V BE V I I I e VT 11 CE o C S V A The output resistance is VA VCE R0 r0 I o Note: the MOSFET implementation of this circuit does not exist since current does not enter the gate of a MOSFET. 7 www.ice77.net Widlar current source The Widlar current source, a variation of the simple current mirror, was advanced by Bob Widlar in the mid 1960s. The only difference between the two circuits is the introduction of an emitter resistor. This additional component forces the currents in the two branches of the circuit to be unequal so this is why the circuit is called a source rather than a mirror. This specific circuit is used as a block in the operational amplifier. VCC Vo 3.600V 1.019mA R1 VCC Vo IREF Io I 2.9k 3.600V 700.0mV V1 V2 Q1 3.6Vdc 0.7Vdc 506.7uA Q2 992.6uA 506.7uA 1.019mA 0V 9.188uA 0V I 16.88uA 645.9mV Q2N3642 Q2N3642 0 0 -1.010mA 515.9uA-515.9uA 17.54mV R2 34 0V 0 Widlar current source 1.2mA 0.8mA 0.4mA 0A -0.4mA 0V 50mV 100mV 150mV 200mV 250mV 300mV 350mV 400mV 450mV 500mV -I(R1) IC(Q2) V_V2 Widlar current source currents Note: the circuit presented here has been designed so that IC1 is twice the value of IC2. The compliance voltage is roughly given by Vo(min) VCE 2(sat) VR2 0.2V I E2 R2 8 www.ice77.net The collector resistor is given by VCC VBE1 R1 I REF The base voltage is defined by VB VBE1 VBE2 I E2 R2 VBE 2 I o R2 The difference in base-emitter voltages is VBE1 VBE2 I o R2 The base-emitter voltages are given by I I REF and o VBE1 VT ln VBE 2 VT ln I S I S Subtracting base-emitter voltages again, I I I REF o REF VBE1 VBE 2 VT ln VT ln VT ln I S I S I o so that I REF VBE1 VBE 2 I o R2 VT ln I o and the emitter resistor is V I T REF R2 ln I o I o Note that if the condition IREF=Io is forced, the argument of the logarithm is 1 which produces 0 and therefore a 0Ω resistance (simple current mirror configuration). This is why reference and output currents do not match. The output resistance is higher than the one for the simple current mirror: Ro ro 1 g m R2 || r Note: the MOSFET implementation of the Widlar current source is not used and if it were, it would behave similarly to the simple current mirrors. 9 www.ice77.net Wilson current mirror Two implementations exist for the Wilson current mirror: BJT and MOSFET. This circuit employs 3 transistors (4 in the improved version). The major advantages of this circuit over the simple current mirror is that it has a higher output impedance and strongly reduces the base error of the BJT implementation. BJT The BJT implementation of the Wilson current mirror was invented by George R. Wilson at Tektronix in 1967. Ro VCC Vo 3.600V 2.266mA R1 IREF Io I VCC Vo 1k Q3 2.245mA 3.600V 1.400V 35.55uA I 1.334V V1 V2 Q2N3642 -2.281mA 3.6Vdc 1.4Vdc Q1 666.9mV 2.245mA 2.266mA 0V Q2 2.230mA 2.210mA 0V 666.9mV 35.07uA 35.07uA 0 0 Q2N3642 Q2N3642 -2.265mA -2.246mA 0V 0V 0 Wilson current mirror (BJT) 4.0mA 2.0mA 0A -2.0mA -4.0mA 0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V 1.6V 1.8V 2.0V -I(R1) IC(Q3) V_V2 Wilson current mirror currents (BJT) 10 www.ice77.net The compliance voltage is roughly given by Vo(min) VBE 2 VCE3(sat) 0.7V 0.2V 0.9V The output resistance is very high and it’s given by r R o3 o 2 An improved version of the above circuit exists.
Recommended publications
  • A Temperature and Process Insensitive Cmos Only Reference

    A Temperature and Process Insensitive Cmos Only Reference

    A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE CURRENT GENERATOR A Thesis Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Master of Science Shivasai Bethi December, 2014 A TEMPERATURE AND PROCESS INSENSITIVE CMOS ONLY REFERENCE CURRENT GENERATOR Shivasai Bethi Thesis Approved: Accepted: ________________________ ________________________ Advisor Department Chair Dr. Kye-shin Lee Dr. Abbas Omar ________________________ ________________________ Committee Member Dean of the College Dr. Joan E. Carletta Dr. George K. Haritos ________________________ ________________________ Committee Member Interim Dean of the Graduate School Dr. Robert Veillette Dr. Rex D. Ramsier ________________________ Date ii ABSTRACT This thesis presents the design of a temperature and process insensitive CMOS only reference current generator. The proposed reference current generator consists of a conventional CMOS Widlar current source, in which the passive resistor is replaced with a transistor resistor. The gate voltage of the transistor resistor is provided by a gate bias generator that makes the output current insensitive to temperature variation. Furthermore, to achieve a process insensitive reference current, three separate gate bias generator circuits for nominal, strong and weak corners were designed. These gate bias generators are manually selected by the control switches to minimize the current variation under different process corners. As an extension of the manual mode selector, the design of an automatic mode selector that automatically selects the optimum gate bias generators to minimize the current variation under different process corners is realized. The proposed reference current generator can be used for high temperature sensor interface applications that include amplifiers, oscillators, filters and data converters.
  • A Low Voltage Very High Impedance Current Mirror Circuit and Its Application

    A Low Voltage Very High Impedance Current Mirror Circuit and Its Application

    ISSN(Online): 2319-8753 ISSN (Print): 2347-6710 International Journal of Innovative Research in Science, Engineering and Technology (A High Impact Factor, Monthly, Peer Reviewed Journal) Visit: www.ijirset.com Vol. 8, Issue 2, February 2019 A Low Voltage Very High Impedance Current Mirror Circuit and Its Application Priya M.K.1, V.K.Vanitha Rugmoni2 M.Tech Scholar, Dept. of ECE, VJCET, Kerala, India1 Asst. Professor, Dept. of ECE, VJCET, Kerala, India2 ABSTRACT: Current mirror circuit has served as the basicbuilding block in analog circuit design since the introduction of integrated circuits. In this paper, “A Very high impedance current mirror, operating in reduced power supply which does not use any additional biasing circuit and its application” is proposed. The design uses a high swing super Wilson current mirror which has negative feedback. A feedback action is used to force the input and output currents to be equal. The output current is expected to be mirrored with a transfer error less than 1% when the input current is increased from 5μA to 40μ A. As an application, the current mirror circuit has been used in the design of a high gain, improved output swing differential amplifier. A telescopic differential amplifier is chosen for designing since it is used in low power application. A comparative study of different current mirror circuits and amplifier is also made. The output swing of the circuit is improved than what is expected. KEYWORDS: Current mirror, Wilson current mirror, Output Impedance, CMRR,Telescopic Differential Amplifier I. INTRODUCTION In the early 1980s many experts predicted the demise of analog circuits.
  • Experiment 2: Discrete BJT Op-Amps (Part I)

    Experiment 2: Discrete BJT Op-Amps (Part I)

    EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2011 C. Nguyen Experiment 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and study the properties of a few circuit blocks commonly used to build operational amplifiers. Because we are limited to using discrete components, we will not be able to construct a complete op-amp. This will be done in the op-amp design project later in the semester. In this lab, however, we will ask you to analyze and design circuits commonly used to make integrated circuit operational amplifiers, and you will use these circuits to build a differential amplifier with both resistive and current mirror biasing. Although built with discrete devices, this op-amp uses a classical topology common to most commercial op- amps including the well-known 741. The operation of these circuits will depend on the use of matched transistors. The CA3083 is a matched NPN transistor array built on a single integrated substrate. To ensure that the transistors are properly isolated, you must connect pin 5 of the array to the most negative point of the circuit (-6 volts). Data sheets for the CA3083, and discrete npn and pnp transistors needed in this lab are attached. In this lab more than any other so far, neatness counts. Unless you build your circuits neatly, they will not operate. Trim your resistor leads if necessary. Make sure that you record all the measurements that you make as you proceed, and include these measurements in your lab report.
  • B.Tech. Biomedical Engineering

    B.Tech. Biomedical Engineering

    RAMA UNIVERSITY UTTAR PRADESH Faculty of Engineering & Technology SYLLABUS & EVALUATION SCHEME [Effective from the Session 2014-15] B.Tech. Biomedical Engineering 2nd, 3rd&4th Year RAMA UNIVERSITY UTTAR PRADESH, KANPUR A meeting of the Board of Studies of the department of B.Tech Biomedical Engineering of Faculty of Engineering and Technology Rama University Uttar Pradesh, Kanpur was held on 5th July 2014 at 11 AM. The following members were present: 1. …………………………………. Convener 2. …………………………………. Member 3. …………………………………. Member 4. ……………………………… External Member 5. ……………………………… External Member The quorum of the meeting was complete. Agenda of the meeting: 1. Assessment Criteria 2. Question Paper Format 3. Syllabus The meeting resolved unanimously that attached Assessment Criteria, Question Paper Format and Syllabus are justified and approved. Convener Signature: ……………………… Name : ……………………….. Date: Internal Members Signature: 1…………………………………. 2……………………………………… Name: Date: External Members Signature: 1……………………………………… 2………………………………………… Name: Date: Rama University Uttar Pradesh, Kanpur Course Detail and Evaluation Scheme (Effective from the Session 2014-15) B. Tech. Biomedical Engineering Year-2 SEMESTER-III EVALUATION Subject Period S.N. Subject Name SCHEME Total Credit Code L T P CE MTE ETE Theory Subjects 1 BAS-301 Mathematics III 3 1 0 20 20 60 100 4 2 BEC-305 Fundamentals of Electronics Devices 3 1 0 20 20 60 100 4 3 BEC-302 Digital Electronics 3 1 0 20 20 60 100 4 4 BEC-306 Electromagnetic Field Theory 3 1 0 20 20 60 100 4 5 BEC-307 Fundamentals of Network Analysis & Synthesis 3 1 0 20 20 60 100 4 Practicals / Project 6 BEC-351 Electronics Engineering Lab I 0 0 2 30 20 50 100 1 7 BEC-352 Digital Electronics Lab-I 0 0 3 30 20 50 100 1 8 BEC-355 PCB & Electronics Workshop 0 0 2 30 20 50 100 1 9 Total 15 5 7 190 160 450 800 23 L-Lecture, T-Tutorial, P- Practical, CE- Continuous Evaluation, MTE-Mid Term Examination, ETE-End Term Examination Evaluation Scheme: Course without practical components For Continuous Evaluation (CE) is such as: 20 Marks 1.
  • Analog Circuits

    Analog Circuits

    Electronics Engineering Analog Circuits Comprehensive Theory with Solved Examples and Practice Questions MADE EASY Publications Corporate Office: 44-A/4, Kalu Sarai (Near Hauz Khas Metro Station), New Delhi-110016 E-mail: [email protected] Contact: 011-45124612, 0-9958995830, 8860378007 Visit us at: www.madeeasypublications.org Analog Circuits © Copyright, by MADE EASY Publications. All rights are reserved. No part of this publication may be reproduced, stored in or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photo-copying, recording or otherwise), without the prior written permission of the above mentioned publisher of this book. First Edition: 2015 Second Edition: 2016 Third Edition: 2017 Fourth Edition: 2018 Fifth Edition: 2019 Sixth Edition: 2020 © All rights reserved by MADE EASY PUBLICATIONS. No part of this book may be reproduced or utilized in any form without the written permission from the publisher. Contents Analog Circuits Chapter 1 Chapter 2 Diode Circuits ������������������������������������������������������ 4 BJT-Characteristics and Biasing ���������������81 1�1 Introduction �������������������������������������������������������������������� 4 2�1 Introduction ������������������������������������������������������������������81 1�2 Diode Circuits : DC Analysis and Models �������������� 4 2�2 Transistors Current Components ���������������������������81 1�3 Diode Logic Gates �������������������������������������������������������11 2�3 Early Effect ���������������������������������������������������������������������85
  • EE 508 OTA Laboratory Experiment

    EE 508 OTA Laboratory Experiment

    EE 508 OTA Laboratory Experiment The Operational Transconductance Amplifier is widely used in integrated amplifier and filter applications. There are also some specific discrete applications where the device can be used. Irrespective whether used in integrated or discrete applications, issues surrounding design and performance are mostly common. There are several discrete OTAs on the market. The CA 3080 and 3092, introduced by RCA, were the first. More recent, the NE 5517 has become quite popular. It is a DUAL OTA with tail bias current control. Another useful OTA is the LM13700 manufactured by National Semiconductor. These devices are particularly useful in the design of voltage or current controlled applications. One of the particularly attractive applications of the OTA is in the design of voltage-controller or current-controlled amplifiers and filters where by a dc voltage or a dc current can be used to control or adjust key characteristics of a filter such as the band edges, the mid-band gain, or the bandwidth. An attached article written a number of years ago is useful at describing some of the signal conditioning strategies needed to used the OTA along with methods of building voltage controlled filters. Part 1 Design and test a voltage controlled amplifier. The gain of the amplifier should be adjustable from +1 to +10 as a control voltage is changed between 1V and 2V Part 2 Design and test a voltage controlled bandpass filter. The bandpass filter should have a Q of 5 and the resonant frequency should be adjustable between 1KHz and 20KHz as the dc control voltage changes between 1V and 2V.
  • Syllabus Applicable in Gautam Buddh Technical University Lucknow Is

    Syllabus Applicable in Gautam Buddh Technical University Lucknow Is

    SyllabusApplicable in GautamBuddhTechnicalUniversity Lucknow isadoptedbytheExecutiveCouncilof MahamayaTechnicalUniversity Noida videresolutionno.13,dated24Feb,2011 forbatchesadmittedinsession:2010-11 B.TECH. BIO-MEDICALENGINEERING 2nd, 3rd and 4th Year MAHAMAYATECHNICAL UNIVERSITY, NOIDA SYLLABUS & EVALUATION SCHEME FOR BIOMEDICAL ENGINEERING (B.Tech. Course) Year II, Semester III Evaluation Scheme S.No. SUBJECT PERIODS SESSIONAL Course Code Subject EXAM. ESE Total L T P CT TA Total THEORY SUBJECTS 1. EHU-301/ Industrial Psychology/ 2 0 0 15 10 25 50 75 2 EHU-302 Industrial Sociology 2. EAS-301/ EOE-Mathematics III/ Science 3 1 0 30 20 50 100 150 4 031-EOE-038 based open Elective** 3. EEC-301 Fundamentals of 3 1 0 30 20 50 100 150 4 Electronics Devices 4. EEC-302 Digital Electronics 3 1 0 30 20 50 100 150 4 5. EEC-303 Electromagnetic Field 3 1 0 30 20 50 100 150 4 Theory 6. EEC-304 Fundamentals of Network 3 1 0 30 20 50 100 150 4 Analysis & Synthesis 7. EHU-111 *Human Values & 2 2 0 15 10 25 50 75 - Professional Ethics PRACTICAL/DESIGN/DRAWING 8 EEC-351 Electronics Engineering 0 0 2 -- 20 20 30 50 1 Lab I 9. EEC-352 Digital Electronics Lab-I 0 0 2 -- 20 20 30 50 1 10. EEC-353 PCB & Electronics 0 0 2 -- 10 10 15 25 1 Workshop 11. GP-301 General Proficiency - - - - - 50 - 50 1 Total 17 5 6 165 160 375 625 1000 26 * Human Values & Professional Ethics will be offered as compulsory Audit Course for which passingmarks are 40% in theory & 50% in aggregate.
  • Detailed Table of Contents

    Detailed Table of Contents

    Analog Circuit Design Discrete and Integrated Sergio Franco San Francisco State University McGraw-Hill Education, 2015 ISBN 978-0-07-802819-9 Detailed Table of Contents 1 DIODES AND THE PN JUNCTION 1.1 The Ideal Diode: Finding the Operating Mode of a Diode, Cut-and-Try Approach, Concluding Observations 1.2 Basic Diode Applications: Rectifiers, Logic Gates, Peak Detectors, The Clamped Capacitor or DC Restorer, Voltage Multipliers and PSpice Simulation 1.3 Operational Amplifiers and Diode Applications: Basic Op Amp Circuits, Our First Diode/Op- Amp Circuit 1.4 Semiconductors: Doping, Drift and Diffusion Currents, An Example: The Integrated-Circuit Diode 1.5 The pn Junction in Equilibrium: Equilibrium Conditions, The Built-in Potential φ0, The Electric Field E0, The SCL Width Xd0, and the SCL Charge Qj0 1.6 Effect of External Bias on the SCL Parameters: The Junction Capacitance Cj 1.7 The pn Diode Equation: Excess Minority Concentrations, The Diode Equation, Short-Base Diodes 1.8 The Reverse-Biased pn Junction: Reverse Breakdown 1.9 Forward-Biased Diode Characteristics: Properties of the Exponential Characteristic, Temperature Dependence, Deviations from Ideality 1.10 Dc Analysis of pn Diode Circuits: Load-Line Analysis, Iterative Analysis, Piecewise-Linear Approximations and Large-Signal Diode Models, Circuit Analysis Using the Piecewise-Linear Approximation, The pn Junction Diode as a Rectifier, the Superdiode 1.11 Ac Analysis of pn Diode Circuits: Small-Signal Operation, The Small-Signal Diode Model, The pn Diode as a Current-Controlled
  • Electronically Tunable Multi-Terminal Floating Nullor and Its Applications

    Electronically Tunable Multi-Terminal Floating Nullor and Its Applications

    RADIOENGINEERING, VOL. 17, NO. 4, DECEMBER 2008 3 Electronically Tunable Multi-Terminal Floating Nullor and Its Applications Worapong TANGSRIRAT Faculty of Engineering , King Mongkut’s Institute of Technology Ladkrabang (KMITL), Chlongkrung Rd., Ladkrabang, Bangkok 10520, Thailand [email protected] Abstract. A realization scheme of an electronically tun- conventional operational amplifier (op-amp) and the com- able multi-terminal floating nullor (ET-MTFN) is de- mercial operational transconductance amplifier (OTA) as scribed in this paper. The proposed circuit mainly employs the major active component, these configurations are less a transconductance amplifier, an improved translinear appropriate for high-frequency applications and uneco- cell, two complementary current mirrors with variable nomical for applying to an IC fabrication. Recently, there current gain and improved Wilson current mirrors, which has been much effort to construct the FTFN with multi- provide an electronic tuning of the current gain. The va- output terminals [11]. In general, if the multi-output type lidity of the performance of the scheme is verified through active components are employed, the number of compo- PSPICE simulation results. Example applications nents that constitutes a configuration may be reduced and employing the proposed ET-MTFN as an active element the resulting circuit may be miniaturized [12]. demonstrate that the circuit properties can be varied by This paper describes an alternative realization scheme electronic means. for realizing a monolithically integrable multi-output FTFN or multi-terminal floating nullor (MTFN), which provides electronically variable current gain. The proposed circuit is Keywords based on the use of a transconductance amplifier, an im- proved translinear cell and some current mirrors.
  • Anna University, Chennai University Departments B.E. Electronics and Communication Engineering Regulations – 2019 Vision

    Anna University, Chennai University Departments B.E. Electronics and Communication Engineering Regulations – 2019 Vision

    ANNA UNIVERSITY, CHENNAI UNIVERSITY DEPARTMENTS B.E. ELECTRONICS AND COMMUNICATION ENGINEERING REGULATIONS – 2019 VISION The Department of ECE shall strive continuously to create highly motivated, technologically competent engineers, be a benchmark and a trend setter in Electronics and Communication Engineering by imparting quality education with interwoven input from academic institutions, research organizations and industries, keeping in phase with rapidly changing technologies imbibing ethical values. MISSION Imparting quality technical education through flexible student centric curriculum evolved continuously for students of ECE with diverse backgrounds. Providing good academic ambience by adopting best teaching and learning practices. Providing congenial ambience in inculcating critical thinking with a quest for creativity, innovation, research and development activities. Enhancing collaborative activities with academia, research institutions and industries by nurturing ethical entrepreneurship and leadership qualities. Nurturing continuous learning in the stat-of-the-art technologies and global outreach programmes resulting in competent world class engineers. 1 ANNA UNIVERSITY, CHENNAI UNIVERSITY DEPARTMENTS B.E. ELECTRONICS AND COMMUNICATION ENGINEERING REGULATIONS – 2019 The Programme defines Programme Educational Objectives, Programme Outcomes and Programme Specific Outcomes as follows: 1. PROGRAMME EDUCATIONAL OBJECTIVES (PEOs): PEO1 Equip the students with sufficient theoretical, analytical and initiative skills in Basic Sciences and Engineering necessary, to assimilate, analyze, synthesis and innovate solutions to meet societal needs. PEO2 To provide adequate research ambience enabling the students to inculcate thirst for life long learning and sustained research interest. PEO3 To instill and practice values, leadership qualities and team spirit to promote entrepreneurship and indigenization. After the course duration of four years, B.E. graduates of Electronics and Communication Engineering will exhibit the following outcomes: 2.
  • Widlar Current Mirror Design Using BJT-Memristor Circuits

    Widlar Current Mirror Design Using BJT-Memristor Circuits

    1 Widlar Current Mirror Design Using BJT-Memristor Circuits Amanzhol Daribay and Irina Dolzhikova, Electrical and Computer Engineering Department, Nazarbayev University, Astana, Kazakhstan [email protected], [email protected] Abstract—This paper presents a description of basic current is calculated to be Rout = V=I = 100=1mA = 100kOhm. mirror (CM), Widlar current mirror, fourth circuit element It is known that Basic BJT CM is aimed to supply nearly (memristor) and an analysis of Widlar Configuration with integrated memristor. The analysis has been performed by comparing a modified configuration with a simple circuit of Widlar CM. The focus of analysis were a power dissipation, a Total Harmonic Distortion and a chip-surface. The results has shown that a presence of memristor in the Widlar CM decreases the chip-surface area and the deviation of the signal in the circuit from a fundamental frequency. Although the analysis of power dissipation has also been conducted, there is no definite conclusion about the power losses in the circuit because of the memristor model. Index Terms—current mirror, Widlar current source, bjt- memristor circuit, power analysis, noise analysis, total harmonic distortion. Figure 2. Basic BJT CM schematic I. INTRODUCTION constant current to a load over a wide range of load resistances. A. Basic Current Mirror Since in LTSpice it is more convenient to change some output over varying DC voltage with specified increment in Basically, current mirrors (CMs) are used to mirror a LTSpice, in order to observe mirrored current Ic(Q2) , it has reference current multiple times from one designated source been established different loading conditions by changing load into another consuming circuits.
  • Section G2: Current Sources and Active Loads

    Section G2: Current Sources and Active Loads

    Section G2: Current Sources and Active Loads The transistor biasing techniques introduced in earlier sections are not suitable for the design of IC amplifiers since, even for a relatively simple multistage amplification system, many resistors and large capacitors are required. This is problematic for a couple of reasons, most importantly the cost of chip “real-estate” and fabrication concerns. However, fabrication of simple transistors has become cheap and easy, as well as providing the ability to have a large number of transistors with matched characteristics. Therefore, biasing in integrated circuit (IC) design is based on the use of transistors configured to act as constant current sources. On a multistage amplifier IC chip, a constant dc current source is generated at one location and is then reproduced at different locations for biasing the various amplification stages. The major advantages to this approach include: ¾ the requirement for resistors, coupling capacitors and bypass capacitors is removed; and ¾ the biasing of the multiple stages track each other in case of parameter changes, such as voltage supply or temperature fluctuations. In this section, we will be looking at several methods of providing a constant dc current source for amplifier biasing using simple transistor configurations. Many of the circuits used to generate bias currents are also used for providing large resistances for IC applications. The active loads created in this manner, as well as the dc current sources, are small and easy to fabricate on IC chips. Diode Connected Transistors Before we get into current sources, let’s take a little bit to look at the details of the diode-connected transistor.