1. Current Mirrors

Analog Integrated Circuits – Fundamental Building Blocks Current mirrors 1. Current mirrors All the circuits studied in the previous paragraphs were simple, controlled current sources. Their analysis has been done under the assumption that all the transistors are correctly biased in the saturation region. The issue, that has not been discussed, is the method used to insure the correct biasing of the transistors. Practically the biasing conditions are reduced to the generation of all the constant voltages in the circuit. The vast majority of the gate potentials are generated by injecting a reference current in one or more diodes connected in series. The voltage drop on these diodes will serve for stabilizing the gate-source voltages of the transistors in the current source. The resulting class of sub-circuits is called current mirrors. The current mirrors are particularly useful for the distribution of bias currents in larger circuits. They can also be employed as current amplifiers. The basic parameter that describes the functionality of a current mirror is its current gain or reflection coefficient. The current gain is defined as a ratio between the generated output current and the input reference current. I n out (1) Iin The performance requirements for current mirrors are similar as for current sources: the output resistance must be as large as possible in order to reduce the dependence of the output current on the output voltage; the input resistance must be as small as possible; the minimum allowed output voltage must be as small as possible; the minimum input voltage must be also as small as possible; the current gain must be precisely defined, constant with the supply voltage and temperature independent. The following paragraphs present the most important current mirror structures. The emphasis lays on the analysis of the circuits based on the parameters listed above and on the methods used to improve the performances. Some of the effects, that will be considered during the analysis, are the channel length modulation (Early effect) and the transistor mismatch. 1.1. MOS current mirrors 1.1.1. The simple MOS current mirror The simple current mirror can be obtained from the one transistor current source by using a second transistor in diode connection that generates the necessary gate-source voltage of the transistor in the output stage. The gate source voltage is set by the diode geometry and the injected input or reference current. Since the gates and the sources of the two transistor are connected together the gate-source voltage of the current source will be equal to the gate source voltage of the diode. The schematic of the circuit is given in Figure 1. The corresponding small signal equivalent model is shown in Figure 2. Figure 1. NMOS and PMOS implementations of a simple current mirror 1 Analog Integrated Circuits – Fundamental Building Blocks Current mirrors Figure 2. The small signal equivalent model of the simple MOS current mirror The calculation of the current gain n starts with the expressions of the input and of the output currents. IIVVV 2 1 in D1 1 GS 1 Th 1 DS 1 2 IIVVV 1 (2) out D2 2 GS 2 Th 2 DS 2 CWCWox1 ox 2 1; 2 2LL1 2 2 If the gate-source voltages of the transistors are assumed to be equal, the current gain results 2 I VVV 1 n out 2GS Th 2 DS 2 (3) I 2 in 1VVVGS Th 1 1 DS 1 The input resistance of the mirror can be determined from the small signal equivalent model. First the input voltage is written as a function of the input current: Vin I in I1 r DS 1 I in g m 1 V GS 1 r DS 1 (4) The gate-source voltage VGS1 of the transistor M1 can be identified from the schematic as the input voltage. By replacing VGS1 with Vin in the equation (4) the input resistance results: Vin r DS1 1 Rin (5) Iin1 g m1 r DS 1 g m 1 The output resistance can be calculated with a similar method as for a simple, one transistor current source. The final expression of the output resistance is Vout Rout r DS1 (6) Iout The minimum allowed output voltage is defined similarly as for the simple, one transistor current source and is equal to the drain-source voltage of the transistor M2 at which the device is still biased in the saturation region. When taking a closer look to the equation (3) it can be noticed that there are three independent factors that can affect the value of the current gain. These factors are the channel length modulation (Early effect), the threshold voltage mismatch and the geometrical mismatch of the transistors. The theorem of superposi- tion can be used to emphasize each effect. In order to clearly see the consequences of channel length modulation, the transistor geometries and the threshold voltages are considered perfectly matched. In this case the current gain of the mirror is 1 V n DS 2 (7) 1 VDS1 2 Analog Integrated Circuits – Fundamental Building Blocks Current mirrors It results that the drain-source voltages of the two transistors must be balanced in order to reduce the influence of the channel length modulation. Figure 3 shows the typical variation of the current gain plotted against the mirror input-output voltage mismatch, equal to the drain source voltage difference of the transistors (Vout−Vin=VDS2−VDS1). Figure 3. Variation of the current gain against the input-output voltage imbalance It can be seen that, for equal input and output voltages, the current gain is equal to unity. It can also be noticed that a 1V voltage imbalance can produce an error approximately equal to 9%. The 1V voltage difference may appear relatively easily in biasing circuits where the mirror is used for changing the sign of a given bias current. Usually in these cases the two branches of the circuit will see different load resistances and, as a consequence, the voltage drops will be imbalanced. The analysis of the current gain errors caused by geometry and threshold voltage mismatch can be per- formed when considering the input-output (and implicitly the drain-source) voltages perfectly balanced. In this case the error is not influenced by the channel length modulation effect. In the calculations it is assumed that the threshold voltage mismatch is ΔVTh and the geometry mismatch is translated to Δβ. For the threshold voltages it holds true that 1 1 VV VVVVVVV ;; Th1 Th 2 (8) Th1 Th2 Th Th 2 Th 2 Th Th 2 Similar equations can be written also for the β-s of the transistors: 1 1 ;; 1 2 (9) 12 2 2 2 By replacing the expressions in the equation (3) the current gain results: 2 1 1 VVVGS Th Th Iout 2 2 n 2 (10) Iin 1 1 VVV 2 GS Th 2 Th Writing the threshold voltage and β as common terms for the numerator and the denominator leads to 2 V 1 1 Th 2 2 VV Iout GS Th n (11) I 2 in VTh 1 1 2 2VVGS Th 3 Analog Integrated Circuits – Fundamental Building Blocks Current mirrors For further calculations let us consider the inverse binomial function and its Taylor series expansion, given by the following equation: 1 xk 1 x x2 x 3 (12) k1 2 3 4 x ak 0 a a a a a For low mismatch between the transistors, if Δβ << β and ΔVTh << 2(VGS-VTh), the second and higher order terms of the series can be neglected and the expression of the current gain may be approximated as 2 4 VTh n 1 1 (13) 2 2VVGS Th After squaring the expressions and successively neglecting second order terms the current gain can be approximated as given in the following equation: 2V n 1 Th (14) 2 VVGS Th It results that the precision of the current gain can be improved if the transistors are sized for larger geometries or their drain currents are increased. In practice, an increase of the bias current either leads to higher consumption or the current value may be imposed by design specifications. Therefore, if operating frequency and circuit area limitations are not an issue, larger geometries are always preferred for better device matching. Typically, the owner of the fabrication facility and the target process indicates the minimum transistor area that should be used for a matching better than ±3σ. The minimum area is obtained after statistical measurements. A ±3σ matching means transistors identical to an extent approximately equal to 99,7% (considering a gaussian statistical distribution of the geometry errors). As a summary on the performances of the simple current mirror it can be concluded that not all the requirements listed at the beginning of this section are entirely and unconditionally satisfied. If necessary, a better precision of the current gain can be obtained by employing a structure that allows the balancing of the transistor drain-source voltages. The output resistance also needs improvement as a heritage from the simple current source output stage. One often used procedure, that reduces these deficiencies, is cascoding. 1.1.2. The cascode MOS current mirror The cascode current mirror is derived from the simple current mirror by cascoding both branches of the circuit. The schematic of the resulting structure is given in Figure 4. Figure 4. NMOS and PMOS implementations of a cascode current mirror The bulk terminal of the transistors is connected either to the lowest potential, or to VDD for PMOS transistors.

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