LM1881 Video Sync Separator Datasheet
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Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LM1881 SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 LM1881 Video Sync Separator 1 Features 3 Description The LM1881 Video sync separator extracts timing 1• AC Coupled Composite Input Signal information including composite and vertical sync, • >10-kΩ Input Resistance burst or back porch timing, and odd and even field • <10-mA Power Supply Drain Current information from standard negative going sync NTSC, • Composite Sync and Vertical Outputs PAL (1) and SECAM video signals with amplitude from • Odd and Even Field Output 0.5-V to 2-V p-p. The integrated circuit is also capable of providing sync separation for non- • Burst Gate or Back Porch Output standard, faster horizontal rate video signals. The • Horizontal Scan Rates to 150 kHz vertical output is produced on the rising edge of the • Edge Triggered Vertical Output first serration in the vertical sync period. A default vertical output is produced after a time delay if the • Default Triggered Vertical Output for Non- rising edge mentioned above does not occur within Standard Video Signal (Video Games-Home the externally set delay period, such as might be the Computers) case for a non-standard video signal. 2 Applications Device Information(1) • Video Cameras and Recorders PART NUMBER PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm • Broadcasting Systems LM1881 • Set-Top Boxes PDIP (8) 9.81 mm × 6.35 mm • Home Entertainment (1) For all available packages, see the orderable addendum at the end of the data sheet. • Computing and Gaming Applications (1) PAL in this datasheet refers to European broadcast TV standard “Phase Alternating Line”, and not to Programmable Array Logic. Typical Connection Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM1881 SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 www.ti.com Table of Contents 1 Features .................................................................. 1 7.2 Functional Block Diagram ......................................... 6 2 Applications ........................................................... 1 7.3 Feature Description................................................... 7 3 Description ............................................................. 1 7.4 Device Functional Modes........................................ 10 4 Revision History..................................................... 2 8 Application and Implementation ........................ 11 5 Pin Configuration and Functions ......................... 3 8.1 Application Information............................................ 11 8.2 Typical Applications ................................................ 11 6 Specifications......................................................... 3 6.1 Absolute Maximum Ratings ...................................... 3 9 Power Supply Recommendations...................... 13 6.2 ESD Ratings.............................................................. 4 10 Device and Documentation Support ................. 14 6.3 Recommended Operating Conditions....................... 4 10.1 Community Resources.......................................... 14 6.4 Electrical Characteristics LM1881............................. 4 10.2 Trademarks ........................................................... 14 6.5 Dissipation Ratings ................................................... 4 10.3 Electrostatic Discharge Caution............................ 14 6.6 Typical Characteristics.............................................. 5 10.4 Glossary ................................................................ 14 7 Detailed Description .............................................. 6 11 Mechanical, Packaging, and Orderable 7.1 Overview ................................................................... 6 Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2013) to Revision G Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision E (March 2013) to Revision F Page • Changed layout of National Data Sheet to TI format ........................................................................................................... 13 2 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: LM1881 LM1881 www.ti.com SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 5 Pin Configuration and Functions D and P Packages 8-Pin SOIC and PDIP Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 CSOUT Output Composite Sync Output 2 CVIN Input Composite Video Input 3 VSOUT Output Vertical Sync Output 4 GND — Ground 5 BPOUT Output Burst or Back Porch Timing Output 6 RSET Input Charge Current External Resistor 7 OEOUT Output Odd and Even Field Output 8 VCC Input Supply Voltage 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply Voltage 13.2 V Input Voltage 3 V 6 V P-P P-P V (VCC = 5) (VCC ≥ 8) Output Sink Currents; Pins, 1, 3, 5 5 mA Output Sink Current; Pin 7 2 mA PDIP Package (10 sec.) 260 Soldering Information Vapor Phase (60 sec.) 215 °C SOIC Package Infrared (15 sec.) 220 Storage temperature, Tstg −65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM1881 LM1881 SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 www.ti.com 6.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Machine Model ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Operating free-air temperature 0 70 °C 6.4 Electrical Characteristics LM1881 VCC = 5 V; RSET = 680 kΩ; TA = 0°C to +70°C by correlation with 100% electrical testing at TA=25°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Supply Current Outputs at VCC = 5 V 5.2 10 Logic 1 mA VCC = 12 V 5.5 12 DC Input Voltage Pin 2 1.3 1.5 1.8 V Input Threshold Voltage See (2) 55 70 85 mV Input Discharge Current Pin 2; VIN = 2 V 6 11 16 µA Input Clamp Charge Current Pin 2; VIN = 1 V 0.2 0.8 mA (3) RSET Pin Reference Voltage Pin 6; 1.1 1.22 1.35 V Composite Sync. & Vertical IOUT = 40 µA; VCC = 5 V 4.0 4.5 Outputs Logic 1 V VCC = 12 V 11 IOUT = 1.6 mA VCC = 5 V 2.4 3.6 Logic 1 V VCC = 12 V 10 Burst Gate and Odd and Even IOUT = 40 µA; VCC = 5 V 4 4.5 Outputs Logic 1 V VCC = 12 V 11 Composite Sync. Output IOUT = −1.6 mA; Logic 0; Pin 1 0.2 0.8 V Vertical Sync. Output IOUT = −1.6 mA; Logic 0; Pin 3 0.2 0.8 V Burst Gate Output IOUT = −1.6 mA; Logic 0; Pin 5 0.2 0.8 V Odd and Even Output IOUT = −1.6 mA; Logic 0; Pin 7 0.2 0.8 V Vertical Sync Width 190 230 300 µs Burst Gate Width 2.7 kΩ from Pin 5 to VCC 2.5 4 4.7 µs Vertical Default Time See (4) 32 65 90 µs (1) Typicals are at TJ = 25°C and represent the most likely parametric norm. (2) Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse. (3) Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the RSET pin (Pin 6). (4) Delay time between the start of vertical sync (at input) and the vertical output pulse. 6.5 Dissipation Ratings MIN MAX UNIT Package Dissipation(1) 1100 mW (1) For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a package thermal resistance of 110°C/W, junction to ambient. 4 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: LM1881 LM1881 www.ti.com SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 6.6 Typical Characteristics Figure 1. RSET Value Selection vs Vertical Serration Pulse Figure 2. Vertical Default Sync Delay Time vs RSET Separation Figure 4. Vertical Pulse Width vs R Figure 3. Burst or Black Level Gate Time vs RSET SET 500 s) P 400 300 200 VERTICAL PULSE WIDTH ( WIDTH PULSE VERTICAL 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 5. Vertical Pulse Width vs Temperature Figure 6. Supply Current vs Supply Voltage Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM1881 LM1881 SNLS384G –FEBRUARY 1995–REVISED JUNE 2015 www.ti.com 7 Detailed Description 7.1 Overview The LM1881 is designed to strip the synchronization